arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         set_lpmode_selfrefresh(EMIF2_BASE);
  41 }
  42
  43 inline u32 emif_num(u32 base)
  44 {
  45         if (base == EMIF1_BASE)
  46                 return 1;
  47         else if (base == EMIF2_BASE)
  48                 return 2;
  49         else
  50                 return 0;
  51 }
  52
  53 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  54 {
  55         u32 mr;
  56         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  57
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  60         if (omap_revision() == OMAP4430_ES2_0)
  61                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  62         else
  63                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  64         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  65               cs, mr_addr, mr);
  66         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  67             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  68             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  69                 return mr & 0xff;
  70         else
  71                 return mr;
  72 }
  73
  74 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  75 {
  76         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  77
  78         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  79         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  80         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  81 }
  82
  83 void emif_reset_phy(u32 base)
  84 {
  85         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  86         u32 iodft;
  87
  88         iodft = readl(&emif->emif_iodft_tlgc);
  89         iodft |= EMIF_REG_RESET_PHY_MASK;
  90         writel(iodft, &emif->emif_iodft_tlgc);
  91 }
  92
  93 static void do_lpddr2_init(u32 base, u32 cs)
  94 {
  95         u32 mr_addr;
  96         const struct lpddr2_mr_regs *mr_regs;
  97
  98         get_lpddr2_mr_regs(&mr_regs);
  99         /* Wait till device auto initialization is complete */
 100         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 101                 ;
 102         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 103         /*
 104          * tZQINIT = 1 us
 105          * Enough loops assuming a maximum of 2GHz
 106          */
 107
 108         sdelay(2000);
 109
 110         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 111         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 112
 113         /*
 114          * Enable refresh along with writing MR2
 115          * Encoding of RL in MR2 is (RL - 2)
 116          */
 117         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 118         set_mr(base, cs, mr_addr, mr_regs->mr2);
 119
 120         if (mr_regs->mr3 > 0)
 121                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 122 }
 123
 124 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 125 {
 126         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 127
 128         /* Not NVM */
 129         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 130
 131         /*
 132          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 133          * when EMIF_SDRAM_CONFIG register is written
 134          */
 135         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 136
 137         /*
 138          * Set the SDRAM_CONFIG and PHY_CTRL for the
 139          * un-locked frequency & default RL
 140          */
 141         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 142         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 143
 144         do_ext_phy_settings(base, regs);
 145
 146         do_lpddr2_init(base, CS0);
 147         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 148                 do_lpddr2_init(base, CS1);
 149
 150         writel(regs->sdram_config, &emif->emif_sdram_config);
 151         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 152
 153         /* Enable refresh now */
 154         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 155
 156         }
 157
 158 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 159 {
 160 }
 161
 162 void emif_update_timings(u32 base, const struct emif_regs *regs)
 163 {
 164         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 165
 166         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 167         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 168         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 169         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 170         if (omap_revision() == OMAP4430_ES1_0) {
 171                 /* ES1 bug EMIF should be in force idle during freq_update */
 172                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 173         } else {
 174                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 175                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 176         }
 177         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 178         writel(regs->zq_config, &emif->emif_zq_config);
 179         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 180         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 181
 182         if ((omap_revision() >= OMAP5430_ES1_0) || is_dra7xx()) {
 183                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 184                         &emif->emif_l3_config);
 185         } else if (omap_revision() >= OMAP4460_ES1_0) {
 186                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 187                         &emif->emif_l3_config);
 188         } else {
 189                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 190                         &emif->emif_l3_config);
 191         }
 192 }
 193
 194 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 195 {
 196         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 197
 198         /* keep sdram in self-refresh */
 199         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 200                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 201         __udelay(130);
 202
 203         /*
 204          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 205          * Invert clock adds an additional half cycle delay on the
 206          * command interface.  The additional half cycle, is usually
 207          * meant to enable leveling in the situation that DQS is later
 208          * than CK on the board.It also helps provide some additional
 209          * margin for leveling.
 210          */
 211         writel(regs->emif_ddr_phy_ctlr_1,
 212                &emif->emif_ddr_phy_ctrl_1);
 213
 214         writel(regs->emif_ddr_phy_ctlr_1,
 215                &emif->emif_ddr_phy_ctrl_1_shdw);
 216         __udelay(130);
 217
 218         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 219                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 220
 221         /* Launch Full leveling */
 222         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 223
 224         /* Wait till full leveling is complete */
 225         readl(&emif->emif_rd_wr_lvl_ctl);
 226               __udelay(130);
 227
 228         /* Read data eye leveling no of samples */
 229         config_data_eye_leveling_samples(base);
 230
 231         /*
 232          * Launch 8 incremental WR_LVL- to compensate for
 233          * PHY limitation.
 234          */
 235         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 236                &emif->emif_rd_wr_lvl_ctl);
 237
 238         __udelay(130);
 239
 240         /* Launch Incremental leveling */
 241         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 242                __udelay(130);
 243 }
 244
 245 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 246 {
 247         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 248
 249         u32 fifo_reg;
 250
 251         fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
 252         writel(fifo_reg | 0x00000100,
 253                &emif->emif_ddr_fifo_misaligned_clear_1);
 254
 255         fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
 256         writel(fifo_reg | 0x00000100,
 257                &emif->emif_ddr_fifo_misaligned_clear_2);
 258
 259         /* Launch Full leveling */
 260         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 261
 262         /* Wait till full leveling is complete */
 263         readl(&emif->emif_rd_wr_lvl_ctl);
 264               __udelay(130);
 265
 266         /* Read data eye leveling no of samples */
 267         config_data_eye_leveling_samples(base);
 268
 269         /*
 270          * Disable leveling. This is because if leveling is kept
 271          * enabled, then PHY triggers a false leveling during
 272          * EMIF-idle scenario which results in wrong delay
 273          * values getting updated. After this the EMIF becomes
 274          * unaccessible. So disable it after the first time
 275          */
 276         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 277 }
 278
 279 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 280 {
 281         if (is_omap54xx())
 282                 omap5_ddr3_leveling(base, regs);
 283         else
 284                 dra7_ddr3_leveling(base, regs);
 285 }
 286
 287 static void ddr3_init(u32 base, const struct emif_regs *regs)
 288 {
 289         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 290
 291         /*
 292          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 293          * and RL =7. As the default values of the Mode Registers are not
 294          * defined, contents of mode Registers must be fully initialized.
 295          * H/W takes care of this initialization
 296          */
 297         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 298
 299         /* Update timing registers */
 300         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 301         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 302         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 303
 304         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 305         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 306
 307         /*
 308          * The same sequence should work on OMAP5432 as well. But strange that
 309          * it is not working
 310          */
 311         if (is_dra7xx()) {
 312                 do_ext_phy_settings(base, regs);
 313                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 314                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 315         } else {
 316                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 317                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 318                 do_ext_phy_settings(base, regs);
 319         }
 320
 321         /* enable leveling */
 322         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 323
 324         ddr3_leveling(base, regs);
 325 }
 326
 327 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 328 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 329
 330 /*
 331  * Organization and refresh requirements for LPDDR2 devices of different
 332  * types and densities. Derived from JESD209-2 section 2.4
 333  */
 334 const struct lpddr2_addressing addressing_table[] = {
 335         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 336         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 337         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 338         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 339         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 340         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 341         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 342         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 343         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 344         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 345         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 346 };
 347
 348 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 349         8,                      /* 64Mb */
 350         16,                     /* 128Mb */
 351         32,                     /* 256Mb */
 352         64,                     /* 512Mb */
 353         128,                    /* 1Gb   */
 354         256,                    /* 2Gb   */
 355         512,                    /* 4Gb   */
 356         1024,                   /* 8Gb   */
 357         2048,                   /* 16Gb  */
 358         4096                    /* 32Gb  */
 359 };
 360
 361 /*
 362  * Calculate the period of DDR clock from frequency value and set the
 363  * denominator and numerator in global variables for easy access later
 364  */
 365 static void set_ddr_clk_period(u32 freq)
 366 {
 367         /*
 368          * period = 1/freq
 369          * period_in_ns = 10^9/freq
 370          */
 371         *T_num = 1000000000;
 372         *T_den = freq;
 373         cancel_out(T_num, T_den, 200);
 374
 375 }
 376
 377 /*
 378  * Convert time in nano seconds to number of cycles of DDR clock
 379  */
 380 static inline u32 ns_2_cycles(u32 ns)
 381 {
 382         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 383 }
 384
 385 /*
 386  * ns_2_cycles with the difference that the time passed is 2 times the actual
 387  * value(to avoid fractions). The cycles returned is for the original value of
 388  * the timing parameter
 389  */
 390 static inline u32 ns_x2_2_cycles(u32 ns)
 391 {
 392         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 393 }
 394
 395 /*
 396  * Find addressing table index based on the device's type(S2 or S4) and
 397  * density
 398  */
 399 s8 addressing_table_index(u8 type, u8 density, u8 width)
 400 {
 401         u8 index;
 402         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 403                 return -1;
 404
 405         /*
 406          * Look at the way ADDR_TABLE_INDEX* values have been defined
 407          * in emif.h compared to LPDDR2_DENSITY_* values
 408          * The table is layed out in the increasing order of density
 409          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 410          * at the end
 411          */
 412         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 413                 index = ADDR_TABLE_INDEX1GS2;
 414         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 415                 index = ADDR_TABLE_INDEX2GS2;
 416         else
 417                 index = density;
 418
 419         debug("emif: addressing table index %d\n", index);
 420
 421         return index;
 422 }
 423
 424 /*
 425  * Find the the right timing table from the array of timing
 426  * tables of the device using DDR clock frequency
 427  */
 428 static const struct lpddr2_ac_timings *get_timings_table(const struct
 429                         lpddr2_ac_timings const *const *device_timings,
 430                         u32 freq)
 431 {
 432         u32 i, temp, freq_nearest;
 433         const struct lpddr2_ac_timings *timings = 0;
 434
 435         emif_assert(freq <= MAX_LPDDR2_FREQ);
 436         emif_assert(device_timings);
 437
 438         /*
 439          * Start with the maximum allowed frequency - that is always safe
 440          */
 441         freq_nearest = MAX_LPDDR2_FREQ;
 442         /*
 443          * Find the timings table that has the max frequency value:
 444          *   i.  Above or equal to the DDR frequency - safe
 445          *   ii. The lowest that satisfies condition (i) - optimal
 446          */
 447         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 448                 temp = device_timings[i]->max_freq;
 449                 if ((temp >= freq) && (temp <= freq_nearest)) {
 450                         freq_nearest = temp;
 451                         timings = device_timings[i];
 452                 }
 453         }
 454         debug("emif: timings table: %d\n", freq_nearest);
 455         return timings;
 456 }
 457
 458 /*
 459  * Finds the value of emif_sdram_config_reg
 460  * All parameters are programmed based on the device on CS0.
 461  * If there is a device on CS1, it will be same as that on CS0 or
 462  * it will be NVM. We don't support NVM yet.
 463  * If cs1_device pointer is NULL it is assumed that there is no device
 464  * on CS1
 465  */
 466 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 467                                 const struct lpddr2_device_details *cs1_device,
 468                                 const struct lpddr2_addressing *addressing,
 469                                 u8 RL)
 470 {
 471         u32 config_reg = 0;
 472
 473         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 474         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 475                         EMIF_REG_IBANK_POS_SHIFT;
 476
 477         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 478
 479         config_reg |= RL << EMIF_REG_CL_SHIFT;
 480
 481         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 482                         EMIF_REG_ROWSIZE_SHIFT;
 483
 484         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 485
 486         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 487                         EMIF_REG_EBANK_SHIFT;
 488
 489         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 490                         EMIF_REG_PAGESIZE_SHIFT;
 491
 492         return config_reg;
 493 }
 494
 495 static u32 get_sdram_ref_ctrl(u32 freq,
 496                               const struct lpddr2_addressing *addressing)
 497 {
 498         u32 ref_ctrl = 0, val = 0, freq_khz;
 499         freq_khz = freq / 1000;
 500         /*
 501          * refresh rate to be set is 'tREFI * freq in MHz
 502          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 503          */
 504         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 505         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 506
 507         return ref_ctrl;
 508 }
 509
 510 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 511                                const struct lpddr2_min_tck *min_tck,
 512                                const struct lpddr2_addressing *addressing)
 513 {
 514         u32 tim1 = 0, val = 0;
 515         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 516         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 517
 518         if (addressing->num_banks == BANKS8)
 519                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 520                                                         (4 * (*T_num)) - 1;
 521         else
 522                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 523
 524         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 525
 526         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 527         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 528
 529         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 530         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 531
 532         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 533         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 534
 535         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 536         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 537
 538         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 539         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 540
 541         return tim1;
 542 }
 543
 544 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 545                                const struct lpddr2_min_tck *min_tck)
 546 {
 547         u32 tim2 = 0, val = 0;
 548         val = max(min_tck->tCKE, timings->tCKE) - 1;
 549         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 550
 551         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 552         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 553
 554         /*
 555          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 556          * same value
 557          */
 558         val = ns_2_cycles(timings->tXSR) - 1;
 559         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 560         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 561
 562         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 563         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 564
 565         return tim2;
 566 }
 567
 568 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 569                                const struct lpddr2_min_tck *min_tck,
 570                                const struct lpddr2_addressing *addressing)
 571 {
 572         u32 tim3 = 0, val = 0;
 573         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 574         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 575
 576         val = ns_2_cycles(timings->tRFCab) - 1;
 577         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 578
 579         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 580         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 581
 582         val = ns_2_cycles(timings->tZQCS) - 1;
 583         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 584
 585         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 586         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 587
 588         return tim3;
 589 }
 590
 591 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 592                              const struct lpddr2_addressing *addressing,
 593                              u8 volt_ramp)
 594 {
 595         u32 zq = 0, val = 0;
 596         if (volt_ramp)
 597                 val =
 598                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 599                     addressing->t_REFI_us_x10;
 600         else
 601                 val =
 602                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 603                     addressing->t_REFI_us_x10;
 604         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 605
 606         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 607
 608         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 609
 610         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 611
 612         /*
 613          * Assuming that two chipselects have a single calibration resistor
 614          * If there are indeed two calibration resistors, then this flag should
 615          * be enabled to take advantage of dual calibration feature.
 616          * This data should ideally come from board files. But considering
 617          * that none of the boards today have calibration resistors per CS,
 618          * it would be an unnecessary overhead.
 619          */
 620         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 621
 622         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 623
 624         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 625
 626         return zq;
 627 }
 628
 629 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 630                                  const struct lpddr2_addressing *addressing,
 631                                  u8 is_derated)
 632 {
 633         u32 alert = 0, interval;
 634         interval =
 635             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 636         if (is_derated)
 637                 interval *= 4;
 638         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 639
 640         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 641
 642         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 643
 644         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 645
 646         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 647
 648         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 649
 650         return alert;
 651 }
 652
 653 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 654 {
 655         u32 idle = 0, val = 0;
 656         if (volt_ramp)
 657                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 658         else
 659                 /*Maximum value in normal conditions - suggested by hw team */
 660                 val = 0x1FF;
 661         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 662
 663         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 664
 665         return idle;
 666 }
 667
 668 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 669 {
 670         u32 phy = 0, val = 0;
 671
 672         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 673
 674         if (freq <= 100000000)
 675                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 676         else if (freq <= 200000000)
 677                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 678         else
 679                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 680         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 681
 682         /* Other fields are constant magic values. Hardcode them together */
 683         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 684                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 685
 686         return phy;
 687 }
 688
 689 static u32 get_emif_mem_size(u32 base)
 690 {
 691         u32 size_mbytes = 0, temp;
 692         struct emif_device_details dev_details;
 693         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 694         u32 emif_nr = emif_num(base);
 695
 696         emif_reset_phy(base);
 697         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 698                                                 &cs0_dev_details);
 699         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 700                                                 &cs1_dev_details);
 701         emif_reset_phy(base);
 702
 703         if (dev_details.cs0_device_details) {
 704                 temp = dev_details.cs0_device_details->density;
 705                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 706         }
 707
 708         if (dev_details.cs1_device_details) {
 709                 temp = dev_details.cs1_device_details->density;
 710                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 711         }
 712         /* convert to bytes */
 713         return size_mbytes << 20;
 714 }
 715
 716 /* Gets the encoding corresponding to a given DMM section size */
 717 u32 get_dmm_section_size_map(u32 section_size)
 718 {
 719         /*
 720          * Section size mapping:
 721          * 0x0: 16-MiB section
 722          * 0x1: 32-MiB section
 723          * 0x2: 64-MiB section
 724          * 0x3: 128-MiB section
 725          * 0x4: 256-MiB section
 726          * 0x5: 512-MiB section
 727          * 0x6: 1-GiB section
 728          * 0x7: 2-GiB section
 729          */
 730         section_size >>= 24; /* divide by 16 MB */
 731         return log_2_n_round_down(section_size);
 732 }
 733
 734 static void emif_calculate_regs(
 735                 const struct emif_device_details *emif_dev_details,
 736                 u32 freq, struct emif_regs *regs)
 737 {
 738         u32 temp, sys_freq;
 739         const struct lpddr2_addressing *addressing;
 740         const struct lpddr2_ac_timings *timings;
 741         const struct lpddr2_min_tck *min_tck;
 742         const struct lpddr2_device_details *cs0_dev_details =
 743                                         emif_dev_details->cs0_device_details;
 744         const struct lpddr2_device_details *cs1_dev_details =
 745                                         emif_dev_details->cs1_device_details;
 746         const struct lpddr2_device_timings *cs0_dev_timings =
 747                                         emif_dev_details->cs0_device_timings;
 748
 749         emif_assert(emif_dev_details);
 750         emif_assert(regs);
 751         /*
 752          * You can not have a device on CS1 without one on CS0
 753          * So configuring EMIF without a device on CS0 doesn't
 754          * make sense
 755          */
 756         emif_assert(cs0_dev_details);
 757         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 758         /*
 759          * If there is a device on CS1 it should be same type as CS0
 760          * (or NVM. But NVM is not supported in this driver yet)
 761          */
 762         emif_assert((cs1_dev_details == NULL) ||
 763                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 764                     (cs0_dev_details->type == cs1_dev_details->type));
 765         emif_assert(freq <= MAX_LPDDR2_FREQ);
 766
 767         set_ddr_clk_period(freq);
 768
 769         /*
 770          * The device on CS0 is used for all timing calculations
 771          * There is only one set of registers for timings per EMIF. So, if the
 772          * second CS(CS1) has a device, it should have the same timings as the
 773          * device on CS0
 774          */
 775         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 776         emif_assert(timings);
 777         min_tck = cs0_dev_timings->min_tck;
 778
 779         temp = addressing_table_index(cs0_dev_details->type,
 780                                       cs0_dev_details->density,
 781                                       cs0_dev_details->io_width);
 782
 783         emif_assert((temp >= 0));
 784         addressing = &(addressing_table[temp]);
 785         emif_assert(addressing);
 786
 787         sys_freq = get_sys_clk_freq();
 788
 789         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 790                                                         cs1_dev_details,
 791                                                         addressing, RL_BOOT);
 792
 793         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 794                                                 cs1_dev_details,
 795                                                 addressing, RL_FINAL);
 796
 797         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 798
 799         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 800
 801         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 802
 803         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 804
 805         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 806
 807         regs->temp_alert_config =
 808             get_temp_alert_config(cs1_dev_details, addressing, 0);
 809
 810         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 811                                             LPDDR2_VOLTAGE_STABLE);
 812
 813         regs->emif_ddr_phy_ctlr_1_init =
 814                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 815
 816         regs->emif_ddr_phy_ctlr_1 =
 817                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 818
 819         regs->freq = freq;
 820
 821         print_timing_reg(regs->sdram_config_init);
 822         print_timing_reg(regs->sdram_config);
 823         print_timing_reg(regs->ref_ctrl);
 824         print_timing_reg(regs->sdram_tim1);
 825         print_timing_reg(regs->sdram_tim2);
 826         print_timing_reg(regs->sdram_tim3);
 827         print_timing_reg(regs->read_idle_ctrl);
 828         print_timing_reg(regs->temp_alert_config);
 829         print_timing_reg(regs->zq_config);
 830         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 831         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 832 }
 833 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 834
 835 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 836 const char *get_lpddr2_type(u8 type_id)
 837 {
 838         switch (type_id) {
 839         case LPDDR2_TYPE_S4:
 840                 return "LPDDR2-S4";
 841         case LPDDR2_TYPE_S2:
 842                 return "LPDDR2-S2";
 843         default:
 844                 return NULL;
 845         }
 846 }
 847
 848 const char *get_lpddr2_io_width(u8 width_id)
 849 {
 850         switch (width_id) {
 851         case LPDDR2_IO_WIDTH_8:
 852                 return "x8";
 853         case LPDDR2_IO_WIDTH_16:
 854                 return "x16";
 855         case LPDDR2_IO_WIDTH_32:
 856                 return "x32";
 857         default:
 858                 return NULL;
 859         }
 860 }
 861
 862 const char *get_lpddr2_manufacturer(u32 manufacturer)
 863 {
 864         switch (manufacturer) {
 865         case LPDDR2_MANUFACTURER_SAMSUNG:
 866                 return "Samsung";
 867         case LPDDR2_MANUFACTURER_QIMONDA:
 868                 return "Qimonda";
 869         case LPDDR2_MANUFACTURER_ELPIDA:
 870                 return "Elpida";
 871         case LPDDR2_MANUFACTURER_ETRON:
 872                 return "Etron";
 873         case LPDDR2_MANUFACTURER_NANYA:
 874                 return "Nanya";
 875         case LPDDR2_MANUFACTURER_HYNIX:
 876                 return "Hynix";
 877         case LPDDR2_MANUFACTURER_MOSEL:
 878                 return "Mosel";
 879         case LPDDR2_MANUFACTURER_WINBOND:
 880                 return "Winbond";
 881         case LPDDR2_MANUFACTURER_ESMT:
 882                 return "ESMT";
 883         case LPDDR2_MANUFACTURER_SPANSION:
 884                 return "Spansion";
 885         case LPDDR2_MANUFACTURER_SST:
 886                 return "SST";
 887         case LPDDR2_MANUFACTURER_ZMOS:
 888                 return "ZMOS";
 889         case LPDDR2_MANUFACTURER_INTEL:
 890                 return "Intel";
 891         case LPDDR2_MANUFACTURER_NUMONYX:
 892                 return "Numonyx";
 893         case LPDDR2_MANUFACTURER_MICRON:
 894                 return "Micron";
 895         default:
 896                 return NULL;
 897         }
 898 }
 899
 900 static void display_sdram_details(u32 emif_nr, u32 cs,
 901                                   struct lpddr2_device_details *device)
 902 {
 903         const char *mfg_str;
 904         const char *type_str;
 905         char density_str[10];
 906         u32 density;
 907
 908         debug("EMIF%d CS%d\t", emif_nr, cs);
 909
 910         if (!device) {
 911                 debug("None\n");
 912                 return;
 913         }
 914
 915         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
 916         type_str = get_lpddr2_type(device->type);
 917
 918         density = lpddr2_density_2_size_in_mbytes[device->density];
 919         if ((density / 1024 * 1024) == density) {
 920                 density /= 1024;
 921                 sprintf(density_str, "%d GB", density);
 922         } else
 923                 sprintf(density_str, "%d MB", density);
 924         if (mfg_str && type_str)
 925                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
 926 }
 927
 928 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 929                                   struct lpddr2_device_details *lpddr2_device)
 930 {
 931         u32 mr = 0, temp;
 932
 933         mr = get_mr(base, cs, LPDDR2_MR0);
 934         if (mr > 0xFF) {
 935                 /* Mode register value bigger than 8 bit */
 936                 return 0;
 937         }
 938
 939         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
 940         if (temp) {
 941                 /* Not SDRAM */
 942                 return 0;
 943         }
 944         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
 945
 946         if (temp) {
 947                 /* DNV supported - But DNV is only supported for NVM */
 948                 return 0;
 949         }
 950
 951         mr = get_mr(base, cs, LPDDR2_MR4);
 952         if (mr > 0xFF) {
 953                 /* Mode register value bigger than 8 bit */
 954                 return 0;
 955         }
 956
 957         mr = get_mr(base, cs, LPDDR2_MR5);
 958         if (mr > 0xFF) {
 959                 /* Mode register value bigger than 8 bit */
 960                 return 0;
 961         }
 962
 963         if (!get_lpddr2_manufacturer(mr)) {
 964                 /* Manufacturer not identified */
 965                 return 0;
 966         }
 967         lpddr2_device->manufacturer = mr;
 968
 969         mr = get_mr(base, cs, LPDDR2_MR6);
 970         if (mr >= 0xFF) {
 971                 /* Mode register value bigger than 8 bit */
 972                 return 0;
 973         }
 974
 975         mr = get_mr(base, cs, LPDDR2_MR7);
 976         if (mr >= 0xFF) {
 977                 /* Mode register value bigger than 8 bit */
 978                 return 0;
 979         }
 980
 981         mr = get_mr(base, cs, LPDDR2_MR8);
 982         if (mr >= 0xFF) {
 983                 /* Mode register value bigger than 8 bit */
 984                 return 0;
 985         }
 986
 987         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
 988         if (!get_lpddr2_type(temp)) {
 989                 /* Not SDRAM */
 990                 return 0;
 991         }
 992         lpddr2_device->type = temp;
 993
 994         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
 995         if (temp > LPDDR2_DENSITY_32Gb) {
 996                 /* Density not supported */
 997                 return 0;
 998         }
 999         lpddr2_device->density = temp;
1000
1001         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1002         if (!get_lpddr2_io_width(temp)) {
1003                 /* IO width unsupported value */
1004                 return 0;
1005         }
1006         lpddr2_device->io_width = temp;
1007
1008         /*
1009          * If all the above tests pass we should
1010          * have a device on this chip-select
1011          */
1012         return 1;
1013 }
1014
1015 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1016                         struct lpddr2_device_details *lpddr2_dev_details)
1017 {
1018         u32 phy;
1019         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1020
1021         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1022
1023         if (!lpddr2_dev_details)
1024                 return NULL;
1025
1026         /* Do the minimum init for mode register accesses */
1027         if (!(running_from_sdram() || warm_reset())) {
1028                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1029                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1030         }
1031
1032         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1033                 return NULL;
1034
1035         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1036
1037         return lpddr2_dev_details;
1038 }
1039 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1040
1041 static void do_sdram_init(u32 base)
1042 {
1043         const struct emif_regs *regs;
1044         u32 in_sdram, emif_nr;
1045
1046         debug(">>do_sdram_init() %x\n", base);
1047
1048         in_sdram = running_from_sdram();
1049         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1050
1051 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1052         emif_get_reg_dump(emif_nr, &regs);
1053         if (!regs) {
1054                 debug("EMIF: reg dump not provided\n");
1055                 return;
1056         }
1057 #else
1058         /*
1059          * The user has not provided the register values. We need to
1060          * calculate it based on the timings and the DDR frequency
1061          */
1062         struct emif_device_details dev_details;
1063         struct emif_regs calculated_regs;
1064
1065         /*
1066          * Get device details:
1067          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1068          * - Obtained from user otherwise
1069          */
1070         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1071         emif_reset_phy(base);
1072         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1073                                                 &cs0_dev_details);
1074         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1075                                                 &cs1_dev_details);
1076         emif_reset_phy(base);
1077
1078         /* Return if no devices on this EMIF */
1079         if (!dev_details.cs0_device_details &&
1080             !dev_details.cs1_device_details) {
1081                 return;
1082         }
1083
1084         /*
1085          * Get device timings:
1086          * - Default timings specified by JESD209-2 if
1087          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1088          * - Obtained from user otherwise
1089          */
1090         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1091                                 &dev_details.cs1_device_timings);
1092
1093         /* Calculate the register values */
1094         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1095         regs = &calculated_regs;
1096 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1097
1098         /*
1099          * Initializing the LPDDR2 device can not happen from SDRAM.
1100          * Changing the timing registers in EMIF can happen(going from one
1101          * OPP to another)
1102          */
1103         if (!(in_sdram || warm_reset())) {
1104                 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1105                         lpddr2_init(base, regs);
1106                 else
1107                         ddr3_init(base, regs);
1108         }
1109         if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1110                 set_lpmode_selfrefresh(base);
1111                 emif_reset_phy(base);
1112                 ddr3_leveling(base, regs);
1113         }
1114
1115         /* Write to the shadow registers */
1116         emif_update_timings(base, regs);
1117
1118         debug("<<do_sdram_init() %x\n", base);
1119 }
1120
1121 void emif_post_init_config(u32 base)
1122 {
1123         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1124         u32 omap_rev = omap_revision();
1125
1126         /* reset phy on ES2.0 */
1127         if (omap_rev == OMAP4430_ES2_0)
1128                 emif_reset_phy(base);
1129
1130         /* Put EMIF back in smart idle on ES1.0 */
1131         if (omap_rev == OMAP4430_ES1_0)
1132                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1133 }
1134
1135 void dmm_init(u32 base)
1136 {
1137         const struct dmm_lisa_map_regs *lisa_map_regs;
1138         u32 i, section, valid;
1139
1140 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1141         emif_get_dmm_regs(&lisa_map_regs);
1142 #else
1143         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1144         u32 section_cnt, sys_addr;
1145         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1146
1147         mapped_size = 0;
1148         section_cnt = 3;
1149         sys_addr = CONFIG_SYS_SDRAM_BASE;
1150         emif1_size = get_emif_mem_size(EMIF1_BASE);
1151         emif2_size = get_emif_mem_size(EMIF2_BASE);
1152         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1153
1154         if (!emif1_size && !emif2_size)
1155                 return;
1156
1157         /* symmetric interleaved section */
1158         if (emif1_size && emif2_size) {
1159                 mapped_size = min(emif1_size, emif2_size);
1160                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1161                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1162                 /* only MSB */
1163                 section_map |= (sys_addr >> 24) <<
1164                                 EMIF_SYS_ADDR_SHIFT;
1165                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1166                                 << EMIF_SYS_SIZE_SHIFT;
1167                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1168                 emif1_size -= mapped_size;
1169                 emif2_size -= mapped_size;
1170                 sys_addr += (mapped_size * 2);
1171                 section_cnt--;
1172         }
1173
1174         /*
1175          * Single EMIF section(we can have a maximum of 1 single EMIF
1176          * section- either EMIF1 or EMIF2 or none, but not both)
1177          */
1178         if (emif1_size) {
1179                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1180                 section_map |= get_dmm_section_size_map(emif1_size)
1181                                 << EMIF_SYS_SIZE_SHIFT;
1182                 /* only MSB */
1183                 section_map |= (mapped_size >> 24) <<
1184                                 EMIF_SDRC_ADDR_SHIFT;
1185                 /* only MSB */
1186                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1187                 section_cnt--;
1188         }
1189         if (emif2_size) {
1190                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1191                 section_map |= get_dmm_section_size_map(emif2_size) <<
1192                                 EMIF_SYS_SIZE_SHIFT;
1193                 /* only MSB */
1194                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1195                 /* only MSB */
1196                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1197                 section_cnt--;
1198         }
1199
1200         if (section_cnt == 2) {
1201                 /* Only 1 section - either symmetric or single EMIF */
1202                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1203                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1204                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1205         } else {
1206                 /* 2 sections - 1 symmetric, 1 single EMIF */
1207                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1208                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1209         }
1210
1211         /* TRAP for invalid TILER mappings in section 0 */
1212         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1213
1214         if (omap_revision() >= OMAP4460_ES1_0)
1215                 lis_map_regs_calculated.is_ma_present = 1;
1216
1217         lisa_map_regs = &lis_map_regs_calculated;
1218 #endif
1219         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1220             (struct dmm_lisa_map_regs *)base;
1221
1222         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1223         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1224         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1225         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1226
1227         writel(lisa_map_regs->dmm_lisa_map_3,
1228                 &hw_lisa_map_regs->dmm_lisa_map_3);
1229         writel(lisa_map_regs->dmm_lisa_map_2,
1230                 &hw_lisa_map_regs->dmm_lisa_map_2);
1231         writel(lisa_map_regs->dmm_lisa_map_1,
1232                 &hw_lisa_map_regs->dmm_lisa_map_1);
1233         writel(lisa_map_regs->dmm_lisa_map_0,
1234                 &hw_lisa_map_regs->dmm_lisa_map_0);
1235
1236         if (lisa_map_regs->is_ma_present) {
1237                 hw_lisa_map_regs =
1238                     (struct dmm_lisa_map_regs *)MA_BASE;
1239
1240                 writel(lisa_map_regs->dmm_lisa_map_3,
1241                         &hw_lisa_map_regs->dmm_lisa_map_3);
1242                 writel(lisa_map_regs->dmm_lisa_map_2,
1243                         &hw_lisa_map_regs->dmm_lisa_map_2);
1244                 writel(lisa_map_regs->dmm_lisa_map_1,
1245                         &hw_lisa_map_regs->dmm_lisa_map_1);
1246                 writel(lisa_map_regs->dmm_lisa_map_0,
1247                         &hw_lisa_map_regs->dmm_lisa_map_0);
1248         }
1249
1250         /*
1251          * EMIF should be configured only when
1252          * memory is mapped on it. Using emif1_enabled
1253          * and emif2_enabled variables for this.
1254          */
1255         emif1_enabled = 0;
1256         emif2_enabled = 0;
1257         for (i = 0; i < 4; i++) {
1258                 section = __raw_readl(DMM_BASE + i*4);
1259                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1260                         (EMIF_SDRC_MAP_SHIFT);
1261                 if (valid == 3) {
1262                         emif1_enabled = 1;
1263                         emif2_enabled = 1;
1264                         break;
1265                 } else if (valid == 1) {
1266                         emif1_enabled = 1;
1267                 } else if (valid == 2) {
1268                         emif2_enabled = 1;
1269                 }
1270         }
1271
1272 }
1273
1274 static void do_bug0039_workaround(u32 base)
1275 {
1276         u32 val, i, clkctrl;
1277         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1278         const struct read_write_regs *bug_00339_regs;
1279         u32 iterations;
1280         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1281         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1282
1283         if (is_dra7xx())
1284                 phy_status_base++;
1285
1286         bug_00339_regs = get_bug_regs(&iterations);
1287
1288         /* Put EMIF in to idle */
1289         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1290         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1291
1292         /* Copy the phy status registers in to phy ctrl shadow registers */
1293         for (i = 0; i < iterations; i++) {
1294                 val = __raw_readl(phy_status_base +
1295                                   bug_00339_regs[i].read_reg - 1);
1296
1297                 __raw_writel(val, phy_ctrl_base +
1298                              ((bug_00339_regs[i].write_reg - 1) << 1));
1299
1300                 __raw_writel(val, phy_ctrl_base +
1301                              (bug_00339_regs[i].write_reg << 1) - 1);
1302         }
1303
1304         /* Disable leveling */
1305         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1306
1307         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1308 }
1309
1310 /*
1311  * SDRAM initialization:
1312  * SDRAM initialization has two parts:
1313  * 1. Configuring the SDRAM device
1314  * 2. Update the AC timings related parameters in the EMIF module
1315  * (1) should be done only once and should not be done while we are
1316  * running from SDRAM.
1317  * (2) can and should be done more than once if OPP changes.
1318  * Particularly, this may be needed when we boot without SPL and
1319  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1320  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1321  * the frequency. So,
1322  * Doing (1) and (2) makes sense - first time initialization
1323  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1324  * Doing (1) and not (2) doen't make sense
1325  * See do_sdram_init() for the details
1326  */
1327 void sdram_init(void)
1328 {
1329         u32 in_sdram, size_prog, size_detect;
1330         u32 sdram_type = emif_sdram_type();
1331
1332         debug(">>sdram_init()\n");
1333
1334         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1335                 return;
1336
1337         in_sdram = running_from_sdram();
1338         debug("in_sdram = %d\n", in_sdram);
1339
1340         if (!in_sdram) {
1341                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1342                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1343                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1344                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1345         }
1346
1347         if (!in_sdram)
1348                 dmm_init(DMM_BASE);
1349
1350         if (emif1_enabled)
1351                 do_sdram_init(EMIF1_BASE);
1352
1353         if (emif2_enabled)
1354                 do_sdram_init(EMIF2_BASE);
1355
1356         if (!(in_sdram || warm_reset())) {
1357                 if (emif1_enabled)
1358                         emif_post_init_config(EMIF1_BASE);
1359                 if (emif2_enabled)
1360                         emif_post_init_config(EMIF2_BASE);
1361         }
1362
1363         /* for the shadow registers to take effect */
1364         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1365                 freq_update_core();
1366
1367         /* Do some testing after the init */
1368         if (!in_sdram) {
1369                 size_prog = omap_sdram_size();
1370                 size_prog = log_2_n_round_down(size_prog);
1371                 size_prog = (1 << size_prog);
1372
1373                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1374                                                 size_prog);
1375                 /* Compare with the size programmed */
1376                 if (size_detect != size_prog) {
1377                         printf("SDRAM: identified size not same as expected"
1378                                 " size identified: %x expected: %x\n",
1379                                 size_detect,
1380                                 size_prog);
1381                 } else
1382                         debug("get_ram_size() successful");
1383         }
1384
1385         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1386             (!in_sdram && !warm_reset())) {
1387                 if (emif1_enabled)
1388                         do_bug0039_workaround(EMIF1_BASE);
1389                 if (emif2_enabled)
1390                         do_bug0039_workaround(EMIF2_BASE);
1391         }
1392
1393         debug("<<sdram_init()\n");
1394 }