arch/arm/cpu/armv7/omap-common/emif-common.c

   1 /*
   2  * EMIF programming
   3  *
   4  * (C) Copyright 2010
   5  * Texas Instruments, <www.ti.com>
   6  *
   7  * Aneesh V <aneesh@ti.com>
   8  *
   9  * SPDX-License-Identifier:     GPL-2.0+
  10  */
  11
  12 #include <common.h>
  13 #include <asm/emif.h>
  14 #include <asm/arch/clock.h>
  15 #include <asm/arch/sys_proto.h>
  16 #include <asm/omap_common.h>
  17 #include <asm/utils.h>
  18 #include <linux/compiler.h>
  19
  20 static int emif1_enabled = -1, emif2_enabled = -1;
  21
  22 void set_lpmode_selfrefresh(u32 base)
  23 {
  24         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  25         u32 reg;
  26
  27         reg = readl(&emif->emif_pwr_mgmt_ctrl);
  28         reg &= ~EMIF_REG_LP_MODE_MASK;
  29         reg |= LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT;
  30         reg &= ~EMIF_REG_SR_TIM_MASK;
  31         writel(reg, &emif->emif_pwr_mgmt_ctrl);
  32
  33         /* dummy read for the new SR_TIM to be loaded */
  34         readl(&emif->emif_pwr_mgmt_ctrl);
  35 }
  36
  37 void force_emif_self_refresh()
  38 {
  39         set_lpmode_selfrefresh(EMIF1_BASE);
  40         set_lpmode_selfrefresh(EMIF2_BASE);
  41 }
  42
  43 inline u32 emif_num(u32 base)
  44 {
  45         if (base == EMIF1_BASE)
  46                 return 1;
  47         else if (base == EMIF2_BASE)
  48                 return 2;
  49         else
  50                 return 0;
  51 }
  52
  53 static inline u32 get_mr(u32 base, u32 cs, u32 mr_addr)
  54 {
  55         u32 mr;
  56         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  57
  58         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  59         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  60         if (omap_revision() == OMAP4430_ES2_0)
  61                 mr = readl(&emif->emif_lpddr2_mode_reg_data_es2);
  62         else
  63                 mr = readl(&emif->emif_lpddr2_mode_reg_data);
  64         debug("get_mr: EMIF%d cs %d mr %08x val 0x%x\n", emif_num(base),
  65               cs, mr_addr, mr);
  66         if (((mr & 0x0000ff00) >>  8) == (mr & 0xff) &&
  67             ((mr & 0x00ff0000) >> 16) == (mr & 0xff) &&
  68             ((mr & 0xff000000) >> 24) == (mr & 0xff))
  69                 return mr & 0xff;
  70         else
  71                 return mr;
  72 }
  73
  74 static inline void set_mr(u32 base, u32 cs, u32 mr_addr, u32 mr_val)
  75 {
  76         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  77
  78         mr_addr |= cs << EMIF_REG_CS_SHIFT;
  79         writel(mr_addr, &emif->emif_lpddr2_mode_reg_cfg);
  80         writel(mr_val, &emif->emif_lpddr2_mode_reg_data);
  81 }
  82
  83 void emif_reset_phy(u32 base)
  84 {
  85         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
  86         u32 iodft;
  87
  88         iodft = readl(&emif->emif_iodft_tlgc);
  89         iodft |= EMIF_REG_RESET_PHY_MASK;
  90         writel(iodft, &emif->emif_iodft_tlgc);
  91 }
  92
  93 static void do_lpddr2_init(u32 base, u32 cs)
  94 {
  95         u32 mr_addr;
  96         const struct lpddr2_mr_regs *mr_regs;
  97
  98         get_lpddr2_mr_regs(&mr_regs);
  99         /* Wait till device auto initialization is complete */
 100         while (get_mr(base, cs, LPDDR2_MR0) & LPDDR2_MR0_DAI_MASK)
 101                 ;
 102         set_mr(base, cs, LPDDR2_MR10, mr_regs->mr10);
 103         /*
 104          * tZQINIT = 1 us
 105          * Enough loops assuming a maximum of 2GHz
 106          */
 107
 108         sdelay(2000);
 109
 110         set_mr(base, cs, LPDDR2_MR1, mr_regs->mr1);
 111         set_mr(base, cs, LPDDR2_MR16, mr_regs->mr16);
 112
 113         /*
 114          * Enable refresh along with writing MR2
 115          * Encoding of RL in MR2 is (RL - 2)
 116          */
 117         mr_addr = LPDDR2_MR2 | EMIF_REG_REFRESH_EN_MASK;
 118         set_mr(base, cs, mr_addr, mr_regs->mr2);
 119
 120         if (mr_regs->mr3 > 0)
 121                 set_mr(base, cs, LPDDR2_MR3, mr_regs->mr3);
 122 }
 123
 124 static void lpddr2_init(u32 base, const struct emif_regs *regs)
 125 {
 126         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 127
 128         /* Not NVM */
 129         clrbits_le32(&emif->emif_lpddr2_nvm_config, EMIF_REG_CS1NVMEN_MASK);
 130
 131         /*
 132          * Keep REG_INITREF_DIS = 1 to prevent re-initialization of SDRAM
 133          * when EMIF_SDRAM_CONFIG register is written
 134          */
 135         setbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 136
 137         /*
 138          * Set the SDRAM_CONFIG and PHY_CTRL for the
 139          * un-locked frequency & default RL
 140          */
 141         writel(regs->sdram_config_init, &emif->emif_sdram_config);
 142         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 143
 144         do_ext_phy_settings(base, regs);
 145
 146         do_lpddr2_init(base, CS0);
 147         if (regs->sdram_config & EMIF_REG_EBANK_MASK)
 148                 do_lpddr2_init(base, CS1);
 149
 150         writel(regs->sdram_config, &emif->emif_sdram_config);
 151         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1);
 152
 153         /* Enable refresh now */
 154         clrbits_le32(&emif->emif_sdram_ref_ctrl, EMIF_REG_INITREF_DIS_MASK);
 155
 156         }
 157
 158 __weak void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 159 {
 160 }
 161
 162 void emif_update_timings(u32 base, const struct emif_regs *regs)
 163 {
 164         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 165
 166         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl_shdw);
 167         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1_shdw);
 168         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2_shdw);
 169         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3_shdw);
 170         if (omap_revision() == OMAP4430_ES1_0) {
 171                 /* ES1 bug EMIF should be in force idle during freq_update */
 172                 writel(0, &emif->emif_pwr_mgmt_ctrl);
 173         } else {
 174                 writel(EMIF_PWR_MGMT_CTRL, &emif->emif_pwr_mgmt_ctrl);
 175                 writel(EMIF_PWR_MGMT_CTRL_SHDW, &emif->emif_pwr_mgmt_ctrl_shdw);
 176         }
 177         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl_shdw);
 178         writel(regs->zq_config, &emif->emif_zq_config);
 179         writel(regs->temp_alert_config, &emif->emif_temp_alert_config);
 180         writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
 181
 182         if ((omap_revision() >= OMAP5430_ES1_0) ||
 183                                 (omap_revision() == DRA752_ES1_0)) {
 184                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0,
 185                         &emif->emif_l3_config);
 186         } else if (omap_revision() >= OMAP4460_ES1_0) {
 187                 writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_3_LL_0,
 188                         &emif->emif_l3_config);
 189         } else {
 190                 writel(EMIF_L3_CONFIG_VAL_SYS_10_LL_0,
 191                         &emif->emif_l3_config);
 192         }
 193 }
 194
 195 static void omap5_ddr3_leveling(u32 base, const struct emif_regs *regs)
 196 {
 197         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 198
 199         /* keep sdram in self-refresh */
 200         writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT)
 201                 & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 202         __udelay(130);
 203
 204         /*
 205          * Set invert_clkout (if activated)--DDR_PHYCTRL_1
 206          * Invert clock adds an additional half cycle delay on the
 207          * command interface.  The additional half cycle, is usually
 208          * meant to enable leveling in the situation that DQS is later
 209          * than CK on the board.It also helps provide some additional
 210          * margin for leveling.
 211          */
 212         writel(regs->emif_ddr_phy_ctlr_1,
 213                &emif->emif_ddr_phy_ctrl_1);
 214
 215         writel(regs->emif_ddr_phy_ctlr_1,
 216                &emif->emif_ddr_phy_ctrl_1_shdw);
 217         __udelay(130);
 218
 219         writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT)
 220                & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl);
 221
 222         /* Launch Full leveling */
 223         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 224
 225         /* Wait till full leveling is complete */
 226         readl(&emif->emif_rd_wr_lvl_ctl);
 227               __udelay(130);
 228
 229         /* Read data eye leveling no of samples */
 230         config_data_eye_leveling_samples(base);
 231
 232         /*
 233          * Launch 8 incremental WR_LVL- to compensate for
 234          * PHY limitation.
 235          */
 236         writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT,
 237                &emif->emif_rd_wr_lvl_ctl);
 238
 239         __udelay(130);
 240
 241         /* Launch Incremental leveling */
 242         writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl);
 243                __udelay(130);
 244 }
 245
 246 static void dra7_ddr3_leveling(u32 base, const struct emif_regs *regs)
 247 {
 248         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 249
 250         u32 fifo_reg;
 251
 252         fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_1);
 253         writel(fifo_reg | 0x00000100,
 254                &emif->emif_ddr_fifo_misaligned_clear_1);
 255
 256         fifo_reg = readl(&emif->emif_ddr_fifo_misaligned_clear_2);
 257         writel(fifo_reg | 0x00000100,
 258                &emif->emif_ddr_fifo_misaligned_clear_2);
 259
 260         /* Launch Full leveling */
 261         writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl);
 262
 263         /* Wait till full leveling is complete */
 264         readl(&emif->emif_rd_wr_lvl_ctl);
 265               __udelay(130);
 266
 267         /* Read data eye leveling no of samples */
 268         config_data_eye_leveling_samples(base);
 269
 270         /*
 271          * Disable leveling. This is because if leveling is kept
 272          * enabled, then PHY triggers a false leveling during
 273          * EMIF-idle scenario which results in wrong delay
 274          * values getting updated. After this the EMIF becomes
 275          * unaccessible. So disable it after the first time
 276          */
 277         writel(0x0, &emif->emif_rd_wr_lvl_rmp_ctl);
 278 }
 279
 280 static void ddr3_leveling(u32 base, const struct emif_regs *regs)
 281 {
 282         if (is_omap54xx())
 283                 omap5_ddr3_leveling(base, regs);
 284         else
 285                 dra7_ddr3_leveling(base, regs);
 286 }
 287
 288 static void ddr3_init(u32 base, const struct emif_regs *regs)
 289 {
 290         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 291
 292         /*
 293          * Set SDRAM_CONFIG and PHY control registers to locked frequency
 294          * and RL =7. As the default values of the Mode Registers are not
 295          * defined, contents of mode Registers must be fully initialized.
 296          * H/W takes care of this initialization
 297          */
 298         writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1);
 299
 300         /* Update timing registers */
 301         writel(regs->sdram_tim1, &emif->emif_sdram_tim_1);
 302         writel(regs->sdram_tim2, &emif->emif_sdram_tim_2);
 303         writel(regs->sdram_tim3, &emif->emif_sdram_tim_3);
 304
 305         writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl);
 306         writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl);
 307
 308         /*
 309          * The same sequence should work on OMAP5432 as well. But strange that
 310          * it is not working
 311          */
 312         if (omap_revision() == DRA752_ES1_0) {
 313                 do_ext_phy_settings(base, regs);
 314                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 315                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 316         } else {
 317                 writel(regs->sdram_config2, &emif->emif_lpddr2_nvm_config);
 318                 writel(regs->sdram_config_init, &emif->emif_sdram_config);
 319                 do_ext_phy_settings(base, regs);
 320         }
 321
 322         /* enable leveling */
 323         writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl);
 324
 325         ddr3_leveling(base, regs);
 326 }
 327
 328 #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
 329 #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
 330
 331 /*
 332  * Organization and refresh requirements for LPDDR2 devices of different
 333  * types and densities. Derived from JESD209-2 section 2.4
 334  */
 335 const struct lpddr2_addressing addressing_table[] = {
 336         /* Banks tREFIx10     rowx32,rowx16      colx32,colx16  density */
 337         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_7, COL_8} },/*64M */
 338         {BANKS4, T_REFI_15_6, {ROW_12, ROW_12}, {COL_8, COL_9} },/*128M */
 339         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_8, COL_9} },/*256M */
 340         {BANKS4, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*512M */
 341         {BANKS8, T_REFI_7_8, {ROW_13, ROW_13}, {COL_9, COL_10} },/*1GS4 */
 342         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_9, COL_10} },/*2GS4 */
 343         {BANKS8, T_REFI_3_9, {ROW_14, ROW_14}, {COL_10, COL_11} },/*4G */
 344         {BANKS8, T_REFI_3_9, {ROW_15, ROW_15}, {COL_10, COL_11} },/*8G */
 345         {BANKS4, T_REFI_7_8, {ROW_14, ROW_14}, {COL_9, COL_10} },/*1GS2 */
 346         {BANKS4, T_REFI_3_9, {ROW_15, ROW_15}, {COL_9, COL_10} },/*2GS2 */
 347 };
 348
 349 static const u32 lpddr2_density_2_size_in_mbytes[] = {
 350         8,                      /* 64Mb */
 351         16,                     /* 128Mb */
 352         32,                     /* 256Mb */
 353         64,                     /* 512Mb */
 354         128,                    /* 1Gb   */
 355         256,                    /* 2Gb   */
 356         512,                    /* 4Gb   */
 357         1024,                   /* 8Gb   */
 358         2048,                   /* 16Gb  */
 359         4096                    /* 32Gb  */
 360 };
 361
 362 /*
 363  * Calculate the period of DDR clock from frequency value and set the
 364  * denominator and numerator in global variables for easy access later
 365  */
 366 static void set_ddr_clk_period(u32 freq)
 367 {
 368         /*
 369          * period = 1/freq
 370          * period_in_ns = 10^9/freq
 371          */
 372         *T_num = 1000000000;
 373         *T_den = freq;
 374         cancel_out(T_num, T_den, 200);
 375
 376 }
 377
 378 /*
 379  * Convert time in nano seconds to number of cycles of DDR clock
 380  */
 381 static inline u32 ns_2_cycles(u32 ns)
 382 {
 383         return ((ns * (*T_den)) + (*T_num) - 1) / (*T_num);
 384 }
 385
 386 /*
 387  * ns_2_cycles with the difference that the time passed is 2 times the actual
 388  * value(to avoid fractions). The cycles returned is for the original value of
 389  * the timing parameter
 390  */
 391 static inline u32 ns_x2_2_cycles(u32 ns)
 392 {
 393         return ((ns * (*T_den)) + (*T_num) * 2 - 1) / ((*T_num) * 2);
 394 }
 395
 396 /*
 397  * Find addressing table index based on the device's type(S2 or S4) and
 398  * density
 399  */
 400 s8 addressing_table_index(u8 type, u8 density, u8 width)
 401 {
 402         u8 index;
 403         if ((density > LPDDR2_DENSITY_8Gb) || (width == LPDDR2_IO_WIDTH_8))
 404                 return -1;
 405
 406         /*
 407          * Look at the way ADDR_TABLE_INDEX* values have been defined
 408          * in emif.h compared to LPDDR2_DENSITY_* values
 409          * The table is layed out in the increasing order of density
 410          * (ignoring type). The exceptions 1GS2 and 2GS2 have been placed
 411          * at the end
 412          */
 413         if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_1Gb))
 414                 index = ADDR_TABLE_INDEX1GS2;
 415         else if ((type == LPDDR2_TYPE_S2) && (density == LPDDR2_DENSITY_2Gb))
 416                 index = ADDR_TABLE_INDEX2GS2;
 417         else
 418                 index = density;
 419
 420         debug("emif: addressing table index %d\n", index);
 421
 422         return index;
 423 }
 424
 425 /*
 426  * Find the the right timing table from the array of timing
 427  * tables of the device using DDR clock frequency
 428  */
 429 static const struct lpddr2_ac_timings *get_timings_table(const struct
 430                         lpddr2_ac_timings const *const *device_timings,
 431                         u32 freq)
 432 {
 433         u32 i, temp, freq_nearest;
 434         const struct lpddr2_ac_timings *timings = 0;
 435
 436         emif_assert(freq <= MAX_LPDDR2_FREQ);
 437         emif_assert(device_timings);
 438
 439         /*
 440          * Start with the maximum allowed frequency - that is always safe
 441          */
 442         freq_nearest = MAX_LPDDR2_FREQ;
 443         /*
 444          * Find the timings table that has the max frequency value:
 445          *   i.  Above or equal to the DDR frequency - safe
 446          *   ii. The lowest that satisfies condition (i) - optimal
 447          */
 448         for (i = 0; (i < MAX_NUM_SPEEDBINS) && device_timings[i]; i++) {
 449                 temp = device_timings[i]->max_freq;
 450                 if ((temp >= freq) && (temp <= freq_nearest)) {
 451                         freq_nearest = temp;
 452                         timings = device_timings[i];
 453                 }
 454         }
 455         debug("emif: timings table: %d\n", freq_nearest);
 456         return timings;
 457 }
 458
 459 /*
 460  * Finds the value of emif_sdram_config_reg
 461  * All parameters are programmed based on the device on CS0.
 462  * If there is a device on CS1, it will be same as that on CS0 or
 463  * it will be NVM. We don't support NVM yet.
 464  * If cs1_device pointer is NULL it is assumed that there is no device
 465  * on CS1
 466  */
 467 static u32 get_sdram_config_reg(const struct lpddr2_device_details *cs0_device,
 468                                 const struct lpddr2_device_details *cs1_device,
 469                                 const struct lpddr2_addressing *addressing,
 470                                 u8 RL)
 471 {
 472         u32 config_reg = 0;
 473
 474         config_reg |=  (cs0_device->type + 4) << EMIF_REG_SDRAM_TYPE_SHIFT;
 475         config_reg |=  EMIF_INTERLEAVING_POLICY_MAX_INTERLEAVING <<
 476                         EMIF_REG_IBANK_POS_SHIFT;
 477
 478         config_reg |= cs0_device->io_width << EMIF_REG_NARROW_MODE_SHIFT;
 479
 480         config_reg |= RL << EMIF_REG_CL_SHIFT;
 481
 482         config_reg |= addressing->row_sz[cs0_device->io_width] <<
 483                         EMIF_REG_ROWSIZE_SHIFT;
 484
 485         config_reg |= addressing->num_banks << EMIF_REG_IBANK_SHIFT;
 486
 487         config_reg |= (cs1_device ? EBANK_CS1_EN : EBANK_CS1_DIS) <<
 488                         EMIF_REG_EBANK_SHIFT;
 489
 490         config_reg |= addressing->col_sz[cs0_device->io_width] <<
 491                         EMIF_REG_PAGESIZE_SHIFT;
 492
 493         return config_reg;
 494 }
 495
 496 static u32 get_sdram_ref_ctrl(u32 freq,
 497                               const struct lpddr2_addressing *addressing)
 498 {
 499         u32 ref_ctrl = 0, val = 0, freq_khz;
 500         freq_khz = freq / 1000;
 501         /*
 502          * refresh rate to be set is 'tREFI * freq in MHz
 503          * division by 10000 to account for khz and x10 in t_REFI_us_x10
 504          */
 505         val = addressing->t_REFI_us_x10 * freq_khz / 10000;
 506         ref_ctrl |= val << EMIF_REG_REFRESH_RATE_SHIFT;
 507
 508         return ref_ctrl;
 509 }
 510
 511 static u32 get_sdram_tim_1_reg(const struct lpddr2_ac_timings *timings,
 512                                const struct lpddr2_min_tck *min_tck,
 513                                const struct lpddr2_addressing *addressing)
 514 {
 515         u32 tim1 = 0, val = 0;
 516         val = max(min_tck->tWTR, ns_x2_2_cycles(timings->tWTRx2)) - 1;
 517         tim1 |= val << EMIF_REG_T_WTR_SHIFT;
 518
 519         if (addressing->num_banks == BANKS8)
 520                 val = (timings->tFAW * (*T_den) + 4 * (*T_num) - 1) /
 521                                                         (4 * (*T_num)) - 1;
 522         else
 523                 val = max(min_tck->tRRD, ns_2_cycles(timings->tRRD)) - 1;
 524
 525         tim1 |= val << EMIF_REG_T_RRD_SHIFT;
 526
 527         val = ns_2_cycles(timings->tRASmin + timings->tRPab) - 1;
 528         tim1 |= val << EMIF_REG_T_RC_SHIFT;
 529
 530         val = max(min_tck->tRAS_MIN, ns_2_cycles(timings->tRASmin)) - 1;
 531         tim1 |= val << EMIF_REG_T_RAS_SHIFT;
 532
 533         val = max(min_tck->tWR, ns_2_cycles(timings->tWR)) - 1;
 534         tim1 |= val << EMIF_REG_T_WR_SHIFT;
 535
 536         val = max(min_tck->tRCD, ns_2_cycles(timings->tRCD)) - 1;
 537         tim1 |= val << EMIF_REG_T_RCD_SHIFT;
 538
 539         val = max(min_tck->tRP_AB, ns_2_cycles(timings->tRPab)) - 1;
 540         tim1 |= val << EMIF_REG_T_RP_SHIFT;
 541
 542         return tim1;
 543 }
 544
 545 static u32 get_sdram_tim_2_reg(const struct lpddr2_ac_timings *timings,
 546                                const struct lpddr2_min_tck *min_tck)
 547 {
 548         u32 tim2 = 0, val = 0;
 549         val = max(min_tck->tCKE, timings->tCKE) - 1;
 550         tim2 |= val << EMIF_REG_T_CKE_SHIFT;
 551
 552         val = max(min_tck->tRTP, ns_x2_2_cycles(timings->tRTPx2)) - 1;
 553         tim2 |= val << EMIF_REG_T_RTP_SHIFT;
 554
 555         /*
 556          * tXSRD = tRFCab + 10 ns. XSRD and XSNR should have the
 557          * same value
 558          */
 559         val = ns_2_cycles(timings->tXSR) - 1;
 560         tim2 |= val << EMIF_REG_T_XSRD_SHIFT;
 561         tim2 |= val << EMIF_REG_T_XSNR_SHIFT;
 562
 563         val = max(min_tck->tXP, ns_x2_2_cycles(timings->tXPx2)) - 1;
 564         tim2 |= val << EMIF_REG_T_XP_SHIFT;
 565
 566         return tim2;
 567 }
 568
 569 static u32 get_sdram_tim_3_reg(const struct lpddr2_ac_timings *timings,
 570                                const struct lpddr2_min_tck *min_tck,
 571                                const struct lpddr2_addressing *addressing)
 572 {
 573         u32 tim3 = 0, val = 0;
 574         val = min(timings->tRASmax * 10 / addressing->t_REFI_us_x10 - 1, 0xF);
 575         tim3 |= val << EMIF_REG_T_RAS_MAX_SHIFT;
 576
 577         val = ns_2_cycles(timings->tRFCab) - 1;
 578         tim3 |= val << EMIF_REG_T_RFC_SHIFT;
 579
 580         val = ns_x2_2_cycles(timings->tDQSCKMAXx2) - 1;
 581         tim3 |= val << EMIF_REG_T_TDQSCKMAX_SHIFT;
 582
 583         val = ns_2_cycles(timings->tZQCS) - 1;
 584         tim3 |= val << EMIF_REG_ZQ_ZQCS_SHIFT;
 585
 586         val = max(min_tck->tCKESR, ns_2_cycles(timings->tCKESR)) - 1;
 587         tim3 |= val << EMIF_REG_T_CKESR_SHIFT;
 588
 589         return tim3;
 590 }
 591
 592 static u32 get_zq_config_reg(const struct lpddr2_device_details *cs1_device,
 593                              const struct lpddr2_addressing *addressing,
 594                              u8 volt_ramp)
 595 {
 596         u32 zq = 0, val = 0;
 597         if (volt_ramp)
 598                 val =
 599                     EMIF_ZQCS_INTERVAL_DVFS_IN_US * 10 /
 600                     addressing->t_REFI_us_x10;
 601         else
 602                 val =
 603                     EMIF_ZQCS_INTERVAL_NORMAL_IN_US * 10 /
 604                     addressing->t_REFI_us_x10;
 605         zq |= val << EMIF_REG_ZQ_REFINTERVAL_SHIFT;
 606
 607         zq |= (REG_ZQ_ZQCL_MULT - 1) << EMIF_REG_ZQ_ZQCL_MULT_SHIFT;
 608
 609         zq |= (REG_ZQ_ZQINIT_MULT - 1) << EMIF_REG_ZQ_ZQINIT_MULT_SHIFT;
 610
 611         zq |= REG_ZQ_SFEXITEN_ENABLE << EMIF_REG_ZQ_SFEXITEN_SHIFT;
 612
 613         /*
 614          * Assuming that two chipselects have a single calibration resistor
 615          * If there are indeed two calibration resistors, then this flag should
 616          * be enabled to take advantage of dual calibration feature.
 617          * This data should ideally come from board files. But considering
 618          * that none of the boards today have calibration resistors per CS,
 619          * it would be an unnecessary overhead.
 620          */
 621         zq |= REG_ZQ_DUALCALEN_DISABLE << EMIF_REG_ZQ_DUALCALEN_SHIFT;
 622
 623         zq |= REG_ZQ_CS0EN_ENABLE << EMIF_REG_ZQ_CS0EN_SHIFT;
 624
 625         zq |= (cs1_device ? 1 : 0) << EMIF_REG_ZQ_CS1EN_SHIFT;
 626
 627         return zq;
 628 }
 629
 630 static u32 get_temp_alert_config(const struct lpddr2_device_details *cs1_device,
 631                                  const struct lpddr2_addressing *addressing,
 632                                  u8 is_derated)
 633 {
 634         u32 alert = 0, interval;
 635         interval =
 636             TEMP_ALERT_POLL_INTERVAL_MS * 10000 / addressing->t_REFI_us_x10;
 637         if (is_derated)
 638                 interval *= 4;
 639         alert |= interval << EMIF_REG_TA_REFINTERVAL_SHIFT;
 640
 641         alert |= TEMP_ALERT_CONFIG_DEVCT_1 << EMIF_REG_TA_DEVCNT_SHIFT;
 642
 643         alert |= TEMP_ALERT_CONFIG_DEVWDT_32 << EMIF_REG_TA_DEVWDT_SHIFT;
 644
 645         alert |= 1 << EMIF_REG_TA_SFEXITEN_SHIFT;
 646
 647         alert |= 1 << EMIF_REG_TA_CS0EN_SHIFT;
 648
 649         alert |= (cs1_device ? 1 : 0) << EMIF_REG_TA_CS1EN_SHIFT;
 650
 651         return alert;
 652 }
 653
 654 static u32 get_read_idle_ctrl_reg(u8 volt_ramp)
 655 {
 656         u32 idle = 0, val = 0;
 657         if (volt_ramp)
 658                 val = ns_2_cycles(READ_IDLE_INTERVAL_DVFS) / 64 - 1;
 659         else
 660                 /*Maximum value in normal conditions - suggested by hw team */
 661                 val = 0x1FF;
 662         idle |= val << EMIF_REG_READ_IDLE_INTERVAL_SHIFT;
 663
 664         idle |= EMIF_REG_READ_IDLE_LEN_VAL << EMIF_REG_READ_IDLE_LEN_SHIFT;
 665
 666         return idle;
 667 }
 668
 669 static u32 get_ddr_phy_ctrl_1(u32 freq, u8 RL)
 670 {
 671         u32 phy = 0, val = 0;
 672
 673         phy |= (RL + 2) << EMIF_REG_READ_LATENCY_SHIFT;
 674
 675         if (freq <= 100000000)
 676                 val = EMIF_DLL_SLAVE_DLY_CTRL_100_MHZ_AND_LESS;
 677         else if (freq <= 200000000)
 678                 val = EMIF_DLL_SLAVE_DLY_CTRL_200_MHZ;
 679         else
 680                 val = EMIF_DLL_SLAVE_DLY_CTRL_400_MHZ;
 681         phy |= val << EMIF_REG_DLL_SLAVE_DLY_CTRL_SHIFT;
 682
 683         /* Other fields are constant magic values. Hardcode them together */
 684         phy |= EMIF_DDR_PHY_CTRL_1_BASE_VAL <<
 685                 EMIF_EMIF_DDR_PHY_CTRL_1_BASE_VAL_SHIFT;
 686
 687         return phy;
 688 }
 689
 690 static u32 get_emif_mem_size(u32 base)
 691 {
 692         u32 size_mbytes = 0, temp;
 693         struct emif_device_details dev_details;
 694         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
 695         u32 emif_nr = emif_num(base);
 696
 697         emif_reset_phy(base);
 698         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
 699                                                 &cs0_dev_details);
 700         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
 701                                                 &cs1_dev_details);
 702         emif_reset_phy(base);
 703
 704         if (dev_details.cs0_device_details) {
 705                 temp = dev_details.cs0_device_details->density;
 706                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 707         }
 708
 709         if (dev_details.cs1_device_details) {
 710                 temp = dev_details.cs1_device_details->density;
 711                 size_mbytes += lpddr2_density_2_size_in_mbytes[temp];
 712         }
 713         /* convert to bytes */
 714         return size_mbytes << 20;
 715 }
 716
 717 /* Gets the encoding corresponding to a given DMM section size */
 718 u32 get_dmm_section_size_map(u32 section_size)
 719 {
 720         /*
 721          * Section size mapping:
 722          * 0x0: 16-MiB section
 723          * 0x1: 32-MiB section
 724          * 0x2: 64-MiB section
 725          * 0x3: 128-MiB section
 726          * 0x4: 256-MiB section
 727          * 0x5: 512-MiB section
 728          * 0x6: 1-GiB section
 729          * 0x7: 2-GiB section
 730          */
 731         section_size >>= 24; /* divide by 16 MB */
 732         return log_2_n_round_down(section_size);
 733 }
 734
 735 static void emif_calculate_regs(
 736                 const struct emif_device_details *emif_dev_details,
 737                 u32 freq, struct emif_regs *regs)
 738 {
 739         u32 temp, sys_freq;
 740         const struct lpddr2_addressing *addressing;
 741         const struct lpddr2_ac_timings *timings;
 742         const struct lpddr2_min_tck *min_tck;
 743         const struct lpddr2_device_details *cs0_dev_details =
 744                                         emif_dev_details->cs0_device_details;
 745         const struct lpddr2_device_details *cs1_dev_details =
 746                                         emif_dev_details->cs1_device_details;
 747         const struct lpddr2_device_timings *cs0_dev_timings =
 748                                         emif_dev_details->cs0_device_timings;
 749
 750         emif_assert(emif_dev_details);
 751         emif_assert(regs);
 752         /*
 753          * You can not have a device on CS1 without one on CS0
 754          * So configuring EMIF without a device on CS0 doesn't
 755          * make sense
 756          */
 757         emif_assert(cs0_dev_details);
 758         emif_assert(cs0_dev_details->type != LPDDR2_TYPE_NVM);
 759         /*
 760          * If there is a device on CS1 it should be same type as CS0
 761          * (or NVM. But NVM is not supported in this driver yet)
 762          */
 763         emif_assert((cs1_dev_details == NULL) ||
 764                     (cs1_dev_details->type == LPDDR2_TYPE_NVM) ||
 765                     (cs0_dev_details->type == cs1_dev_details->type));
 766         emif_assert(freq <= MAX_LPDDR2_FREQ);
 767
 768         set_ddr_clk_period(freq);
 769
 770         /*
 771          * The device on CS0 is used for all timing calculations
 772          * There is only one set of registers for timings per EMIF. So, if the
 773          * second CS(CS1) has a device, it should have the same timings as the
 774          * device on CS0
 775          */
 776         timings = get_timings_table(cs0_dev_timings->ac_timings, freq);
 777         emif_assert(timings);
 778         min_tck = cs0_dev_timings->min_tck;
 779
 780         temp = addressing_table_index(cs0_dev_details->type,
 781                                       cs0_dev_details->density,
 782                                       cs0_dev_details->io_width);
 783
 784         emif_assert((temp >= 0));
 785         addressing = &(addressing_table[temp]);
 786         emif_assert(addressing);
 787
 788         sys_freq = get_sys_clk_freq();
 789
 790         regs->sdram_config_init = get_sdram_config_reg(cs0_dev_details,
 791                                                         cs1_dev_details,
 792                                                         addressing, RL_BOOT);
 793
 794         regs->sdram_config = get_sdram_config_reg(cs0_dev_details,
 795                                                 cs1_dev_details,
 796                                                 addressing, RL_FINAL);
 797
 798         regs->ref_ctrl = get_sdram_ref_ctrl(freq, addressing);
 799
 800         regs->sdram_tim1 = get_sdram_tim_1_reg(timings, min_tck, addressing);
 801
 802         regs->sdram_tim2 = get_sdram_tim_2_reg(timings, min_tck);
 803
 804         regs->sdram_tim3 = get_sdram_tim_3_reg(timings, min_tck, addressing);
 805
 806         regs->read_idle_ctrl = get_read_idle_ctrl_reg(LPDDR2_VOLTAGE_STABLE);
 807
 808         regs->temp_alert_config =
 809             get_temp_alert_config(cs1_dev_details, addressing, 0);
 810
 811         regs->zq_config = get_zq_config_reg(cs1_dev_details, addressing,
 812                                             LPDDR2_VOLTAGE_STABLE);
 813
 814         regs->emif_ddr_phy_ctlr_1_init =
 815                         get_ddr_phy_ctrl_1(sys_freq / 2, RL_BOOT);
 816
 817         regs->emif_ddr_phy_ctlr_1 =
 818                         get_ddr_phy_ctrl_1(freq, RL_FINAL);
 819
 820         regs->freq = freq;
 821
 822         print_timing_reg(regs->sdram_config_init);
 823         print_timing_reg(regs->sdram_config);
 824         print_timing_reg(regs->ref_ctrl);
 825         print_timing_reg(regs->sdram_tim1);
 826         print_timing_reg(regs->sdram_tim2);
 827         print_timing_reg(regs->sdram_tim3);
 828         print_timing_reg(regs->read_idle_ctrl);
 829         print_timing_reg(regs->temp_alert_config);
 830         print_timing_reg(regs->zq_config);
 831         print_timing_reg(regs->emif_ddr_phy_ctlr_1);
 832         print_timing_reg(regs->emif_ddr_phy_ctlr_1_init);
 833 }
 834 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 835
 836 #ifdef CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION
 837 const char *get_lpddr2_type(u8 type_id)
 838 {
 839         switch (type_id) {
 840         case LPDDR2_TYPE_S4:
 841                 return "LPDDR2-S4";
 842         case LPDDR2_TYPE_S2:
 843                 return "LPDDR2-S2";
 844         default:
 845                 return NULL;
 846         }
 847 }
 848
 849 const char *get_lpddr2_io_width(u8 width_id)
 850 {
 851         switch (width_id) {
 852         case LPDDR2_IO_WIDTH_8:
 853                 return "x8";
 854         case LPDDR2_IO_WIDTH_16:
 855                 return "x16";
 856         case LPDDR2_IO_WIDTH_32:
 857                 return "x32";
 858         default:
 859                 return NULL;
 860         }
 861 }
 862
 863 const char *get_lpddr2_manufacturer(u32 manufacturer)
 864 {
 865         switch (manufacturer) {
 866         case LPDDR2_MANUFACTURER_SAMSUNG:
 867                 return "Samsung";
 868         case LPDDR2_MANUFACTURER_QIMONDA:
 869                 return "Qimonda";
 870         case LPDDR2_MANUFACTURER_ELPIDA:
 871                 return "Elpida";
 872         case LPDDR2_MANUFACTURER_ETRON:
 873                 return "Etron";
 874         case LPDDR2_MANUFACTURER_NANYA:
 875                 return "Nanya";
 876         case LPDDR2_MANUFACTURER_HYNIX:
 877                 return "Hynix";
 878         case LPDDR2_MANUFACTURER_MOSEL:
 879                 return "Mosel";
 880         case LPDDR2_MANUFACTURER_WINBOND:
 881                 return "Winbond";
 882         case LPDDR2_MANUFACTURER_ESMT:
 883                 return "ESMT";
 884         case LPDDR2_MANUFACTURER_SPANSION:
 885                 return "Spansion";
 886         case LPDDR2_MANUFACTURER_SST:
 887                 return "SST";
 888         case LPDDR2_MANUFACTURER_ZMOS:
 889                 return "ZMOS";
 890         case LPDDR2_MANUFACTURER_INTEL:
 891                 return "Intel";
 892         case LPDDR2_MANUFACTURER_NUMONYX:
 893                 return "Numonyx";
 894         case LPDDR2_MANUFACTURER_MICRON:
 895                 return "Micron";
 896         default:
 897                 return NULL;
 898         }
 899 }
 900
 901 static void display_sdram_details(u32 emif_nr, u32 cs,
 902                                   struct lpddr2_device_details *device)
 903 {
 904         const char *mfg_str;
 905         const char *type_str;
 906         char density_str[10];
 907         u32 density;
 908
 909         debug("EMIF%d CS%d\t", emif_nr, cs);
 910
 911         if (!device) {
 912                 debug("None\n");
 913                 return;
 914         }
 915
 916         mfg_str = get_lpddr2_manufacturer(device->manufacturer);
 917         type_str = get_lpddr2_type(device->type);
 918
 919         density = lpddr2_density_2_size_in_mbytes[device->density];
 920         if ((density / 1024 * 1024) == density) {
 921                 density /= 1024;
 922                 sprintf(density_str, "%d GB", density);
 923         } else
 924                 sprintf(density_str, "%d MB", density);
 925         if (mfg_str && type_str)
 926                 debug("%s\t\t%s\t%s\n", mfg_str, type_str, density_str);
 927 }
 928
 929 static u8 is_lpddr2_sdram_present(u32 base, u32 cs,
 930                                   struct lpddr2_device_details *lpddr2_device)
 931 {
 932         u32 mr = 0, temp;
 933
 934         mr = get_mr(base, cs, LPDDR2_MR0);
 935         if (mr > 0xFF) {
 936                 /* Mode register value bigger than 8 bit */
 937                 return 0;
 938         }
 939
 940         temp = (mr & LPDDR2_MR0_DI_MASK) >> LPDDR2_MR0_DI_SHIFT;
 941         if (temp) {
 942                 /* Not SDRAM */
 943                 return 0;
 944         }
 945         temp = (mr & LPDDR2_MR0_DNVI_MASK) >> LPDDR2_MR0_DNVI_SHIFT;
 946
 947         if (temp) {
 948                 /* DNV supported - But DNV is only supported for NVM */
 949                 return 0;
 950         }
 951
 952         mr = get_mr(base, cs, LPDDR2_MR4);
 953         if (mr > 0xFF) {
 954                 /* Mode register value bigger than 8 bit */
 955                 return 0;
 956         }
 957
 958         mr = get_mr(base, cs, LPDDR2_MR5);
 959         if (mr > 0xFF) {
 960                 /* Mode register value bigger than 8 bit */
 961                 return 0;
 962         }
 963
 964         if (!get_lpddr2_manufacturer(mr)) {
 965                 /* Manufacturer not identified */
 966                 return 0;
 967         }
 968         lpddr2_device->manufacturer = mr;
 969
 970         mr = get_mr(base, cs, LPDDR2_MR6);
 971         if (mr >= 0xFF) {
 972                 /* Mode register value bigger than 8 bit */
 973                 return 0;
 974         }
 975
 976         mr = get_mr(base, cs, LPDDR2_MR7);
 977         if (mr >= 0xFF) {
 978                 /* Mode register value bigger than 8 bit */
 979                 return 0;
 980         }
 981
 982         mr = get_mr(base, cs, LPDDR2_MR8);
 983         if (mr >= 0xFF) {
 984                 /* Mode register value bigger than 8 bit */
 985                 return 0;
 986         }
 987
 988         temp = (mr & MR8_TYPE_MASK) >> MR8_TYPE_SHIFT;
 989         if (!get_lpddr2_type(temp)) {
 990                 /* Not SDRAM */
 991                 return 0;
 992         }
 993         lpddr2_device->type = temp;
 994
 995         temp = (mr & MR8_DENSITY_MASK) >> MR8_DENSITY_SHIFT;
 996         if (temp > LPDDR2_DENSITY_32Gb) {
 997                 /* Density not supported */
 998                 return 0;
 999         }
1000         lpddr2_device->density = temp;
1001
1002         temp = (mr & MR8_IO_WIDTH_MASK) >> MR8_IO_WIDTH_SHIFT;
1003         if (!get_lpddr2_io_width(temp)) {
1004                 /* IO width unsupported value */
1005                 return 0;
1006         }
1007         lpddr2_device->io_width = temp;
1008
1009         /*
1010          * If all the above tests pass we should
1011          * have a device on this chip-select
1012          */
1013         return 1;
1014 }
1015
1016 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
1017                         struct lpddr2_device_details *lpddr2_dev_details)
1018 {
1019         u32 phy;
1020         u32 base = (emif_nr == 1) ? EMIF1_BASE : EMIF2_BASE;
1021
1022         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1023
1024         if (!lpddr2_dev_details)
1025                 return NULL;
1026
1027         /* Do the minimum init for mode register accesses */
1028         if (!(running_from_sdram() || warm_reset())) {
1029                 phy = get_ddr_phy_ctrl_1(get_sys_clk_freq() / 2, RL_BOOT);
1030                 writel(phy, &emif->emif_ddr_phy_ctrl_1);
1031         }
1032
1033         if (!(is_lpddr2_sdram_present(base, cs, lpddr2_dev_details)))
1034                 return NULL;
1035
1036         display_sdram_details(emif_num(base), cs, lpddr2_dev_details);
1037
1038         return lpddr2_dev_details;
1039 }
1040 #endif /* CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION */
1041
1042 static void do_sdram_init(u32 base)
1043 {
1044         const struct emif_regs *regs;
1045         u32 in_sdram, emif_nr;
1046
1047         debug(">>do_sdram_init() %x\n", base);
1048
1049         in_sdram = running_from_sdram();
1050         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
1051
1052 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1053         emif_get_reg_dump(emif_nr, &regs);
1054         if (!regs) {
1055                 debug("EMIF: reg dump not provided\n");
1056                 return;
1057         }
1058 #else
1059         /*
1060          * The user has not provided the register values. We need to
1061          * calculate it based on the timings and the DDR frequency
1062          */
1063         struct emif_device_details dev_details;
1064         struct emif_regs calculated_regs;
1065
1066         /*
1067          * Get device details:
1068          * - Discovered if CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION is set
1069          * - Obtained from user otherwise
1070          */
1071         struct lpddr2_device_details cs0_dev_details, cs1_dev_details;
1072         emif_reset_phy(base);
1073         dev_details.cs0_device_details = emif_get_device_details(emif_nr, CS0,
1074                                                 &cs0_dev_details);
1075         dev_details.cs1_device_details = emif_get_device_details(emif_nr, CS1,
1076                                                 &cs1_dev_details);
1077         emif_reset_phy(base);
1078
1079         /* Return if no devices on this EMIF */
1080         if (!dev_details.cs0_device_details &&
1081             !dev_details.cs1_device_details) {
1082                 return;
1083         }
1084
1085         /*
1086          * Get device timings:
1087          * - Default timings specified by JESD209-2 if
1088          *   CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS is set
1089          * - Obtained from user otherwise
1090          */
1091         emif_get_device_timings(emif_nr, &dev_details.cs0_device_timings,
1092                                 &dev_details.cs1_device_timings);
1093
1094         /* Calculate the register values */
1095         emif_calculate_regs(&dev_details, omap_ddr_clk(), &calculated_regs);
1096         regs = &calculated_regs;
1097 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
1098
1099         /*
1100          * Initializing the LPDDR2 device can not happen from SDRAM.
1101          * Changing the timing registers in EMIF can happen(going from one
1102          * OPP to another)
1103          */
1104         if (!(in_sdram || warm_reset())) {
1105                 if (emif_sdram_type() == EMIF_SDRAM_TYPE_LPDDR2)
1106                         lpddr2_init(base, regs);
1107                 else
1108                         ddr3_init(base, regs);
1109         }
1110         if (warm_reset() && (emif_sdram_type() == EMIF_SDRAM_TYPE_DDR3)) {
1111                 set_lpmode_selfrefresh(base);
1112                 emif_reset_phy(base);
1113                 ddr3_leveling(base, regs);
1114         }
1115
1116         /* Write to the shadow registers */
1117         emif_update_timings(base, regs);
1118
1119         debug("<<do_sdram_init() %x\n", base);
1120 }
1121
1122 void emif_post_init_config(u32 base)
1123 {
1124         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
1125         u32 omap_rev = omap_revision();
1126
1127         /* reset phy on ES2.0 */
1128         if (omap_rev == OMAP4430_ES2_0)
1129                 emif_reset_phy(base);
1130
1131         /* Put EMIF back in smart idle on ES1.0 */
1132         if (omap_rev == OMAP4430_ES1_0)
1133                 writel(0x80000000, &emif->emif_pwr_mgmt_ctrl);
1134 }
1135
1136 void dmm_init(u32 base)
1137 {
1138         const struct dmm_lisa_map_regs *lisa_map_regs;
1139         u32 i, section, valid;
1140
1141 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
1142         emif_get_dmm_regs(&lisa_map_regs);
1143 #else
1144         u32 emif1_size, emif2_size, mapped_size, section_map = 0;
1145         u32 section_cnt, sys_addr;
1146         struct dmm_lisa_map_regs lis_map_regs_calculated = {0};
1147
1148         mapped_size = 0;
1149         section_cnt = 3;
1150         sys_addr = CONFIG_SYS_SDRAM_BASE;
1151         emif1_size = get_emif_mem_size(EMIF1_BASE);
1152         emif2_size = get_emif_mem_size(EMIF2_BASE);
1153         debug("emif1_size 0x%x emif2_size 0x%x\n", emif1_size, emif2_size);
1154
1155         if (!emif1_size && !emif2_size)
1156                 return;
1157
1158         /* symmetric interleaved section */
1159         if (emif1_size && emif2_size) {
1160                 mapped_size = min(emif1_size, emif2_size);
1161                 section_map = DMM_LISA_MAP_INTERLEAVED_BASE_VAL;
1162                 section_map |= 0 << EMIF_SDRC_ADDR_SHIFT;
1163                 /* only MSB */
1164                 section_map |= (sys_addr >> 24) <<
1165                                 EMIF_SYS_ADDR_SHIFT;
1166                 section_map |= get_dmm_section_size_map(mapped_size * 2)
1167                                 << EMIF_SYS_SIZE_SHIFT;
1168                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1169                 emif1_size -= mapped_size;
1170                 emif2_size -= mapped_size;
1171                 sys_addr += (mapped_size * 2);
1172                 section_cnt--;
1173         }
1174
1175         /*
1176          * Single EMIF section(we can have a maximum of 1 single EMIF
1177          * section- either EMIF1 or EMIF2 or none, but not both)
1178          */
1179         if (emif1_size) {
1180                 section_map = DMM_LISA_MAP_EMIF1_ONLY_BASE_VAL;
1181                 section_map |= get_dmm_section_size_map(emif1_size)
1182                                 << EMIF_SYS_SIZE_SHIFT;
1183                 /* only MSB */
1184                 section_map |= (mapped_size >> 24) <<
1185                                 EMIF_SDRC_ADDR_SHIFT;
1186                 /* only MSB */
1187                 section_map |= (sys_addr >> 24) << EMIF_SYS_ADDR_SHIFT;
1188                 section_cnt--;
1189         }
1190         if (emif2_size) {
1191                 section_map = DMM_LISA_MAP_EMIF2_ONLY_BASE_VAL;
1192                 section_map |= get_dmm_section_size_map(emif2_size) <<
1193                                 EMIF_SYS_SIZE_SHIFT;
1194                 /* only MSB */
1195                 section_map |= mapped_size >> 24 << EMIF_SDRC_ADDR_SHIFT;
1196                 /* only MSB */
1197                 section_map |= sys_addr >> 24 << EMIF_SYS_ADDR_SHIFT;
1198                 section_cnt--;
1199         }
1200
1201         if (section_cnt == 2) {
1202                 /* Only 1 section - either symmetric or single EMIF */
1203                 lis_map_regs_calculated.dmm_lisa_map_3 = section_map;
1204                 lis_map_regs_calculated.dmm_lisa_map_2 = 0;
1205                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1206         } else {
1207                 /* 2 sections - 1 symmetric, 1 single EMIF */
1208                 lis_map_regs_calculated.dmm_lisa_map_2 = section_map;
1209                 lis_map_regs_calculated.dmm_lisa_map_1 = 0;
1210         }
1211
1212         /* TRAP for invalid TILER mappings in section 0 */
1213         lis_map_regs_calculated.dmm_lisa_map_0 = DMM_LISA_MAP_0_INVAL_ADDR_TRAP;
1214
1215         if (omap_revision() >= OMAP4460_ES1_0)
1216                 lis_map_regs_calculated.is_ma_present = 1;
1217
1218         lisa_map_regs = &lis_map_regs_calculated;
1219 #endif
1220         struct dmm_lisa_map_regs *hw_lisa_map_regs =
1221             (struct dmm_lisa_map_regs *)base;
1222
1223         writel(0, &hw_lisa_map_regs->dmm_lisa_map_3);
1224         writel(0, &hw_lisa_map_regs->dmm_lisa_map_2);
1225         writel(0, &hw_lisa_map_regs->dmm_lisa_map_1);
1226         writel(0, &hw_lisa_map_regs->dmm_lisa_map_0);
1227
1228         writel(lisa_map_regs->dmm_lisa_map_3,
1229                 &hw_lisa_map_regs->dmm_lisa_map_3);
1230         writel(lisa_map_regs->dmm_lisa_map_2,
1231                 &hw_lisa_map_regs->dmm_lisa_map_2);
1232         writel(lisa_map_regs->dmm_lisa_map_1,
1233                 &hw_lisa_map_regs->dmm_lisa_map_1);
1234         writel(lisa_map_regs->dmm_lisa_map_0,
1235                 &hw_lisa_map_regs->dmm_lisa_map_0);
1236
1237         if (lisa_map_regs->is_ma_present) {
1238                 hw_lisa_map_regs =
1239                     (struct dmm_lisa_map_regs *)MA_BASE;
1240
1241                 writel(lisa_map_regs->dmm_lisa_map_3,
1242                         &hw_lisa_map_regs->dmm_lisa_map_3);
1243                 writel(lisa_map_regs->dmm_lisa_map_2,
1244                         &hw_lisa_map_regs->dmm_lisa_map_2);
1245                 writel(lisa_map_regs->dmm_lisa_map_1,
1246                         &hw_lisa_map_regs->dmm_lisa_map_1);
1247                 writel(lisa_map_regs->dmm_lisa_map_0,
1248                         &hw_lisa_map_regs->dmm_lisa_map_0);
1249         }
1250
1251         /*
1252          * EMIF should be configured only when
1253          * memory is mapped on it. Using emif1_enabled
1254          * and emif2_enabled variables for this.
1255          */
1256         emif1_enabled = 0;
1257         emif2_enabled = 0;
1258         for (i = 0; i < 4; i++) {
1259                 section = __raw_readl(DMM_BASE + i*4);
1260                 valid = (section & EMIF_SDRC_MAP_MASK) >>
1261                         (EMIF_SDRC_MAP_SHIFT);
1262                 if (valid == 3) {
1263                         emif1_enabled = 1;
1264                         emif2_enabled = 1;
1265                         break;
1266                 } else if (valid == 1) {
1267                         emif1_enabled = 1;
1268                 } else if (valid == 2) {
1269                         emif2_enabled = 1;
1270                 }
1271         }
1272
1273 }
1274
1275 static void do_bug0039_workaround(u32 base)
1276 {
1277         u32 val, i, clkctrl;
1278         struct emif_reg_struct *emif_base = (struct emif_reg_struct *)base;
1279         const struct read_write_regs *bug_00339_regs;
1280         u32 iterations;
1281         u32 *phy_status_base = &emif_base->emif_ddr_phy_status[0];
1282         u32 *phy_ctrl_base = &emif_base->emif_ddr_ext_phy_ctrl_1;
1283
1284         if (is_dra7xx())
1285                 phy_status_base++;
1286
1287         bug_00339_regs = get_bug_regs(&iterations);
1288
1289         /* Put EMIF in to idle */
1290         clkctrl = __raw_readl((*prcm)->cm_memif_clkstctrl);
1291         __raw_writel(0x0, (*prcm)->cm_memif_clkstctrl);
1292
1293         /* Copy the phy status registers in to phy ctrl shadow registers */
1294         for (i = 0; i < iterations; i++) {
1295                 val = __raw_readl(phy_status_base +
1296                                   bug_00339_regs[i].read_reg - 1);
1297
1298                 __raw_writel(val, phy_ctrl_base +
1299                              ((bug_00339_regs[i].write_reg - 1) << 1));
1300
1301                 __raw_writel(val, phy_ctrl_base +
1302                              (bug_00339_regs[i].write_reg << 1) - 1);
1303         }
1304
1305         /* Disable leveling */
1306         writel(0x0, &emif_base->emif_rd_wr_lvl_rmp_ctl);
1307
1308         __raw_writel(clkctrl,  (*prcm)->cm_memif_clkstctrl);
1309 }
1310
1311 /*
1312  * SDRAM initialization:
1313  * SDRAM initialization has two parts:
1314  * 1. Configuring the SDRAM device
1315  * 2. Update the AC timings related parameters in the EMIF module
1316  * (1) should be done only once and should not be done while we are
1317  * running from SDRAM.
1318  * (2) can and should be done more than once if OPP changes.
1319  * Particularly, this may be needed when we boot without SPL and
1320  * and using Configuration Header(CH). ROM code supports only at 50% OPP
1321  * at boot (low power boot). So u-boot has to switch to OPP100 and update
1322  * the frequency. So,
1323  * Doing (1) and (2) makes sense - first time initialization
1324  * Doing (2) and not (1) makes sense - OPP change (when using CH)
1325  * Doing (1) and not (2) doen't make sense
1326  * See do_sdram_init() for the details
1327  */
1328 void sdram_init(void)
1329 {
1330         u32 in_sdram, size_prog, size_detect;
1331         u32 sdram_type = emif_sdram_type();
1332
1333         debug(">>sdram_init()\n");
1334
1335         if (omap_hw_init_context() == OMAP_INIT_CONTEXT_UBOOT_AFTER_SPL)
1336                 return;
1337
1338         in_sdram = running_from_sdram();
1339         debug("in_sdram = %d\n", in_sdram);
1340
1341         if (!in_sdram) {
1342                 if ((sdram_type == EMIF_SDRAM_TYPE_LPDDR2) && !warm_reset())
1343                         bypass_dpll((*prcm)->cm_clkmode_dpll_core);
1344                 else if (sdram_type == EMIF_SDRAM_TYPE_DDR3)
1345                         writel(CM_DLL_CTRL_NO_OVERRIDE, (*prcm)->cm_dll_ctrl);
1346         }
1347
1348         if (!in_sdram)
1349                 dmm_init(DMM_BASE);
1350
1351         if (emif1_enabled)
1352                 do_sdram_init(EMIF1_BASE);
1353
1354         if (emif2_enabled)
1355                 do_sdram_init(EMIF2_BASE);
1356
1357         if (!(in_sdram || warm_reset())) {
1358                 if (emif1_enabled)
1359                         emif_post_init_config(EMIF1_BASE);
1360                 if (emif2_enabled)
1361                         emif_post_init_config(EMIF2_BASE);
1362         }
1363
1364         /* for the shadow registers to take effect */
1365         if (sdram_type == EMIF_SDRAM_TYPE_LPDDR2)
1366                 freq_update_core();
1367
1368         /* Do some testing after the init */
1369         if (!in_sdram) {
1370                 size_prog = omap_sdram_size();
1371                 size_prog = log_2_n_round_down(size_prog);
1372                 size_prog = (1 << size_prog);
1373
1374                 size_detect = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
1375                                                 size_prog);
1376                 /* Compare with the size programmed */
1377                 if (size_detect != size_prog) {
1378                         printf("SDRAM: identified size not same as expected"
1379                                 " size identified: %x expected: %x\n",
1380                                 size_detect,
1381                                 size_prog);
1382                 } else
1383                         debug("get_ram_size() successful");
1384         }
1385
1386         if (sdram_type == EMIF_SDRAM_TYPE_DDR3 &&
1387             (!in_sdram && !warm_reset())) {
1388                 do_bug0039_workaround(EMIF1_BASE);
1389                 do_bug0039_workaround(EMIF2_BASE);
1390         }
1391
1392         debug("<<sdram_init()\n");
1393 }