arch/arm/cpu/armv7/omap-common/mem-common.c

   1 /*
   2  * (C) Copyright 2010
   3  * Texas Instruments, <www.ti.com>
   4  *
   5  * Author :
   6  *     Mansoor Ahamed <mansoor.ahamed@ti.com>
   7  *
   8  * Initial Code from:
   9  *     Manikandan Pillai <mani.pillai@ti.com>
  10  *     Richard Woodruff <r-woodruff2@ti.com>
  11  *     Syed Mohammed Khasim <khasim@ti.com>
  12  *
  13  * SPDX-License-Identifier:     GPL-2.0+
  14  */
  15
  16 #include <common.h>
  17 #include <asm/io.h>
  18 #include <asm/arch/cpu.h>
  19 #include <asm/arch/mem.h>
  20 #include <asm/arch/sys_proto.h>
  21 #include <command.h>
  22 #include <linux/mtd/omap_gpmc.h>
  23
  24 struct gpmc *gpmc_cfg;
  25
  26 #if defined(CONFIG_OMAP34XX)
  27 /********************************************************
  28  *  mem_ok() - test used to see if timings are correct
  29  *             for a part. Helps in guessing which part
  30  *             we are currently using.
  31  *******************************************************/
  32 u32 mem_ok(u32 cs)
  33 {
  34         u32 val1, val2, addr;
  35         u32 pattern = 0x12345678;
  36
  37         addr = OMAP34XX_SDRC_CS0 + get_sdr_cs_offset(cs);
  38
  39         writel(0x0, addr + 0x400);      /* clear pos A */
  40         writel(pattern, addr);          /* pattern to pos B */
  41         writel(0x0, addr + 4);          /* remove pattern off the bus */
  42         val1 = readl(addr + 0x400);     /* get pos A value */
  43         val2 = readl(addr);             /* get val2 */
  44         writel(0x0, addr + 0x400);      /* clear pos A */
  45
  46         if ((val1 != 0) || (val2 != pattern))   /* see if pos A val changed */
  47                 return 0;
  48         else
  49                 return 1;
  50 }
  51 #endif
  52
  53 void enable_gpmc_cs_config(const u32 *gpmc_config, struct gpmc_cs *cs, u32 base,
  54                         u32 size)
  55 {
  56         writel(0, &cs->config7);
  57         sdelay(1000);
  58         /* Delay for settling */
  59         writel(gpmc_config[0], &cs->config1);
  60         writel(gpmc_config[1], &cs->config2);
  61         writel(gpmc_config[2], &cs->config3);
  62         writel(gpmc_config[3], &cs->config4);
  63         writel(gpmc_config[4], &cs->config5);
  64         writel(gpmc_config[5], &cs->config6);
  65         /* Enable the config */
  66         writel((((size & 0xF) << 8) | ((base >> 24) & 0x3F) |
  67                 (1 << 6)), &cs->config7);
  68         sdelay(2000);
  69 }
  70
  71 /*****************************************************
  72  * gpmc_init(): init gpmc bus
  73  * Init GPMC for x16, MuxMode (SDRAM in x32).
  74  * This code can only be executed from SRAM or SDRAM.
  75  *****************************************************/
  76 void gpmc_init(void)
  77 {
  78         /* putting a blanket check on GPMC based on ZeBu for now */
  79         gpmc_cfg = (struct gpmc *)GPMC_BASE;
  80 #if defined(CONFIG_NOR)
  81 /* configure GPMC for NOR */
  82         const u32 gpmc_regs[GPMC_MAX_REG] = {   STNOR_GPMC_CONFIG1,
  83                                                 STNOR_GPMC_CONFIG2,
  84                                                 STNOR_GPMC_CONFIG3,
  85                                                 STNOR_GPMC_CONFIG4,
  86                                                 STNOR_GPMC_CONFIG5,
  87                                                 STNOR_GPMC_CONFIG6,
  88                                                 STNOR_GPMC_CONFIG7
  89                                                 };
  90         u32 size = GPMC_SIZE_16M;
  91         u32 base = CONFIG_SYS_FLASH_BASE;
  92 #elif defined(CONFIG_NAND) || defined(CONFIG_CMD_NAND)
  93 /* configure GPMC for NAND */
  94         const u32  gpmc_regs[GPMC_MAX_REG] = {  M_NAND_GPMC_CONFIG1,
  95                                                 M_NAND_GPMC_CONFIG2,
  96                                                 M_NAND_GPMC_CONFIG3,
  97                                                 M_NAND_GPMC_CONFIG4,
  98                                                 M_NAND_GPMC_CONFIG5,
  99                                                 M_NAND_GPMC_CONFIG6,
 100                                                 0
 101                                                 };
 102         u32 size = GPMC_SIZE_256M;
 103         u32 base = CONFIG_SYS_NAND_BASE;
 104 #elif defined(CONFIG_CMD_ONENAND)
 105         const u32 gpmc_regs[GPMC_MAX_REG] = {   ONENAND_GPMC_CONFIG1,
 106                                                 ONENAND_GPMC_CONFIG2,
 107                                                 ONENAND_GPMC_CONFIG3,
 108                                                 ONENAND_GPMC_CONFIG4,
 109                                                 ONENAND_GPMC_CONFIG5,
 110                                                 ONENAND_GPMC_CONFIG6,
 111                                                 0
 112                                                 };
 113         u32 base = PISMO1_ONEN_BASE;
 114         u32 size = PISMO1_ONEN_SIZE;
 115 #else
 116         const u32 gpmc_regs[GPMC_MAX_REG] = { 0, 0, 0, 0, 0, 0, 0 };
 117         u32 size = 0;
 118         u32 base = 0;
 119 #endif
 120         /* global settings */
 121         writel(0x00000008, &gpmc_cfg->sysconfig);
 122         writel(0x00000000, &gpmc_cfg->irqstatus);
 123         writel(0x00000000, &gpmc_cfg->irqenable);
 124         /* disable timeout, set a safe reset value */
 125         writel(0x00001ff0, &gpmc_cfg->timeout_control);
 126 #ifdef CONFIG_NOR
 127         writel(0x00000200, &gpmc_cfg->config);
 128 #else
 129         writel(0x00000012, &gpmc_cfg->config);
 130 #endif
 131         /*
 132          * Disable the GPMC0 config set by ROM code
 133          */
 134         writel(0, &gpmc_cfg->cs[0].config7);
 135         sdelay(1000);
 136         /* enable chip-select specific configurations */
 137         if (base != 0)
 138                 enable_gpmc_cs_config(gpmc_regs, &gpmc_cfg->cs[0], base, size);
 139 }