arch/arm/cpu/armv7/omap4/sdram_elpida.c

   1 /*
   2  * Timing and Organization details of the Elpida parts used in OMAP4
   3  * SDPs and Panda
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <asm/emif.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 /*
  17  * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  18  * SDP and Panda. Since the parts used and geometry are identical for
  19  * SDP and Panda for a given OMAP4 revision, this information is kept
  20  * here instead of being in board directory. However the key functions
  21  * exported are weakly linked so that they can be over-ridden in the board
  22  * directory if there is a OMAP4 board in the future that uses a different
  23  * memory device or geometry.
  24  *
  25  * For any new board with different memory devices over-ride one or more
  26  * of the following functions as per the CONFIG flags you intend to enable:
  27  * - emif_get_reg_dump()
  28  * - emif_get_dmm_regs()
  29  * - emif_get_device_details()
  30  * - emif_get_device_timings()
  31  */
  32
  33 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  34
  35 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  36         .sdram_config_init              = 0x80000eb9,
  37         .sdram_config                   = 0x80001ab9,
  38         .ref_ctrl                       = 0x0000030c,
  39         .sdram_tim1                     = 0x08648311,
  40         .sdram_tim2                     = 0x101b06ca,
  41         .sdram_tim3                     = 0x0048a19f,
  42         .read_idle_ctrl                 = 0x000501ff,
  43         .zq_config                      = 0x500b3214,
  44         .temp_alert_config              = 0xd8016893,
  45         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  46         .emif_ddr_phy_ctlr_1            = 0x049ff808
  47 };
  48
  49 static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  50         .sdram_config_init              = 0x80000eb1,
  51         .sdram_config                   = 0x80001ab1,
  52         .ref_ctrl                       = 0x000005cd,
  53         .sdram_tim1                     = 0x10cb0622,
  54         .sdram_tim2                     = 0x20350d52,
  55         .sdram_tim3                     = 0x00b1431f,
  56         .read_idle_ctrl                 = 0x000501ff,
  57         .zq_config                      = 0x500b3214,
  58         .temp_alert_config              = 0x58016893,
  59         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  60         .emif_ddr_phy_ctlr_1            = 0x049ff418
  61 };
  62
  63 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  64         .sdram_config_init              = 0x80000eb9,
  65         .sdram_config                   = 0x80001ab9,
  66         .ref_ctrl                       = 0x00000618,
  67         .sdram_tim1                     = 0x10eb0662,
  68         .sdram_tim2                     = 0x20370dd2,
  69         .sdram_tim3                     = 0x00b1c33f,
  70         .read_idle_ctrl                 = 0x000501ff,
  71         .zq_config                      = 0xd00b3214,
  72         .temp_alert_config              = 0xd8016893,
  73         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  74         .emif_ddr_phy_ctlr_1            = 0x049ff418
  75 };
  76
  77 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  78         .dmm_lisa_map_0 = 0xFF020100,
  79         .dmm_lisa_map_1 = 0,
  80         .dmm_lisa_map_2 = 0,
  81         .dmm_lisa_map_3 = 0x80540300,
  82         .is_ma_present  = 0x0
  83 };
  84
  85 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
  86         .dmm_lisa_map_0 = 0xFF020100,
  87         .dmm_lisa_map_1 = 0,
  88         .dmm_lisa_map_2 = 0,
  89         .dmm_lisa_map_3 = 0x80640300,
  90         .is_ma_present  = 0x0
  91 };
  92
  93 const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
  94         .dmm_lisa_map_0 = 0xFF020100,
  95         .dmm_lisa_map_1 = 0,
  96         .dmm_lisa_map_2 = 0,
  97         .dmm_lisa_map_3 = 0x80640300,
  98         .is_ma_present  = 0x1
  99 };
 100
 101 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 102 {
 103         u32 omap4_rev = omap_revision();
 104
 105         /* Same devices and geometry on both EMIFs */
 106         if (omap4_rev == OMAP4430_ES1_0)
 107                 *regs = &emif_regs_elpida_380_mhz_1cs;
 108         else if (omap4_rev == OMAP4430_ES2_0)
 109                 *regs = &emif_regs_elpida_200_mhz_2cs;
 110         else
 111                 *regs = &emif_regs_elpida_400_mhz_2cs;
 112 }
 113 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 114         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 115
 116 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 117                                                 **dmm_lisa_regs)
 118 {
 119         u32 omap_rev = omap_revision();
 120
 121         if (omap_rev == OMAP4430_ES1_0)
 122                 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 123         else if (omap_rev < OMAP4460_ES1_0)
 124                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 125         else
 126                 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
 127 }
 128
 129 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 130         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 131
 132 #else
 133
 134 static const struct lpddr2_device_details elpida_2G_S4_details = {
 135         .type           = LPDDR2_TYPE_S4,
 136         .density        = LPDDR2_DENSITY_2Gb,
 137         .io_width       = LPDDR2_IO_WIDTH_32,
 138         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 139 };
 140
 141 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 142                         struct lpddr2_device_details *lpddr2_dev_details)
 143 {
 144         u32 omap_rev = omap_revision();
 145
 146         /* EMIF1 & EMIF2 have identical configuration */
 147         if ((omap_rev == OMAP4430_ES1_0) && (cs == CS1)) {
 148                 /* Nothing connected on CS1 for ES1.0 */
 149                 return NULL;
 150         } else {
 151                 /* In all other cases Elpida 2G device */
 152                 *lpddr2_dev_details = elpida_2G_S4_details;
 153                 return lpddr2_dev_details;
 154         }
 155 }
 156
 157 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 158                         struct lpddr2_device_details *lpddr2_dev_details)
 159         __attribute__((weak, alias("emif_get_device_details_sdp")));
 160
 161 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 162
 163 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 164 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 165         .max_freq       = 400000000,
 166         .RL             = 6,
 167         .tRPab          = 21,
 168         .tRCD           = 18,
 169         .tWR            = 15,
 170         .tRASmin        = 42,
 171         .tRRD           = 10,
 172         .tWTRx2         = 15,
 173         .tXSR           = 140,
 174         .tXPx2          = 15,
 175         .tRFCab         = 130,
 176         .tRTPx2         = 15,
 177         .tCKE           = 3,
 178         .tCKESR         = 15,
 179         .tZQCS          = 90,
 180         .tZQCL          = 360,
 181         .tZQINIT        = 1000,
 182         .tDQSCKMAXx2    = 11,
 183         .tRASmax        = 70,
 184         .tFAW           = 50
 185 };
 186
 187 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
 188         .max_freq       = 333000000,
 189         .RL             = 5,
 190         .tRPab          = 21,
 191         .tRCD           = 18,
 192         .tWR            = 15,
 193         .tRASmin        = 42,
 194         .tRRD           = 10,
 195         .tWTRx2         = 15,
 196         .tXSR           = 140,
 197         .tXPx2          = 15,
 198         .tRFCab         = 130,
 199         .tRTPx2         = 15,
 200         .tCKE           = 3,
 201         .tCKESR         = 15,
 202         .tZQCS          = 90,
 203         .tZQCL          = 360,
 204         .tZQINIT        = 1000,
 205         .tDQSCKMAXx2    = 11,
 206         .tRASmax        = 70,
 207         .tFAW           = 50
 208 };
 209
 210 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
 211         .max_freq       = 200000000,
 212         .RL             = 3,
 213         .tRPab          = 21,
 214         .tRCD           = 18,
 215         .tWR            = 15,
 216         .tRASmin        = 42,
 217         .tRRD           = 10,
 218         .tWTRx2         = 20,
 219         .tXSR           = 140,
 220         .tXPx2          = 15,
 221         .tRFCab         = 130,
 222         .tRTPx2         = 15,
 223         .tCKE           = 3,
 224         .tCKESR         = 15,
 225         .tZQCS          = 90,
 226         .tZQCL          = 360,
 227         .tZQINIT        = 1000,
 228         .tDQSCKMAXx2    = 11,
 229         .tRASmax        = 70,
 230         .tFAW           = 50
 231 };
 232
 233 static const struct lpddr2_min_tck min_tck_elpida = {
 234         .tRL            = 3,
 235         .tRP_AB         = 3,
 236         .tRCD           = 3,
 237         .tWR            = 3,
 238         .tRAS_MIN       = 3,
 239         .tRRD           = 2,
 240         .tWTR           = 2,
 241         .tXP            = 2,
 242         .tRTP           = 2,
 243         .tCKE           = 3,
 244         .tCKESR         = 3,
 245         .tFAW           = 8
 246 };
 247
 248 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
 249                 &timings_elpida_200_mhz,
 250                 &timings_elpida_333_mhz,
 251                 &timings_elpida_400_mhz
 252 };
 253
 254 static const struct lpddr2_device_timings elpida_2G_S4_timings = {
 255         .ac_timings     = elpida_ac_timings,
 256         .min_tck        = &min_tck_elpida,
 257 };
 258
 259 void emif_get_device_timings_sdp(u32 emif_nr,
 260                 const struct lpddr2_device_timings **cs0_device_timings,
 261                 const struct lpddr2_device_timings **cs1_device_timings)
 262 {
 263         u32 omap_rev = omap_revision();
 264
 265         /* Identical devices on EMIF1 & EMIF2 */
 266         *cs0_device_timings = &elpida_2G_S4_timings;
 267
 268         if (omap_rev == OMAP4430_ES1_0)
 269                 *cs1_device_timings = NULL;
 270         else
 271                 *cs1_device_timings = &elpida_2G_S4_timings;
 272 }
 273
 274 void emif_get_device_timings(u32 emif_nr,
 275                 const struct lpddr2_device_timings **cs0_device_timings,
 276                 const struct lpddr2_device_timings **cs1_device_timings)
 277         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 278
 279 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 280
 281 const struct lpddr2_mr_regs mr_regs = {
 282         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
 283         .mr2    = 0x4,
 284         .mr3    = -1,
 285         .mr10   = MR10_ZQ_ZQINIT,
 286         .mr16   = MR16_REF_FULL_ARRAY
 287 };
 288
 289 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 290 {
 291         *regs = &mr_regs;
 292 }