arch/arm/cpu/armv7/omap4/sdram_elpida.c

   1 /*
   2  * Timing and Organization details of the Elpida parts used in OMAP4
   3  * SDPs and Panda
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <asm/emif.h>
  14 #include <asm/arch/sys_proto.h>
  15
  16 /*
  17  * This file provides details of the LPDDR2 SDRAM parts used on OMAP4430
  18  * SDP and Panda. Since the parts used and geometry are identical for
  19  * SDP and Panda for a given OMAP4 revision, this information is kept
  20  * here instead of being in board directory. However the key functions
  21  * exported are weakly linked so that they can be over-ridden in the board
  22  * directory if there is a OMAP4 board in the future that uses a different
  23  * memory device or geometry.
  24  *
  25  * For any new board with different memory devices over-ride one or more
  26  * of the following functions as per the CONFIG flags you intend to enable:
  27  * - emif_get_reg_dump()
  28  * - emif_get_dmm_regs()
  29  * - emif_get_device_details()
  30  * - emif_get_device_timings()
  31  */
  32
  33 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  34
  35 static const struct emif_regs emif_regs_elpida_200_mhz_2cs = {
  36         .sdram_config_init              = 0x80000eb9,
  37         .sdram_config                   = 0x80001ab9,
  38         .ref_ctrl                       = 0x0000030c,
  39         .sdram_tim1                     = 0x08648311,
  40         .sdram_tim2                     = 0x101b06ca,
  41         .sdram_tim3                     = 0x0048a19f,
  42         .read_idle_ctrl                 = 0x000501ff,
  43         .zq_config                      = 0x500b3214,
  44         .temp_alert_config              = 0xd8016893,
  45         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  46         .emif_ddr_phy_ctlr_1            = 0x049ff808
  47 };
  48
  49 static const struct emif_regs emif_regs_elpida_380_mhz_1cs = {
  50         .sdram_config_init              = 0x80000eb1,
  51         .sdram_config                   = 0x80001ab1,
  52         .ref_ctrl                       = 0x000005cd,
  53         .sdram_tim1                     = 0x10cb0622,
  54         .sdram_tim2                     = 0x20350d52,
  55         .sdram_tim3                     = 0x00b1431f,
  56         .read_idle_ctrl                 = 0x000501ff,
  57         .zq_config                      = 0x500b3214,
  58         .temp_alert_config              = 0x58016893,
  59         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  60         .emif_ddr_phy_ctlr_1            = 0x049ff418
  61 };
  62
  63 const struct emif_regs emif_regs_elpida_400_mhz_1cs = {
  64         .sdram_config_init              = 0x80800eb2,
  65         .sdram_config                   = 0x80801ab2,
  66         .ref_ctrl                       = 0x00000618,
  67         .sdram_tim1                     = 0x10eb0662,
  68         .sdram_tim2                     = 0x20370dd2,
  69         .sdram_tim3                     = 0x00b1c33f,
  70         .read_idle_ctrl                 = 0x000501ff,
  71         .zq_config                      = 0x500b3215,
  72         .temp_alert_config              = 0x58016893,
  73         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  74         .emif_ddr_phy_ctlr_1            = 0x049ff418
  75 };
  76
  77 const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
  78         .sdram_config_init              = 0x80000eb9,
  79         .sdram_config                   = 0x80001ab9,
  80         .ref_ctrl                       = 0x00000618,
  81         .sdram_tim1                     = 0x10eb0662,
  82         .sdram_tim2                     = 0x20370dd2,
  83         .sdram_tim3                     = 0x00b1c33f,
  84         .read_idle_ctrl                 = 0x000501ff,
  85         .zq_config                      = 0xd00b3214,
  86         .temp_alert_config              = 0xd8016893,
  87         .emif_ddr_phy_ctlr_1_init       = 0x049ffff5,
  88         .emif_ddr_phy_ctlr_1            = 0x049ff418
  89 };
  90
  91 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
  92         .dmm_lisa_map_0 = 0xFF020100,
  93         .dmm_lisa_map_1 = 0,
  94         .dmm_lisa_map_2 = 0,
  95         .dmm_lisa_map_3 = 0x80540300,
  96         .is_ma_present  = 0x0
  97 };
  98
  99 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 100         .dmm_lisa_map_0 = 0xFF020100,
 101         .dmm_lisa_map_1 = 0,
 102         .dmm_lisa_map_2 = 0,
 103         .dmm_lisa_map_3 = 0x80640300,
 104         .is_ma_present  = 0x0
 105 };
 106
 107 const struct dmm_lisa_map_regs ma_lisa_map_2G_x_2_x_2 = {
 108         .dmm_lisa_map_0 = 0xFF020100,
 109         .dmm_lisa_map_1 = 0,
 110         .dmm_lisa_map_2 = 0,
 111         .dmm_lisa_map_3 = 0x80640300,
 112         .is_ma_present  = 0x1
 113 };
 114
 115 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 116 {
 117         u32 omap4_rev = omap_revision();
 118
 119         /* Same devices and geometry on both EMIFs */
 120         if (omap4_rev == OMAP4430_ES1_0)
 121                 *regs = &emif_regs_elpida_380_mhz_1cs;
 122         else if (omap4_rev == OMAP4430_ES2_0)
 123                 *regs = &emif_regs_elpida_200_mhz_2cs;
 124         else if (omap4_rev == OMAP4430_ES2_3)
 125                 *regs = &emif_regs_elpida_400_mhz_1cs;
 126         else if (omap4_rev < OMAP4470_ES1_0)
 127                 *regs = &emif_regs_elpida_400_mhz_2cs;
 128         else
 129                 *regs = &emif_regs_elpida_400_mhz_1cs;
 130 }
 131 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 132         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 133
 134 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 135                                                 **dmm_lisa_regs)
 136 {
 137         u32 omap_rev = omap_revision();
 138
 139         if (omap_rev == OMAP4430_ES1_0)
 140                 *dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
 141         else if (omap_rev == OMAP4430_ES2_3)
 142                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 143         else if (omap_rev < OMAP4460_ES1_0)
 144                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
 145         else
 146                 *dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
 147 }
 148
 149 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 150         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 151
 152 #else
 153
 154 static const struct lpddr2_device_details elpida_2G_S4_details = {
 155         .type           = LPDDR2_TYPE_S4,
 156         .density        = LPDDR2_DENSITY_2Gb,
 157         .io_width       = LPDDR2_IO_WIDTH_32,
 158         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 159 };
 160
 161 static const struct lpddr2_device_details elpida_4G_S4_details = {
 162         .type           = LPDDR2_TYPE_S4,
 163         .density        = LPDDR2_DENSITY_4Gb,
 164         .io_width       = LPDDR2_IO_WIDTH_32,
 165         .manufacturer   = LPDDR2_MANUFACTURER_ELPIDA
 166 };
 167
 168 struct lpddr2_device_details *emif_get_device_details_sdp(u32 emif_nr, u8 cs,
 169                         struct lpddr2_device_details *lpddr2_dev_details)
 170 {
 171         u32 omap_rev = omap_revision();
 172
 173         /* EMIF1 & EMIF2 have identical configuration */
 174         if (((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
 175                 && (cs == CS1)) {
 176                 /* Nothing connected on CS1 for 4430/4470 ES1.0 */
 177                 return NULL;
 178         } else if (omap_rev < OMAP4470_ES1_0) {
 179                 /* In all other 4430/4460 cases Elpida 2G device */
 180                 *lpddr2_dev_details = elpida_2G_S4_details;
 181         } else {
 182                 /* 4470: 4G device */
 183                 *lpddr2_dev_details = elpida_4G_S4_details;
 184         }
 185         return lpddr2_dev_details;
 186 }
 187
 188 struct lpddr2_device_details *emif_get_device_details(u32 emif_nr, u8 cs,
 189                         struct lpddr2_device_details *lpddr2_dev_details)
 190         __attribute__((weak, alias("emif_get_device_details_sdp")));
 191
 192 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 193
 194 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 195 static const struct lpddr2_ac_timings timings_elpida_400_mhz = {
 196         .max_freq       = 400000000,
 197         .RL             = 6,
 198         .tRPab          = 21,
 199         .tRCD           = 18,
 200         .tWR            = 15,
 201         .tRASmin        = 42,
 202         .tRRD           = 10,
 203         .tWTRx2         = 15,
 204         .tXSR           = 140,
 205         .tXPx2          = 15,
 206         .tRFCab         = 130,
 207         .tRTPx2         = 15,
 208         .tCKE           = 3,
 209         .tCKESR         = 15,
 210         .tZQCS          = 90,
 211         .tZQCL          = 360,
 212         .tZQINIT        = 1000,
 213         .tDQSCKMAXx2    = 11,
 214         .tRASmax        = 70,
 215         .tFAW           = 50
 216 };
 217
 218 static const struct lpddr2_ac_timings timings_elpida_333_mhz = {
 219         .max_freq       = 333000000,
 220         .RL             = 5,
 221         .tRPab          = 21,
 222         .tRCD           = 18,
 223         .tWR            = 15,
 224         .tRASmin        = 42,
 225         .tRRD           = 10,
 226         .tWTRx2         = 15,
 227         .tXSR           = 140,
 228         .tXPx2          = 15,
 229         .tRFCab         = 130,
 230         .tRTPx2         = 15,
 231         .tCKE           = 3,
 232         .tCKESR         = 15,
 233         .tZQCS          = 90,
 234         .tZQCL          = 360,
 235         .tZQINIT        = 1000,
 236         .tDQSCKMAXx2    = 11,
 237         .tRASmax        = 70,
 238         .tFAW           = 50
 239 };
 240
 241 static const struct lpddr2_ac_timings timings_elpida_200_mhz = {
 242         .max_freq       = 200000000,
 243         .RL             = 3,
 244         .tRPab          = 21,
 245         .tRCD           = 18,
 246         .tWR            = 15,
 247         .tRASmin        = 42,
 248         .tRRD           = 10,
 249         .tWTRx2         = 20,
 250         .tXSR           = 140,
 251         .tXPx2          = 15,
 252         .tRFCab         = 130,
 253         .tRTPx2         = 15,
 254         .tCKE           = 3,
 255         .tCKESR         = 15,
 256         .tZQCS          = 90,
 257         .tZQCL          = 360,
 258         .tZQINIT        = 1000,
 259         .tDQSCKMAXx2    = 11,
 260         .tRASmax        = 70,
 261         .tFAW           = 50
 262 };
 263
 264 static const struct lpddr2_min_tck min_tck_elpida = {
 265         .tRL            = 3,
 266         .tRP_AB         = 3,
 267         .tRCD           = 3,
 268         .tWR            = 3,
 269         .tRAS_MIN       = 3,
 270         .tRRD           = 2,
 271         .tWTR           = 2,
 272         .tXP            = 2,
 273         .tRTP           = 2,
 274         .tCKE           = 3,
 275         .tCKESR         = 3,
 276         .tFAW           = 8
 277 };
 278
 279 static const struct lpddr2_ac_timings *elpida_ac_timings[MAX_NUM_SPEEDBINS] = {
 280                 &timings_elpida_200_mhz,
 281                 &timings_elpida_333_mhz,
 282                 &timings_elpida_400_mhz
 283 };
 284
 285 static const struct lpddr2_device_timings elpida_2G_S4_timings = {
 286         .ac_timings     = elpida_ac_timings,
 287         .min_tck        = &min_tck_elpida,
 288 };
 289
 290 void emif_get_device_timings_sdp(u32 emif_nr,
 291                 const struct lpddr2_device_timings **cs0_device_timings,
 292                 const struct lpddr2_device_timings **cs1_device_timings)
 293 {
 294         u32 omap_rev = omap_revision();
 295
 296         /* Identical devices on EMIF1 & EMIF2 */
 297         *cs0_device_timings = &elpida_2G_S4_timings;
 298
 299         if ((omap_rev == OMAP4430_ES1_0) || (omap_rev == OMAP4470_ES1_0))
 300                 *cs1_device_timings = NULL;
 301         else
 302                 *cs1_device_timings = &elpida_2G_S4_timings;
 303 }
 304
 305 void emif_get_device_timings(u32 emif_nr,
 306                 const struct lpddr2_device_timings **cs0_device_timings,
 307                 const struct lpddr2_device_timings **cs1_device_timings)
 308         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 309
 310 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */
 311
 312 const struct lpddr2_mr_regs mr_regs = {
 313         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_3,
 314         .mr2    = 0x4,
 315         .mr3    = -1,
 316         .mr10   = MR10_ZQ_ZQINIT,
 317         .mr16   = MR16_REF_FULL_ARRAY
 318 };
 319
 320 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 321 {
 322         *regs = &mr_regs;
 323 }