arch/arm/cpu/armv7/omap5/sdram.c

   1 /*
   2  * Timing and Organization details of the ddr device parts used in OMAP5
   3  * EVM
   4  *
   5  * (C) Copyright 2010
   6  * Texas Instruments, <www.ti.com>
   7  *
   8  * Aneesh V <aneesh@ti.com>
   9  * Sricharan R <r.sricharan@ti.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #include <asm/emif.h>
  15 #include <asm/arch/sys_proto.h>
  16
  17 /*
  18  * This file provides details of the LPDDR2 SDRAM parts used on OMAP5
  19  * EVM. Since the parts used and geometry are identical for
  20  * evm for a given OMAP5 revision, this information is kept
  21  * here instead of being in board directory. However the key functions
  22  * exported are weakly linked so that they can be over-ridden in the board
  23  * directory if there is a OMAP5 board in the future that uses a different
  24  * memory device or geometry.
  25  *
  26  * For any new board with different memory devices over-ride one or more
  27  * of the following functions as per the CONFIG flags you intend to enable:
  28  * - emif_get_reg_dump()
  29  * - emif_get_dmm_regs()
  30  * - emif_get_device_details()
  31  * - emif_get_device_timings()
  32  */
  33
  34 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
  35 const struct emif_regs emif_regs_532_mhz_2cs = {
  36         .sdram_config_init              = 0x80800EBA,
  37         .sdram_config                   = 0x808022BA,
  38         .ref_ctrl                       = 0x0000081A,
  39         .sdram_tim1                     = 0x772F6873,
  40         .sdram_tim2                     = 0x304a129a,
  41         .sdram_tim3                     = 0x02f7e45f,
  42         .read_idle_ctrl                 = 0x00050000,
  43         .zq_config                      = 0x000b3215,
  44         .temp_alert_config              = 0x08000a05,
  45         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  46         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  47         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  48         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  49         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  50         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  51         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  52 };
  53
  54 const struct emif_regs emif_regs_532_mhz_2cs_es2 = {
  55         .sdram_config_init              = 0x80800EBA,
  56         .sdram_config                   = 0x808022BA,
  57         .ref_ctrl                       = 0x0000081A,
  58         .sdram_tim1                     = 0x772F6873,
  59         .sdram_tim2                     = 0x304a129a,
  60         .sdram_tim3                     = 0x02f7e45f,
  61         .read_idle_ctrl                 = 0x00050000,
  62         .zq_config                      = 0x100b3215,
  63         .temp_alert_config              = 0x08000a05,
  64         .emif_ddr_phy_ctlr_1_init       = 0x0E30400d,
  65         .emif_ddr_phy_ctlr_1            = 0x0E30400d,
  66         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  67         .emif_ddr_ext_phy_ctrl_2        = 0x28C518A3,
  68         .emif_ddr_ext_phy_ctrl_3        = 0x518A3146,
  69         .emif_ddr_ext_phy_ctrl_4        = 0x0014628C,
  70         .emif_ddr_ext_phy_ctrl_5        = 0xC330CC33,
  71 };
  72
  73 const struct emif_regs emif_regs_266_mhz_2cs = {
  74         .sdram_config_init              = 0x80800EBA,
  75         .sdram_config                   = 0x808022BA,
  76         .ref_ctrl                       = 0x0000040D,
  77         .sdram_tim1                     = 0x2A86B419,
  78         .sdram_tim2                     = 0x1025094A,
  79         .sdram_tim3                     = 0x026BA22F,
  80         .read_idle_ctrl                 = 0x00050000,
  81         .zq_config                      = 0x000b3215,
  82         .temp_alert_config              = 0x08000a05,
  83         .emif_ddr_phy_ctlr_1_init       = 0x0E28420d,
  84         .emif_ddr_phy_ctlr_1            = 0x0E28420d,
  85         .emif_ddr_ext_phy_ctrl_1        = 0x04020080,
  86         .emif_ddr_ext_phy_ctrl_2        = 0x0A414829,
  87         .emif_ddr_ext_phy_ctrl_3        = 0x14829052,
  88         .emif_ddr_ext_phy_ctrl_4        = 0x000520A4,
  89         .emif_ddr_ext_phy_ctrl_5        = 0x04010040
  90 };
  91
  92 const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
  93         .sdram_config_init              = 0x61851B32,
  94         .sdram_config                   = 0x61851B32,
  95         .sdram_config2                  = 0x0,
  96         .ref_ctrl                       = 0x00001035,
  97         .sdram_tim1                     = 0xCCCF36B3,
  98         .sdram_tim2                     = 0x308F7FDA,
  99         .sdram_tim3                     = 0x027F88A8,
 100         .read_idle_ctrl                 = 0x00050000,
 101         .zq_config                      = 0x0007190B,
 102         .temp_alert_config              = 0x00000000,
 103         .emif_ddr_phy_ctlr_1_init       = 0x0020420A,
 104         .emif_ddr_phy_ctlr_1            = 0x0024420A,
 105         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 106         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 107         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 108         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 109         .emif_ddr_ext_phy_ctrl_5        = 0x04010040,
 110         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 111         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 112         .emif_rd_wr_lvl_ctl             = 0x00000000,
 113         .emif_rd_wr_exec_thresh         = 0x00000305
 114 };
 115
 116 const struct emif_regs emif_regs_ddr3_532_mhz_1cs_es2 = {
 117         .sdram_config_init              = 0x61851B32,
 118         .sdram_config                   = 0x61851B32,
 119         .sdram_config2                  = 0x0,
 120         .ref_ctrl                       = 0x00001035,
 121         .sdram_tim1                     = 0xCCCF36B3,
 122         .sdram_tim2                     = 0x308F7FDA,
 123         .sdram_tim3                     = 0x027F88A8,
 124         .read_idle_ctrl                 = 0x00050000,
 125         .zq_config                      = 0x1007190B,
 126         .temp_alert_config              = 0x00000000,
 127         .emif_ddr_phy_ctlr_1_init       = 0x0030400A,
 128         .emif_ddr_phy_ctlr_1            = 0x0034400A,
 129         .emif_ddr_ext_phy_ctrl_1        = 0x04040100,
 130         .emif_ddr_ext_phy_ctrl_2        = 0x00000000,
 131         .emif_ddr_ext_phy_ctrl_3        = 0x00000000,
 132         .emif_ddr_ext_phy_ctrl_4        = 0x00000000,
 133         .emif_ddr_ext_phy_ctrl_5        = 0x4350D435,
 134         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 135         .emif_rd_wr_lvl_rmp_ctl         = 0x80000000,
 136         .emif_rd_wr_lvl_ctl             = 0x00000000,
 137         .emif_rd_wr_exec_thresh         = 0x40000305
 138 };
 139
 140 const struct emif_regs emif_1_regs_ddr3_532_mhz_1cs_dra_es1 = {
 141         .sdram_config_init              = 0x61851ab2,
 142         .sdram_config                   = 0x61851ab2,
 143         .sdram_config2                  = 0x08000000,
 144         .ref_ctrl                       = 0x00001035,
 145         .sdram_tim1                     = 0xCCCF36B3,
 146         .sdram_tim2                     = 0x308F7FDA,
 147         .sdram_tim3                     = 0x027F88A8,
 148         .read_idle_ctrl                 = 0x00050001,
 149         .zq_config                      = 0x0007190B,
 150         .temp_alert_config              = 0x00000000,
 151         .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
 152         .emif_ddr_phy_ctlr_1            = 0x0E24400A,
 153         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 154         .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
 155         .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
 156         .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
 157         .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
 158         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 159         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 160         .emif_rd_wr_lvl_ctl             = 0x00000000,
 161         .emif_rd_wr_exec_thresh         = 0x00000305
 162 };
 163
 164 const struct emif_regs emif_2_regs_ddr3_532_mhz_1cs_dra_es1 = {
 165         .sdram_config_init              = 0x61851B32,
 166         .sdram_config                   = 0x61851B32,
 167         .sdram_config2                  = 0x08000000,
 168         .ref_ctrl                       = 0x00001035,
 169         .sdram_tim1                     = 0xCCCF36B3,
 170         .sdram_tim2                     = 0x308F7FDA,
 171         .sdram_tim3                     = 0x027F88A8,
 172         .read_idle_ctrl                 = 0x00050001,
 173         .zq_config                      = 0x0007190B,
 174         .temp_alert_config              = 0x00000000,
 175         .emif_ddr_phy_ctlr_1_init       = 0x0E24400A,
 176         .emif_ddr_phy_ctlr_1            = 0x0E24400A,
 177         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 178         .emif_ddr_ext_phy_ctrl_2        = 0x00BB00BB,
 179         .emif_ddr_ext_phy_ctrl_3        = 0x00BB00BB,
 180         .emif_ddr_ext_phy_ctrl_4        = 0x00BB00BB,
 181         .emif_ddr_ext_phy_ctrl_5        = 0x00BB00BB,
 182         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 183         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 184         .emif_rd_wr_lvl_ctl             = 0x00000000,
 185         .emif_rd_wr_exec_thresh         = 0x00000305
 186 };
 187
 188 const struct emif_regs emif_1_regs_ddr3_666_mhz_1cs_dra_es1 = {
 189         .sdram_config_init              = 0x61851AB2,
 190         .sdram_config                   = 0x61851AB2,
 191         .sdram_config2                  = 0x08000000,
 192         .ref_ctrl                       = 0x00001035,
 193         .sdram_tim1                     = 0xCCCF36B3,
 194         .sdram_tim2                     = 0x308F7FDA,
 195         .sdram_tim3                     = 0x027F88A8,
 196         .read_idle_ctrl                 = 0x00050000,
 197         .zq_config                      = 0x0007190B,
 198         .temp_alert_config              = 0x00000000,
 199         .emif_ddr_phy_ctlr_1_init       = 0x0024400A,
 200         .emif_ddr_phy_ctlr_1            = 0x0024400A,
 201         .emif_ddr_ext_phy_ctrl_1        = 0x10040100,
 202         .emif_ddr_ext_phy_ctrl_2        = 0x00A400A4,
 203         .emif_ddr_ext_phy_ctrl_3        = 0x00A900A9,
 204         .emif_ddr_ext_phy_ctrl_4        = 0x00B000B0,
 205         .emif_ddr_ext_phy_ctrl_5        = 0x00B000B0,
 206         .emif_rd_wr_lvl_rmp_win         = 0x00000000,
 207         .emif_rd_wr_lvl_rmp_ctl         = 0x00000000,
 208         .emif_rd_wr_lvl_ctl             = 0x00000000,
 209         .emif_rd_wr_exec_thresh         = 0x00000305
 210 };
 211
 212 const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = {
 213         .dmm_lisa_map_0 = 0x0,
 214         .dmm_lisa_map_1 = 0x0,
 215         .dmm_lisa_map_2 = 0x80740300,
 216         .dmm_lisa_map_3 = 0xFF020100,
 217         .is_ma_present  = 0x1
 218 };
 219
 220 /*
 221  * DRA752 EVM board has 1.5 GB of memory
 222  * EMIF1 --> 2Gb * 2 =  512MB
 223  * EMIF2 --> 2Gb * 4 =  1GB
 224  * so mapping 1GB interleaved and 512MB non-interleaved
 225  */
 226 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2_2G_x_1_x_2 = {
 227         .dmm_lisa_map_0 = 0x0,
 228         .dmm_lisa_map_1 = 0x80640300,
 229         .dmm_lisa_map_2 = 0xC0500220,
 230         .dmm_lisa_map_3 = 0xFF020100,
 231         .is_ma_present  = 0x1
 232 };
 233
 234 /*
 235  * DRA752 EVM EMIF1 ONLY CONFIGURATION
 236  */
 237 const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = {
 238         .dmm_lisa_map_0 = 0x0,
 239         .dmm_lisa_map_1 = 0x0,
 240         .dmm_lisa_map_2 = 0x80500100,
 241         .dmm_lisa_map_3 = 0xFF020100,
 242         .is_ma_present  = 0x1
 243 };
 244
 245 /*
 246  * DRA752 EVM EMIF2 ONLY CONFIGURATION
 247  */
 248 const struct dmm_lisa_map_regs lisa_map_2G_x_2_x_2 = {
 249         .dmm_lisa_map_0 = 0x0,
 250         .dmm_lisa_map_1 = 0x0,
 251         .dmm_lisa_map_2 = 0x80600200,
 252         .dmm_lisa_map_3 = 0xFF020100,
 253         .is_ma_present  = 0x1
 254 };
 255
 256 /*
 257  * DRA722 EVM EMIF1 CONFIGURATION
 258  */
 259 const struct dmm_lisa_map_regs lisa_map_2G_x_2 = {
 260         .dmm_lisa_map_0 = 0x0,
 261         .dmm_lisa_map_1 = 0x0,
 262         .dmm_lisa_map_2 = 0x80600100,
 263         .dmm_lisa_map_3 = 0xFF020100,
 264         .is_ma_present  = 0x1
 265 };
 266
 267 static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs)
 268 {
 269         switch (omap_revision()) {
 270         case OMAP5430_ES1_0:
 271                 *regs = &emif_regs_532_mhz_2cs;
 272                 break;
 273         case OMAP5432_ES1_0:
 274                 *regs = &emif_regs_ddr3_532_mhz_1cs;
 275                 break;
 276         case OMAP5430_ES2_0:
 277                 *regs = &emif_regs_532_mhz_2cs_es2;
 278                 break;
 279         case OMAP5432_ES2_0:
 280                 *regs = &emif_regs_ddr3_532_mhz_1cs_es2;
 281                 break;
 282         case DRA752_ES1_0:
 283         case DRA752_ES1_1:
 284                 switch (emif_nr) {
 285                 case 1:
 286                         *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 287                         break;
 288                 case 2:
 289                         *regs = &emif_2_regs_ddr3_532_mhz_1cs_dra_es1;
 290                         break;
 291                 }
 292                 break;
 293         case DRA722_ES1_0:
 294                 *regs = &emif_1_regs_ddr3_666_mhz_1cs_dra_es1;
 295                 break;
 296         default:
 297                 *regs = &emif_1_regs_ddr3_532_mhz_1cs_dra_es1;
 298         }
 299 }
 300
 301 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
 302         __attribute__((weak, alias("emif_get_reg_dump_sdp")));
 303
 304 static void emif_get_dmm_regs_sdp(const struct dmm_lisa_map_regs
 305                                                 **dmm_lisa_regs)
 306 {
 307         switch (omap_revision()) {
 308         case OMAP5430_ES1_0:
 309         case OMAP5430_ES2_0:
 310         case OMAP5432_ES1_0:
 311         case OMAP5432_ES2_0:
 312                 *dmm_lisa_regs = &lisa_map_4G_x_2_x_2;
 313                 break;
 314         case DRA752_ES1_0:
 315         case DRA752_ES1_1:
 316                 *dmm_lisa_regs = &lisa_map_2G_x_2_x_2_2G_x_1_x_2;
 317                 break;
 318         case DRA722_ES1_0:
 319         default:
 320                 *dmm_lisa_regs = &lisa_map_2G_x_2;
 321         }
 322
 323 }
 324
 325 void emif_get_dmm_regs(const struct dmm_lisa_map_regs **dmm_lisa_regs)
 326         __attribute__((weak, alias("emif_get_dmm_regs_sdp")));
 327 #else
 328
 329 static const struct lpddr2_device_details dev_4G_S4_details = {
 330         .type           = LPDDR2_TYPE_S4,
 331         .density        = LPDDR2_DENSITY_4Gb,
 332         .io_width       = LPDDR2_IO_WIDTH_32,
 333         .manufacturer   = LPDDR2_MANUFACTURER_SAMSUNG
 334 };
 335
 336 static void emif_get_device_details_sdp(u32 emif_nr,
 337                 struct lpddr2_device_details *cs0_device_details,
 338                 struct lpddr2_device_details *cs1_device_details)
 339 {
 340         /* EMIF1 & EMIF2 have identical configuration */
 341         *cs0_device_details = dev_4G_S4_details;
 342         *cs1_device_details = dev_4G_S4_details;
 343 }
 344
 345 void emif_get_device_details(u32 emif_nr,
 346                 struct lpddr2_device_details *cs0_device_details,
 347                 struct lpddr2_device_details *cs1_device_details)
 348         __attribute__((weak, alias("emif_get_device_details_sdp")));
 349
 350 #endif /* CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS */
 351
 352 const u32 ext_phy_ctrl_const_base[] = {
 353         0x01004010,
 354         0x00001004,
 355         0x04010040,
 356         0x01004010,
 357         0x00001004,
 358         0x00000000,
 359         0x00000000,
 360         0x00000000,
 361         0x80080080,
 362         0x00800800,
 363         0x08102040,
 364         0x00000001,
 365         0x540A8150,
 366         0xA81502a0,
 367         0x002A0540,
 368         0x00000000,
 369         0x00000000,
 370         0x00000000,
 371         0x00000077,
 372         0x0
 373 };
 374
 375 const u32 ddr3_ext_phy_ctrl_const_base_es1[] = {
 376         0x01004010,
 377         0x00001004,
 378         0x04010040,
 379         0x01004010,
 380         0x00001004,
 381         0x00000000,
 382         0x00000000,
 383         0x00000000,
 384         0x80080080,
 385         0x00800800,
 386         0x08102040,
 387         0x00000002,
 388         0x0,
 389         0x0,
 390         0x0,
 391         0x00000000,
 392         0x00000000,
 393         0x00000000,
 394         0x00000057,
 395         0x0
 396 };
 397
 398 const u32 ddr3_ext_phy_ctrl_const_base_es2[] = {
 399         0x50D4350D,
 400         0x00000D43,
 401         0x04010040,
 402         0x01004010,
 403         0x00001004,
 404         0x00000000,
 405         0x00000000,
 406         0x00000000,
 407         0x80080080,
 408         0x00800800,
 409         0x08102040,
 410         0x00000002,
 411         0x00000000,
 412         0x00000000,
 413         0x00000000,
 414         0x00000000,
 415         0x00000000,
 416         0x00000000,
 417         0x00000057,
 418         0x0
 419 };
 420
 421 const u32
 422 dra_ddr3_ext_phy_ctrl_const_base_es1_emif1[] = {
 423         0x00BB00BB,
 424         0x00440044,
 425         0x00440044,
 426         0x00440044,
 427         0x00440044,
 428         0x00440044,
 429         0x007F007F,
 430         0x007F007F,
 431         0x007F007F,
 432         0x007F007F,
 433         0x007F007F,
 434         0x00600060,
 435         0x00600060,
 436         0x00600060,
 437         0x00600060,
 438         0x00600060,
 439         0x00000000,
 440         0x00600020,
 441         0x40010080,
 442         0x08102040,
 443         0x0,
 444         0x0,
 445         0x0,
 446         0x0,
 447         0x0
 448 };
 449
 450 const u32
 451 dra_ddr3_ext_phy_ctrl_const_base_es1_emif2[] = {
 452         0x00BB00BB,
 453         0x00440044,
 454         0x00440044,
 455         0x00440044,
 456         0x00440044,
 457         0x00440044,
 458         0x007F007F,
 459         0x007F007F,
 460         0x007F007F,
 461         0x007F007F,
 462         0x007F007F,
 463         0x00600060,
 464         0x00600060,
 465         0x00600060,
 466         0x00600060,
 467         0x00600060,
 468         0x00000000,
 469         0x00600020,
 470         0x40010080,
 471         0x08102040,
 472         0x0,
 473         0x0,
 474         0x0,
 475         0x0,
 476         0x0
 477 };
 478
 479 const u32
 480 dra_ddr3_ext_phy_ctrl_const_base_666MHz[] = {
 481         0x00A400A4,
 482         0x00390039,
 483         0x00320032,
 484         0x00320032,
 485         0x00320032,
 486         0x00440044,
 487         0x00550055,
 488         0x00550055,
 489         0x00550055,
 490         0x00550055,
 491         0x007F007F,
 492         0x004D004D,
 493         0x00430043,
 494         0x00560056,
 495         0x00540054,
 496         0x00600060,
 497         0x0,
 498         0x00600020,
 499         0x40010080,
 500         0x08102040,
 501         0x0,
 502         0x0,
 503         0x0,
 504         0x0,
 505         0x0
 506 };
 507
 508 const struct lpddr2_mr_regs mr_regs = {
 509         .mr1    = MR1_BL_8_BT_SEQ_WRAP_EN_NWR_8,
 510         .mr2    = 0x6,
 511         .mr3    = 0x1,
 512         .mr10   = MR10_ZQ_ZQINIT,
 513         .mr16   = MR16_REF_FULL_ARRAY
 514 };
 515
 516 void __weak emif_get_ext_phy_ctrl_const_regs(u32 emif_nr,
 517                                              const u32 **regs,
 518                                              u32 *size)
 519 {
 520         switch (omap_revision()) {
 521         case OMAP5430_ES1_0:
 522         case OMAP5430_ES2_0:
 523                 *regs = ext_phy_ctrl_const_base;
 524                 *size = ARRAY_SIZE(ext_phy_ctrl_const_base);
 525                 break;
 526         case OMAP5432_ES1_0:
 527                 *regs = ddr3_ext_phy_ctrl_const_base_es1;
 528                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es1);
 529                 break;
 530         case OMAP5432_ES2_0:
 531                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 532                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 533                 break;
 534         case DRA752_ES1_0:
 535         case DRA752_ES1_1:
 536                 if (emif_nr == 1) {
 537                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif1;
 538                         *size =
 539                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif1);
 540                 } else {
 541                         *regs = dra_ddr3_ext_phy_ctrl_const_base_es1_emif2;
 542                         *size =
 543                         ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_es1_emif2);
 544                 }
 545                 break;
 546         case DRA722_ES1_0:
 547                 *regs = dra_ddr3_ext_phy_ctrl_const_base_666MHz;
 548                 *size = ARRAY_SIZE(dra_ddr3_ext_phy_ctrl_const_base_666MHz);
 549                 break;
 550         default:
 551                 *regs = ddr3_ext_phy_ctrl_const_base_es2;
 552                 *size = ARRAY_SIZE(ddr3_ext_phy_ctrl_const_base_es2);
 553
 554         }
 555 }
 556
 557 void get_lpddr2_mr_regs(const struct lpddr2_mr_regs **regs)
 558 {
 559         *regs = &mr_regs;
 560 }
 561
 562 void do_ext_phy_settings(u32 base, const struct emif_regs *regs)
 563 {
 564         u32 *ext_phy_ctrl_base = 0;
 565         u32 *emif_ext_phy_ctrl_base = 0;
 566         u32 emif_nr;
 567         const u32 *ext_phy_ctrl_const_regs;
 568         u32 i = 0;
 569         u32 size;
 570
 571         emif_nr = (base == EMIF1_BASE) ? 1 : 2;
 572
 573         struct emif_reg_struct *emif = (struct emif_reg_struct *)base;
 574
 575         ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1);
 576         emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1);
 577
 578         /* Configure external phy control timing registers */
 579         for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) {
 580                 writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++);
 581                 /* Update shadow registers */
 582                 writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++);
 583         }
 584
 585         /*
 586          * external phy 6-24 registers do not change with
 587          * ddr frequency
 588          */
 589         emif_get_ext_phy_ctrl_const_regs(emif_nr,
 590                                          &ext_phy_ctrl_const_regs, &size);
 591
 592         for (i = 0; i < size; i++) {
 593                 writel(ext_phy_ctrl_const_regs[i],
 594                        emif_ext_phy_ctrl_base++);
 595                 /* Update shadow registers */
 596                 writel(ext_phy_ctrl_const_regs[i],
 597                        emif_ext_phy_ctrl_base++);
 598         }
 599 }
 600
 601 #ifndef CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS
 602 static const struct lpddr2_ac_timings timings_jedec_532_mhz = {
 603         .max_freq       = 532000000,
 604         .RL             = 8,
 605         .tRPab          = 21,
 606         .tRCD           = 18,
 607         .tWR            = 15,
 608         .tRASmin        = 42,
 609         .tRRD           = 10,
 610         .tWTRx2         = 15,
 611         .tXSR           = 140,
 612         .tXPx2          = 15,
 613         .tRFCab         = 130,
 614         .tRTPx2         = 15,
 615         .tCKE           = 3,
 616         .tCKESR         = 15,
 617         .tZQCS          = 90,
 618         .tZQCL          = 360,
 619         .tZQINIT        = 1000,
 620         .tDQSCKMAXx2    = 11,
 621         .tRASmax        = 70,
 622         .tFAW           = 50
 623 };
 624
 625 static const struct lpddr2_min_tck min_tck = {
 626         .tRL            = 3,
 627         .tRP_AB         = 3,
 628         .tRCD           = 3,
 629         .tWR            = 3,
 630         .tRAS_MIN       = 3,
 631         .tRRD           = 2,
 632         .tWTR           = 2,
 633         .tXP            = 2,
 634         .tRTP           = 2,
 635         .tCKE           = 3,
 636         .tCKESR         = 3,
 637         .tFAW           = 8
 638 };
 639
 640 static const struct lpddr2_ac_timings *ac_timings[MAX_NUM_SPEEDBINS] = {
 641         &timings_jedec_532_mhz
 642 };
 643
 644 static const struct lpddr2_device_timings dev_4G_S4_timings = {
 645         .ac_timings     = ac_timings,
 646         .min_tck        = &min_tck,
 647 };
 648
 649 /*
 650  * List of status registers to be controlled back to control registers
 651  * after initial leveling
 652  * readreg, writereg
 653  */
 654 const struct read_write_regs omap5_bug_00339_regs[] = {
 655         { 8,  5 },
 656         { 9,  6 },
 657         { 10, 7 },
 658         { 14, 8 },
 659         { 15, 9 },
 660         { 16, 10 },
 661         { 11, 2 },
 662         { 12, 3 },
 663         { 13, 4 },
 664         { 17, 11 },
 665         { 18, 12 },
 666         { 19, 13 },
 667 };
 668
 669 const struct read_write_regs dra_bug_00339_regs[] = {
 670         { 7,  7 },
 671         { 8,  8 },
 672         { 9,  9 },
 673         { 10, 10 },
 674         { 11, 11 },
 675         { 12, 2 },
 676         { 13, 3 },
 677         { 14, 4 },
 678         { 15, 5 },
 679         { 16, 6 },
 680         { 17, 12 },
 681         { 18, 13 },
 682         { 19, 14 },
 683         { 20, 15 },
 684         { 21, 16 },
 685         { 22, 17 },
 686         { 23, 18 },
 687         { 24, 19 },
 688         { 25, 20 },
 689         { 26, 21}
 690 };
 691
 692 const struct read_write_regs *get_bug_regs(u32 *iterations)
 693 {
 694         const struct read_write_regs *bug_00339_regs_ptr = NULL;
 695
 696         switch (omap_revision()) {
 697         case OMAP5430_ES1_0:
 698         case OMAP5430_ES2_0:
 699         case OMAP5432_ES1_0:
 700         case OMAP5432_ES2_0:
 701                 bug_00339_regs_ptr = omap5_bug_00339_regs;
 702                 *iterations = sizeof(omap5_bug_00339_regs)/
 703                              sizeof(omap5_bug_00339_regs[0]);
 704                 break;
 705         case DRA752_ES1_0:
 706         case DRA752_ES1_1:
 707         case DRA722_ES1_0:
 708                 bug_00339_regs_ptr = dra_bug_00339_regs;
 709                 *iterations = sizeof(dra_bug_00339_regs)/
 710                              sizeof(dra_bug_00339_regs[0]);
 711                 break;
 712         default:
 713                 printf("\n Error: UnKnown SOC");
 714         }
 715
 716         return bug_00339_regs_ptr;
 717 }
 718
 719 void emif_get_device_timings_sdp(u32 emif_nr,
 720                 const struct lpddr2_device_timings **cs0_device_timings,
 721                 const struct lpddr2_device_timings **cs1_device_timings)
 722 {
 723         /* Identical devices on EMIF1 & EMIF2 */
 724         *cs0_device_timings = &dev_4G_S4_timings;
 725         *cs1_device_timings = &dev_4G_S4_timings;
 726 }
 727
 728 void emif_get_device_timings(u32 emif_nr,
 729                 const struct lpddr2_device_timings **cs0_device_timings,
 730                 const struct lpddr2_device_timings **cs1_device_timings)
 731         __attribute__((weak, alias("emif_get_device_timings_sdp")));
 732
 733 #endif /* CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS */