arch/arm/cpu/armv7/sunxi/clock_sun6i.c

   1 /*
   2  * sun6i specific clock code
   3  *
   4  * (C) Copyright 2007-2012
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * Tom Cubie <tangliang@allwinnertech.com>
   7  *
   8  * (C) Copyright 2013 Luke Kenneth Casson Leighton <lkcl@lkcl.net>
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #include <common.h>
  14 #include <asm/io.h>
  15 #include <asm/arch/clock.h>
  16 #include <asm/arch/prcm.h>
  17 #include <asm/arch/sys_proto.h>
  18
  19 #ifdef CONFIG_SPL_BUILD
  20 void clock_init_safe(void)
  21 {
  22         struct sunxi_ccm_reg * const ccm =
  23                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  24         struct sunxi_prcm_reg * const prcm =
  25                 (struct sunxi_prcm_reg *)SUNXI_PRCM_BASE;
  26
  27         /* Set PLL ldo voltage without this PLL6 does not work properly */
  28         clrsetbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK,
  29                         PRCM_PLL_CTRL_LDO_KEY);
  30         clrsetbits_le32(&prcm->pll_ctrl1, ~PRCM_PLL_CTRL_LDO_KEY_MASK,
  31                 PRCM_PLL_CTRL_LDO_DIGITAL_EN | PRCM_PLL_CTRL_LDO_ANALOG_EN |
  32                 PRCM_PLL_CTRL_EXT_OSC_EN | PRCM_PLL_CTRL_LDO_OUT_L(1140));
  33         clrbits_le32(&prcm->pll_ctrl1, PRCM_PLL_CTRL_LDO_KEY_MASK);
  34
  35         clock_set_pll1(408000000);
  36
  37         writel(AHB1_ABP1_DIV_DEFAULT, &ccm->ahb1_apb1_div);
  38
  39         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  40
  41         writel(MBUS_CLK_DEFAULT, &ccm->mbus0_clk_cfg);
  42         writel(MBUS_CLK_DEFAULT, &ccm->mbus1_clk_cfg);
  43 }
  44 #endif
  45
  46 void clock_init_uart(void)
  47 {
  48         struct sunxi_ccm_reg *const ccm =
  49                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  50
  51 #if CONFIG_CONS_INDEX < 5
  52         /* uart clock source is apb2 */
  53         writel(APB2_CLK_SRC_OSC24M|
  54                APB2_CLK_RATE_N_1|
  55                APB2_CLK_RATE_M(1),
  56                &ccm->apb2_div);
  57
  58         /* open the clock for uart */
  59         setbits_le32(&ccm->apb2_gate,
  60                      CLK_GATE_OPEN << (APB2_GATE_UART_SHIFT +
  61                                        CONFIG_CONS_INDEX - 1));
  62
  63         /* deassert uart reset */
  64         setbits_le32(&ccm->apb2_reset_cfg,
  65                      1 << (APB2_RESET_UART_SHIFT +
  66                            CONFIG_CONS_INDEX - 1));
  67 #else
  68         /* enable R_PIO and R_UART clocks, and de-assert resets */
  69         prcm_apb0_enable(PRCM_APB0_GATE_PIO | PRCM_APB0_GATE_UART);
  70 #endif
  71
  72         /* Dup with clock_init_safe(), drop once sun6i SPL support lands */
  73         writel(PLL6_CFG_DEFAULT, &ccm->pll6_cfg);
  74 }
  75
  76 int clock_twi_onoff(int port, int state)
  77 {
  78         struct sunxi_ccm_reg *const ccm =
  79                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  80
  81         if (port > 3)
  82                 return -1;
  83
  84         /* set the apb clock gate for twi */
  85         if (state)
  86                 setbits_le32(&ccm->apb2_gate,
  87                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
  88         else
  89                 clrbits_le32(&ccm->apb2_gate,
  90                              CLK_GATE_OPEN << (APB2_GATE_TWI_SHIFT+port));
  91
  92         return 0;
  93 }
  94
  95 #ifdef CONFIG_SPL_BUILD
  96 void clock_set_pll1(unsigned int clk)
  97 {
  98         struct sunxi_ccm_reg * const ccm =
  99                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 100         int k = 1;
 101         int m = 1;
 102
 103         if (clk > 1152000000) {
 104                 k = 2;
 105         } else if (clk > 768000000) {
 106                 k = 3;
 107                 m = 2;
 108         }
 109
 110         /* Switch to 24MHz clock while changing PLL1 */
 111         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 112                ATB_DIV_2 << ATB_DIV_SHIFT |
 113                CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT,
 114                &ccm->cpu_axi_cfg);
 115
 116         /* PLL1 rate = 24000000 * n * k / m */
 117         writel(CCM_PLL1_CTRL_EN | CCM_PLL1_CTRL_MAGIC |
 118                CCM_PLL1_CTRL_N(clk / (24000000 * k / m)) |
 119                CCM_PLL1_CTRL_K(k) | CCM_PLL1_CTRL_M(m), &ccm->pll1_cfg);
 120         sdelay(200);
 121
 122         /* Switch CPU to PLL1 */
 123         writel(AXI_DIV_3 << AXI_DIV_SHIFT |
 124                ATB_DIV_2 << ATB_DIV_SHIFT |
 125                CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT,
 126                &ccm->cpu_axi_cfg);
 127 }
 128 #endif
 129
 130 void clock_set_pll3(unsigned int clk)
 131 {
 132         struct sunxi_ccm_reg * const ccm =
 133                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 134         const int m = 8; /* 3 MHz steps just like sun4i, sun5i and sun7i */
 135
 136         if (clk == 0) {
 137                 clrbits_le32(&ccm->pll3_cfg, CCM_PLL3_CTRL_EN);
 138                 return;
 139         }
 140
 141         /* PLL3 rate = 24000000 * n / m */
 142         writel(CCM_PLL3_CTRL_EN | CCM_PLL3_CTRL_INTEGER_MODE |
 143                CCM_PLL3_CTRL_N(clk / (24000000 / m)) | CCM_PLL3_CTRL_M(m),
 144                &ccm->pll3_cfg);
 145 }
 146
 147 void clock_set_pll5(unsigned int clk)
 148 {
 149         struct sunxi_ccm_reg * const ccm =
 150                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 151         const int k = 2;
 152         const int m = 1;
 153
 154         /* PLL5 rate = 24000000 * n * k / m */
 155         writel(CCM_PLL5_CTRL_EN | CCM_PLL5_CTRL_UPD |
 156                CCM_PLL5_CTRL_N(clk / (24000000 * k / m)) |
 157                CCM_PLL5_CTRL_K(k) | CCM_PLL5_CTRL_M(m), &ccm->pll5_cfg);
 158
 159         udelay(5500);
 160 }
 161
 162 unsigned int clock_get_pll6(void)
 163 {
 164         struct sunxi_ccm_reg *const ccm =
 165                 (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
 166         uint32_t rval = readl(&ccm->pll6_cfg);
 167         int n = ((rval & CCM_PLL6_CTRL_N_MASK) >> CCM_PLL6_CTRL_N_SHIFT) + 1;
 168         int k = ((rval & CCM_PLL6_CTRL_K_MASK) >> CCM_PLL6_CTRL_K_SHIFT) + 1;
 169         return 24000000 * n * k / 2;
 170 }
 171
 172 void clock_set_de_mod_clock(u32 *clk_cfg, unsigned int hz)
 173 {
 174         int pll = clock_get_pll6() * 2;
 175         int div = 1;
 176
 177         while ((pll / div) > hz)
 178                 div++;
 179
 180         writel(CCM_DE_CTRL_GATE | CCM_DE_CTRL_PLL6_2X | CCM_DE_CTRL_M(div),
 181                clk_cfg);
 182 }