arch/arm/cpu/armv7/uniphier/ph1-ld4/ddrphy_init.c

   1 /*
   2  * Copyright (C) 2014 Panasonic Corporation
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <linux/types.h>
   8 #include <asm/io.h>
   9 #include <asm/arch/ddrphy-regs.h>
  10
  11 void ddrphy_init(struct ddrphy __iomem *phy, int freq, int size)
  12 {
  13         u32 tmp;
  14
  15         writel(0x0300c473, &phy->pgcr[1]);
  16         if (freq == 1333) {
  17                 writel(0x0a806844, &phy->ptr[0]);
  18                 writel(0x208e0124, &phy->ptr[1]);
  19         } else {
  20                 writel(0x0c807d04, &phy->ptr[0]);
  21                 writel(0x2710015E, &phy->ptr[1]);
  22         }
  23         writel(0x00083DEF, &phy->ptr[2]);
  24         if (freq == 1333) {
  25                 writel(0x0f051616, &phy->ptr[3]);
  26                 writel(0x06ae08d6, &phy->ptr[4]);
  27         } else {
  28                 writel(0x12061A80, &phy->ptr[3]);
  29                 writel(0x08027100, &phy->ptr[4]);
  30         }
  31         writel(0xF004001A, &phy->dsgcr);
  32
  33         /* change the value of the on-die pull-up/pull-down registors */
  34         tmp = readl(&phy->dxccr);
  35         tmp &= ~0x0ee0;
  36         tmp |= DXCCR_DQSNRES_688_OHM | DXCCR_DQSRES_688_OHM;
  37         writel(tmp, &phy->dxccr);
  38
  39         writel(0x0000040B, &phy->dcr);
  40         if (freq == 1333) {
  41                 writel(0x85589955, &phy->dtpr[0]);
  42                 if (size == 1)
  43                         writel(0x1a8253c0, &phy->dtpr[1]);
  44                 else
  45                         writel(0x1a8363c0, &phy->dtpr[1]);
  46                 writel(0x5002c200, &phy->dtpr[2]);
  47                 writel(0x00000b51, &phy->mr0);
  48         } else {
  49                 writel(0x999cbb66, &phy->dtpr[0]);
  50                 if (size == 1)
  51                         writel(0x1a82dbc0, &phy->dtpr[1]);
  52                 else
  53                         writel(0x1a878400, &phy->dtpr[1]);
  54                 writel(0xa00214f8, &phy->dtpr[2]);
  55                 writel(0x00000d71, &phy->mr0);
  56         }
  57         writel(0x00000006, &phy->mr1);
  58         if (freq == 1333)
  59                 writel(0x00000290, &phy->mr2);
  60         else
  61                 writel(0x00000298, &phy->mr2);
  62
  63         writel(0x00000800, &phy->mr3);
  64
  65         while (!(readl(&phy->pgsr[0]) & PGSR0_IDONE))
  66                 ;
  67
  68         writel(0x0300C473, &phy->pgcr[1]);
  69         writel(0x0000005D, &phy->zq[0].cr[1]);
  70 }