3 * David Feng <fenghua@phytium.com.cn>
5 * SPDX-License-Identifier: GPL-2.0+
8 #include <asm-offsets.h>
11 #include <linux/linkage.h>
12 #include <asm/macro.h>
13 #include <asm/armv8/mmu.h>
15 /*************************************************************************
17 * Startup Code (reset vector)
19 *************************************************************************/
29 .quad CONFIG_SYS_TEXT_BASE
32 * These are defined in the linker script.
40 .quad __bss_start - _start
44 .quad __bss_end - _start
48 * Could be EL3/EL2/EL1, Initial State:
49 * Little Endian, MMU Disabled, i/dCache Disabled
52 switch_el x1, 3f, 2f, 1f
54 msr cptr_el3, xzr /* Enable FP/SIMD */
55 ldr x0, =COUNTER_FREQUENCY
56 msr cntfrq_el0, x0 /* Initialize CNTFRQ */
60 msr cptr_el2, x0 /* Enable FP/SIMD */
64 msr cpacr_el1, x0 /* Enable FP/SIMD */
68 * Cache/BPB/TLB Invalidate
69 * i-cache is invalidated before enabled in icache_enable()
70 * tlb is invalidated before mmu is enabled in dcache_enable()
71 * d-cache is invalidated before enabled in dcache_enable()
74 /* Processor specific initialization */
77 branch_if_master x0, x1, master_cpu
84 ldr x1, =CPU_RELEASE_ADDR
87 br x0 /* branch to the given address */
95 /*-----------------------------------------------------------------------*/
98 /* Initialize GIC Secure Bank Status */
99 mov x29, lr /* Save LR */
102 branch_if_master x0, x1, 1f
105 * Slave should wait for master clearing spin table.
106 * This sync prevent salves observing incorrect
107 * value of spin table and jumping to wrong place.
112 * All processors will enter EL2 and optionally EL1.
114 bl armv8_switch_to_el2
115 #ifdef CONFIG_ARMV8_SWITCH_TO_EL1
116 bl armv8_switch_to_el1
120 mov lr, x29 /* Restore LR */
122 ENDPROC(lowlevel_init)
124 /*-----------------------------------------------------------------------*/
126 ENTRY(c_runtime_cpu_setup)
129 switch_el x1, 3f, 2f, 1f
138 ENDPROC(c_runtime_cpu_setup)