2 * Startup Code for S3C44B0 CPU-core
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30 #include <asm-offsets.h>
41 add pc, pc, #0x0c000000
42 add pc, pc, #0x0c000000
43 add pc, pc, #0x0c000000
44 add pc, pc, #0x0c000000
45 add pc, pc, #0x0c000000
46 add pc, pc, #0x0c000000
47 add pc, pc, #0x0c000000
49 .balignl 16,0xdeadbeef
53 *************************************************************************
55 * Startup Code (reset vector)
57 * do important init only if we don't start from memory!
58 * relocate u-boot to ram
60 * jump to second stage
62 *************************************************************************
67 .word CONFIG_SYS_TEXT_BASE
70 * These are defined in the board-specific linker script.
71 * Subtracting _start from them lets the linker put their
72 * relative position in the executable instead of leaving
77 .word __bss_start - _start
84 /* IRQ stack memory (calculated at run-time) */
85 .globl IRQ_STACK_START
89 /* IRQ stack memory (calculated at run-time) */
90 .globl FIQ_STACK_START
95 /* IRQ stack memory (calculated at run-time) + 8 bytes */
96 .globl IRQ_STACK_START_IN
101 * the actual reset code
106 * set the cpu to SVC32 mode
114 * we do sys-critical inits only at reboot,
115 * not when booting from ram!
117 #ifndef CONFIG_SKIP_LOWLEVEL_INIT
120 * before relocating, we have to setup RAM timing
121 * because memory timing is board-dependend, you will
122 * find a lowlevel_init.S in your board directory.
127 /* Set stackpointer in internal RAM to call board_init_f */
129 ldr sp, =(CONFIG_SYS_INIT_SP_ADDR)
133 /*------------------------------------------------------------------------------*/
136 * void relocate_code (addr_sp, gd, addr_moni)
138 * This "function" does not return, instead it continues in RAM
139 * after relocating the monitor code.
144 mov r4, r0 /* save addr_sp */
145 mov r5, r1 /* save addr of gd */
146 mov r6, r2 /* save addr of destination */
147 mov r7, r2 /* save addr of destination */
149 /* Set up the stack */
155 ldr r3, _bss_start_ofs
156 add r2, r0, r3 /* r2 <- source end address */
161 ldmia r0!, {r9-r10} /* copy from source address [r0] */
162 stmia r6!, {r9-r10} /* copy to target address [r1] */
163 cmp r0, r2 /* until source end address [r2] */
166 #ifndef CONFIG_PRELOADER
168 * fix .rel.dyn relocations
170 ldr r0, _TEXT_BASE /* r0 <- Text base */
171 sub r9, r7, r0 /* r9 <- relocation offset */
172 ldr r10, _dynsym_start_ofs /* r10 <- sym table ofs */
173 add r10, r10, r0 /* r10 <- sym table in FLASH */
174 ldr r2, _rel_dyn_start_ofs /* r2 <- rel dyn start ofs */
175 add r2, r2, r0 /* r2 <- rel dyn start in FLASH */
176 ldr r3, _rel_dyn_end_ofs /* r3 <- rel dyn end ofs */
177 add r3, r3, r0 /* r3 <- rel dyn end in FLASH */
179 ldr r0, [r2] /* r0 <- location to fix up, IN FLASH! */
180 add r0, r0, r9 /* r0 <- location to fix up in RAM */
183 cmp r8, #23 /* relative fixup? */
185 cmp r8, #2 /* absolute fixup? */
187 /* ignore unknown type of fixup */
190 /* absolute fix: set location to (offset) symbol value */
191 mov r1, r1, LSR #4 /* r1 <- symbol index in .dynsym */
192 add r1, r10, r1 /* r1 <- address of symbol in table */
193 ldr r1, [r1, #4] /* r1 <- symbol value */
194 add r1, r9 /* r1 <- relocated sym addr */
197 /* relative fix: increase location by offset */
202 add r2, r2, #8 /* each rel.dyn entry is 8 bytes */
208 #ifndef CONFIG_PRELOADER
209 ldr r0, _bss_start_ofs
211 ldr r3, _TEXT_BASE /* Text base */
212 mov r4, r7 /* reloc addr */
215 mov r2, #0x00000000 /* clear */
217 clbss_l:str r2, [r0] /* clear loop... */
227 * We are done. Do not return, instead branch to second part of board
228 * initialization, now running from RAM.
230 ldr r0, _board_init_r_ofs
234 /* setup parameters for board_init_r */
235 mov r0, r5 /* gd_t */
236 mov r1, r7 /* dest_addr */
241 .word board_init_r - _start
244 .word __rel_dyn_start - _start
246 .word __rel_dyn_end - _start
248 .word __dynsym_start - _start
251 *************************************************************************
253 * CPU_init_critical registers
255 * setup important registers
256 * setup memory timing
258 *************************************************************************
261 #define INTCON (0x01c00000+0x200000)
262 #define INTMSK (0x01c00000+0x20000c)
263 #define LOCKTIME (0x01c00000+0x18000c)
264 #define PLLCON (0x01c00000+0x180000)
265 #define CLKCON (0x01c00000+0x180004)
266 #define WTCON (0x01c00000+0x130000)
268 /* disable watch dog */
274 * mask all IRQs by clearing all bits in the INTMRs
284 /* Set Clock Control Register */
291 #if CONFIG_S3C44B0_CLOCK_SPEED==66
292 ldr r0, =0x34031 /* 66MHz (Quartz=11MHz) */
293 #elif CONFIG_S3C44B0_CLOCK_SPEED==75
294 ldr r0, =0x610c1 /*B2: Xtal=20mhz Fclk=75MHz */
296 # error CONFIG_S3C44B0_CLOCK_SPEED undefined
308 /*************************************************/
309 /* interrupt vectors */
310 /*************************************************/
313 b undefined_instruction
321 /*************************************************/
323 undefined_instruction:
340 /* we *should* never reach this */