2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
3 * Copyright (c) 2011 The Chromium OS Authors.
5 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/pinmux.h>
12 /* return 1 if a pingrp is in range */
13 #define pmux_pingrp_isvalid(pin) (((pin) >= 0) && ((pin) < PMUX_PINGRP_COUNT))
15 /* return 1 if a pmux_func is in range */
16 #define pmux_func_isvalid(func) \
17 ((((func) >= 0) && ((func) < PMUX_FUNC_COUNT)) || \
18 (((func) >= PMUX_FUNC_RSVD1) && ((func) <= PMUX_FUNC_RSVD4)))
20 /* return 1 if a pin_pupd_is in range */
21 #define pmux_pin_pupd_isvalid(pupd) \
22 (((pupd) >= PMUX_PULL_NORMAL) && ((pupd) <= PMUX_PULL_UP))
24 /* return 1 if a pin_tristate_is in range */
25 #define pmux_pin_tristate_isvalid(tristate) \
26 (((tristate) >= PMUX_TRI_NORMAL) && ((tristate) <= PMUX_TRI_TRISTATE))
28 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
29 /* return 1 if a pin_io_is in range */
30 #define pmux_pin_io_isvalid(io) \
31 (((io) >= PMUX_PIN_OUTPUT) && ((io) <= PMUX_PIN_INPUT))
33 /* return 1 if a pin_lock is in range */
34 #define pmux_pin_lock_isvalid(lock) \
35 (((lock) >= PMUX_PIN_LOCK_DISABLE) && ((lock) <= PMUX_PIN_LOCK_ENABLE))
37 /* return 1 if a pin_od is in range */
38 #define pmux_pin_od_isvalid(od) \
39 (((od) >= PMUX_PIN_OD_DISABLE) && ((od) <= PMUX_PIN_OD_ENABLE))
41 /* return 1 if a pin_ioreset_is in range */
42 #define pmux_pin_ioreset_isvalid(ioreset) \
43 (((ioreset) >= PMUX_PIN_IO_RESET_DISABLE) && \
44 ((ioreset) <= PMUX_PIN_IO_RESET_ENABLE))
46 #ifdef TEGRA_PMX_HAS_RCV_SEL
47 /* return 1 if a pin_rcv_sel_is in range */
48 #define pmux_pin_rcv_sel_isvalid(rcv_sel) \
49 (((rcv_sel) >= PMUX_PIN_RCV_SEL_NORMAL) && \
50 ((rcv_sel) <= PMUX_PIN_RCV_SEL_HIGH))
51 #endif /* TEGRA_PMX_HAS_RCV_SEL */
52 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
54 #define _R(offset) (u32 *)(NV_PA_APB_MISC_BASE + (offset))
56 #if defined(CONFIG_TEGRA20)
58 #define MUX_REG(grp) _R(0x80 + ((tegra_soc_pingroups[grp].ctl_id / 16) * 4))
59 #define MUX_SHIFT(grp) ((tegra_soc_pingroups[grp].ctl_id % 16) * 2)
61 #define PULL_REG(grp) _R(0xa0 + ((tegra_soc_pingroups[grp].pull_id / 16) * 4))
62 #define PULL_SHIFT(grp) ((tegra_soc_pingroups[grp].pull_id % 16) * 2)
64 #define TRI_REG(grp) _R(0x14 + (((grp) / 32) * 4))
65 #define TRI_SHIFT(grp) ((grp) % 32)
69 #define REG(pin) _R(0x3000 + ((pin) * 4))
71 #define MUX_REG(pin) REG(pin)
72 #define MUX_SHIFT(pin) 0
74 #define PULL_REG(pin) REG(pin)
75 #define PULL_SHIFT(pin) 2
77 #define TRI_REG(pin) REG(pin)
78 #define TRI_SHIFT(pin) 4
80 #endif /* CONFIG_TEGRA20 */
82 #define DRV_REG(group) _R(0x868 + ((group) * 4))
87 #define IO_RESET_SHIFT 8
88 #define RCV_SEL_SHIFT 9
90 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
92 u32 *reg = MUX_REG(pin);
96 /* Error check on pin and func */
97 assert(pmux_pingrp_isvalid(pin));
98 assert(pmux_func_isvalid(func));
100 if (func & PMUX_FUNC_RSVD1) {
103 /* Search for the appropriate function */
104 for (i = 0; i < 4; i++) {
105 if (tegra_soc_pingroups[pin].funcs[i] == func) {
114 val &= ~(3 << MUX_SHIFT(pin));
115 val |= (mux << MUX_SHIFT(pin));
119 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
121 u32 *reg = PULL_REG(pin);
124 /* Error check on pin and pupd */
125 assert(pmux_pingrp_isvalid(pin));
126 assert(pmux_pin_pupd_isvalid(pupd));
129 val &= ~(3 << PULL_SHIFT(pin));
130 val |= (pupd << PULL_SHIFT(pin));
134 static void pinmux_set_tristate(enum pmux_pingrp pin, int tri)
136 u32 *reg = TRI_REG(pin);
139 /* Error check on pin */
140 assert(pmux_pingrp_isvalid(pin));
141 assert(pmux_pin_tristate_isvalid(tri));
144 if (tri == PMUX_TRI_TRISTATE)
145 val |= (1 << TRI_SHIFT(pin));
147 val &= ~(1 << TRI_SHIFT(pin));
151 void pinmux_tristate_enable(enum pmux_pingrp pin)
153 pinmux_set_tristate(pin, PMUX_TRI_TRISTATE);
156 void pinmux_tristate_disable(enum pmux_pingrp pin)
158 pinmux_set_tristate(pin, PMUX_TRI_NORMAL);
161 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
162 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
167 if (io == PMUX_PIN_NONE)
170 /* Error check on pin and io */
171 assert(pmux_pingrp_isvalid(pin));
172 assert(pmux_pin_io_isvalid(io));
175 if (io == PMUX_PIN_INPUT)
176 val |= (io & 1) << IO_SHIFT;
178 val &= ~(1 << IO_SHIFT);
182 static void pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
187 if (lock == PMUX_PIN_LOCK_DEFAULT)
190 /* Error check on pin and lock */
191 assert(pmux_pingrp_isvalid(pin));
192 assert(pmux_pin_lock_isvalid(lock));
195 if (lock == PMUX_PIN_LOCK_ENABLE) {
196 val |= (1 << LOCK_SHIFT);
198 if (val & (1 << LOCK_SHIFT))
199 printf("%s: Cannot clear LOCK bit!\n", __func__);
200 val &= ~(1 << LOCK_SHIFT);
207 static void pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
212 if (od == PMUX_PIN_OD_DEFAULT)
215 /* Error check on pin and od */
216 assert(pmux_pingrp_isvalid(pin));
217 assert(pmux_pin_od_isvalid(od));
220 if (od == PMUX_PIN_OD_ENABLE)
221 val |= (1 << OD_SHIFT);
223 val &= ~(1 << OD_SHIFT);
229 static void pinmux_set_ioreset(enum pmux_pingrp pin,
230 enum pmux_pin_ioreset ioreset)
235 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
238 /* Error check on pin and ioreset */
239 assert(pmux_pingrp_isvalid(pin));
240 assert(pmux_pin_ioreset_isvalid(ioreset));
243 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
244 val |= (1 << IO_RESET_SHIFT);
246 val &= ~(1 << IO_RESET_SHIFT);
252 #ifdef TEGRA_PMX_HAS_RCV_SEL
253 static void pinmux_set_rcv_sel(enum pmux_pingrp pin,
254 enum pmux_pin_rcv_sel rcv_sel)
259 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
262 /* Error check on pin and rcv_sel */
263 assert(pmux_pingrp_isvalid(pin));
264 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
267 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
268 val |= (1 << RCV_SEL_SHIFT);
270 val &= ~(1 << RCV_SEL_SHIFT);
275 #endif /* TEGRA_PMX_HAS_RCV_SEL */
276 #endif /* TEGRA_PMX_HAS_PIN_IO_BIT_ETC */
278 static void pinmux_config_pingrp(const struct pmux_pingrp_config *config)
280 enum pmux_pingrp pin = config->pingrp;
282 pinmux_set_func(pin, config->func);
283 pinmux_set_pullupdown(pin, config->pull);
284 pinmux_set_tristate(pin, config->tristate);
285 #ifdef TEGRA_PMX_HAS_PIN_IO_BIT_ETC
286 pinmux_set_io(pin, config->io);
287 pinmux_set_lock(pin, config->lock);
288 pinmux_set_od(pin, config->od);
289 pinmux_set_ioreset(pin, config->ioreset);
290 #ifdef TEGRA_PMX_HAS_RCV_SEL
291 pinmux_set_rcv_sel(pin, config->rcv_sel);
296 void pinmux_config_pingrp_table(const struct pmux_pingrp_config *config,
301 for (i = 0; i < len; i++)
302 pinmux_config_pingrp(&config[i]);
305 #ifdef TEGRA_PMX_HAS_DRVGRPS
307 #define pmux_drvgrp_isvalid(pd) (((pd) >= 0) && ((pd) < PMUX_DRVGRP_COUNT))
309 #define pmux_slw_isvalid(slw) \
310 (((slw) >= PMUX_SLWF_MIN) && ((slw) <= PMUX_SLWF_MAX))
312 #define pmux_drv_isvalid(drv) \
313 (((drv) >= PMUX_DRVUP_MIN) && ((drv) <= PMUX_DRVUP_MAX))
315 #define pmux_lpmd_isvalid(lpm) \
316 (((lpm) >= PMUX_LPMD_X8) && ((lpm) <= PMUX_LPMD_X))
318 #define pmux_schmt_isvalid(schmt) \
319 (((schmt) >= PMUX_SCHMT_DISABLE) && ((schmt) <= PMUX_SCHMT_ENABLE))
321 #define pmux_hsm_isvalid(hsm) \
322 (((hsm) >= PMUX_HSM_DISABLE) && ((hsm) <= PMUX_HSM_ENABLE))
325 #define SCHMT_SHIFT 3
327 #define LPMD_MASK (3 << LPMD_SHIFT)
328 #define DRVDN_SHIFT 12
329 #define DRVDN_MASK (0x7F << DRVDN_SHIFT)
330 #define DRVUP_SHIFT 20
331 #define DRVUP_MASK (0x7F << DRVUP_SHIFT)
332 #define SLWR_SHIFT 28
333 #define SLWR_MASK (3 << SLWR_SHIFT)
334 #define SLWF_SHIFT 30
335 #define SLWF_MASK (3 << SLWF_SHIFT)
337 static void pinmux_set_drvup_slwf(enum pmux_drvgrp grp, int slwf)
339 u32 *reg = DRV_REG(grp);
342 /* NONE means unspecified/do not change/use POR value */
343 if (slwf == PMUX_SLWF_NONE)
346 /* Error check on pad and slwf */
347 assert(pmux_drvgrp_isvalid(grp));
348 assert(pmux_slw_isvalid(slwf));
352 val |= (slwf << SLWF_SHIFT);
358 static void pinmux_set_drvdn_slwr(enum pmux_drvgrp grp, int slwr)
360 u32 *reg = DRV_REG(grp);
363 /* NONE means unspecified/do not change/use POR value */
364 if (slwr == PMUX_SLWR_NONE)
367 /* Error check on pad and slwr */
368 assert(pmux_drvgrp_isvalid(grp));
369 assert(pmux_slw_isvalid(slwr));
373 val |= (slwr << SLWR_SHIFT);
379 static void pinmux_set_drvup(enum pmux_drvgrp grp, int drvup)
381 u32 *reg = DRV_REG(grp);
384 /* NONE means unspecified/do not change/use POR value */
385 if (drvup == PMUX_DRVUP_NONE)
388 /* Error check on pad and drvup */
389 assert(pmux_drvgrp_isvalid(grp));
390 assert(pmux_drv_isvalid(drvup));
394 val |= (drvup << DRVUP_SHIFT);
400 static void pinmux_set_drvdn(enum pmux_drvgrp grp, int drvdn)
402 u32 *reg = DRV_REG(grp);
405 /* NONE means unspecified/do not change/use POR value */
406 if (drvdn == PMUX_DRVDN_NONE)
409 /* Error check on pad and drvdn */
410 assert(pmux_drvgrp_isvalid(grp));
411 assert(pmux_drv_isvalid(drvdn));
415 val |= (drvdn << DRVDN_SHIFT);
421 static void pinmux_set_lpmd(enum pmux_drvgrp grp, enum pmux_lpmd lpmd)
423 u32 *reg = DRV_REG(grp);
426 /* NONE means unspecified/do not change/use POR value */
427 if (lpmd == PMUX_LPMD_NONE)
430 /* Error check pad and lpmd value */
431 assert(pmux_drvgrp_isvalid(grp));
432 assert(pmux_lpmd_isvalid(lpmd));
436 val |= (lpmd << LPMD_SHIFT);
442 static void pinmux_set_schmt(enum pmux_drvgrp grp, enum pmux_schmt schmt)
444 u32 *reg = DRV_REG(grp);
447 /* NONE means unspecified/do not change/use POR value */
448 if (schmt == PMUX_SCHMT_NONE)
451 /* Error check pad */
452 assert(pmux_drvgrp_isvalid(grp));
453 assert(pmux_schmt_isvalid(schmt));
456 if (schmt == PMUX_SCHMT_ENABLE)
457 val |= (1 << SCHMT_SHIFT);
459 val &= ~(1 << SCHMT_SHIFT);
465 static void pinmux_set_hsm(enum pmux_drvgrp grp, enum pmux_hsm hsm)
467 u32 *reg = DRV_REG(grp);
470 /* NONE means unspecified/do not change/use POR value */
471 if (hsm == PMUX_HSM_NONE)
474 /* Error check pad */
475 assert(pmux_drvgrp_isvalid(grp));
476 assert(pmux_hsm_isvalid(hsm));
479 if (hsm == PMUX_HSM_ENABLE)
480 val |= (1 << HSM_SHIFT);
482 val &= ~(1 << HSM_SHIFT);
488 static void pinmux_config_drvgrp(const struct pmux_drvgrp_config *config)
490 enum pmux_drvgrp grp = config->drvgrp;
492 pinmux_set_drvup_slwf(grp, config->slwf);
493 pinmux_set_drvdn_slwr(grp, config->slwr);
494 pinmux_set_drvup(grp, config->drvup);
495 pinmux_set_drvdn(grp, config->drvdn);
496 pinmux_set_lpmd(grp, config->lpmd);
497 pinmux_set_schmt(grp, config->schmt);
498 pinmux_set_hsm(grp, config->hsm);
501 void pinmux_config_drvgrp_table(const struct pmux_drvgrp_config *config,
506 for (i = 0; i < len; i++)
507 pinmux_config_drvgrp(&config[i]);
509 #endif /* TEGRA_PMX_HAS_DRVGRPS */