2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra114 pin multiplexing functions */
21 #include <asm/arch/tegra.h>
22 #include <asm/arch/pinmux.h>
24 struct tegra_pingroup_desc {
26 enum pmux_func funcs[4];
30 #define PMUX_MUXCTL_SHIFT 0
31 #define PMUX_PULL_SHIFT 2
32 #define PMUX_TRISTATE_SHIFT 4
33 #define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
34 #define PMUX_IO_SHIFT 5
35 #define PMUX_OD_SHIFT 6
36 #define PMUX_LOCK_SHIFT 7
37 #define PMUX_IO_RESET_SHIFT 8
38 #define PMUX_RCV_SEL_SHIFT 9
40 #define PGRP_HSM_SHIFT 2
41 #define PGRP_SCHMT_SHIFT 3
42 #define PGRP_LPMD_SHIFT 4
43 #define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
44 #define PGRP_DRVDN_SHIFT 12
45 #define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
46 #define PGRP_DRVUP_SHIFT 20
47 #define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
48 #define PGRP_SLWR_SHIFT 28
49 #define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
50 #define PGRP_SLWF_SHIFT 30
51 #define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
53 /* Convenient macro for defining pin group properties */
54 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
62 .io = PMUX_PIN_ ## iod, \
65 /* Input and output pins */
66 #define PINI(pg_name, vdd, f0, f1, f2, f3) \
67 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
68 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
69 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
71 /* A pin group number which is not used */
72 #define PIN_RESERVED \
73 PIN(NONE, NONE, INVALID, INVALID, INVALID, INVALID, NONE)
75 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
76 /* NAME VDD f0 f1 f2 f3 */
77 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
78 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
79 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
80 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
81 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
82 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
83 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
84 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
85 PINI(ULPI_CLK, BB, SPI1, SPI5, UARTD, ULPI),
86 PINI(ULPI_DIR, BB, SPI1, SPI5, UARTD, ULPI),
87 PINI(ULPI_NXT, BB, SPI1, SPI5, UARTD, ULPI),
88 PINI(ULPI_STP, BB, SPI1, SPI5, UARTD, ULPI),
89 PINI(DAP3_FS, BB, I2S2, SPI5, DISPA, DISPB),
90 PINI(DAP3_DIN, BB, I2S2, SPI5, DISPA, DISPB),
91 PINI(DAP3_DOUT, BB, I2S2, SPI5, DISPA, DISPB),
92 PINI(DAP3_SCLK, BB, I2S2, SPI5, DISPA, DISPB),
93 PINI(GPIO_PV0, BB, USB, RSVD2, RSVD3, RSVD4),
94 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
95 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, CLK12, RSVD3, RSVD4),
96 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
97 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, SPDIF, SPI4, UARTA),
98 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, PWM0, SPI4, UARTA),
99 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, PWM1, SPI4, UARTA),
100 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, SPI4, UARTA),
101 PIN_RESERVED, /* Reserved by t114: 0x3060 - 0x3064 */
103 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
104 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
105 PIN_RESERVED, /* Reserved by t114: 0x3070 - 0x310c */
145 PINI(HDMI_INT, LCD, RSVD1, RSVD2, RSVD3, RSVD4),
146 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
147 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
148 PIN_RESERVED, /* Reserved by t114: 0x311c - 0x3160 */
166 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
167 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
168 PINI(UART2_RTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
169 PINI(UART2_CTS_N, UART, UARTA, UARTB, RSVD3, SPI4),
170 PINI(UART3_TXD, UART, UARTC, RSVD2, RSVD3, SPI4),
171 PINI(UART3_RXD, UART, UARTC, RSVD2, RSVD3, SPI4),
172 PINI(UART3_CTS_N, UART, UARTC, SDMMC1, DTV, SPI4),
173 PINI(UART3_RTS_N, UART, UARTC, PWM0, DTV, DISPA),
174 PINI(GPIO_PU0, UART, OWR, UARTA, RSVD3, RSVD4),
175 PINI(GPIO_PU1, UART, RSVD1, UARTA, RSVD3, RSVD4),
176 PINI(GPIO_PU2, UART, RSVD1, UARTA, RSVD3, RSVD4),
177 PINI(GPIO_PU3, UART, PWM0, UARTA, DISPA, DISPB),
178 PINI(GPIO_PU4, UART, PWM1, UARTA, DISPA, DISPB),
179 PINI(GPIO_PU5, UART, PWM2, UARTA, DISPA, DISPB),
180 PINI(GPIO_PU6, UART, PWM3, UARTA, USB, DISPB),
181 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
182 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
183 PINI(DAP4_FS, UART, I2S3, RSVD2, DTV, RSVD4),
184 PINI(DAP4_DIN, UART, I2S3, RSVD2, RSVD3, RSVD4),
185 PINI(DAP4_DOUT, UART, I2S3, RSVD2, DTV, RSVD4),
186 PINI(DAP4_SCLK, UART, I2S3, RSVD2, RSVD3, RSVD4),
187 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
188 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
189 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
190 PINI(GMI_IORDY, GMI, SDMMC2, RSVD2, GMI, TRACE),
191 PINI(GMI_WAIT, GMI, SPI4, NAND, GMI, DTV),
192 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, TRACE),
193 PINI(GMI_CLK, GMI, SDMMC2, NAND, GMI, TRACE),
194 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, USB),
195 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, SOC),
196 PINI(GMI_CS2_N, GMI, SDMMC2, NAND, GMI, TRACE),
197 PINI(GMI_CS3_N, GMI, SDMMC2, NAND, GMI, GMI_ALT),
198 PINI(GMI_CS4_N, GMI, USB, NAND, GMI, TRACE),
199 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SPI4),
200 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, SDMMC2),
201 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
202 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
203 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
204 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
205 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
206 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, SPI4),
207 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, SPI4),
208 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, SPI4),
209 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, DTV),
210 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, CLDVFS),
211 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, CLDVFS),
212 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, USB),
213 PINI(GMI_AD12, GMI, SDMMC2, NAND, GMI, RSVD4),
214 PINI(GMI_AD13, GMI, SDMMC2, NAND, GMI, RSVD4),
215 PINI(GMI_AD14, GMI, SDMMC2, NAND, GMI, DTV),
216 PINI(GMI_AD15, GMI, SDMMC2, NAND, GMI, DTV),
217 PINI(GMI_A16, GMI, UARTD, TRACE, GMI, GMI_ALT),
218 PINI(GMI_A17, GMI, UARTD, RSVD2, GMI, TRACE),
219 PINI(GMI_A18, GMI, UARTD, RSVD2, GMI, TRACE),
220 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, TRACE),
221 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, SPI4),
222 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, SOC),
223 PINI(GMI_DQS, GMI, SDMMC2, NAND, GMI, TRACE),
224 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
225 PINI(GEN2_I2C_SCL, GMI, I2C2, RSVD2, GMI, RSVD4),
226 PINI(GEN2_I2C_SDA, GMI, I2C2, RSVD2, GMI, RSVD4),
227 PINI(SDMMC4_CLK, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
228 PINI(SDMMC4_CMD, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
229 PINI(SDMMC4_DAT0, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
230 PINI(SDMMC4_DAT1, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
231 PINI(SDMMC4_DAT2, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
232 PINI(SDMMC4_DAT3, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
233 PINI(SDMMC4_DAT4, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
234 PINI(SDMMC4_DAT5, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
235 PINI(SDMMC4_DAT6, SDMMC4, SDMMC4, SPI3, GMI, RSVD4),
236 PINI(SDMMC4_DAT7, SDMMC4, SDMMC4, RSVD2, GMI, RSVD4),
237 PIN_RESERVED, /* Reserved by t114: 0x3280 */
238 PINI(CAM_MCLK, CAM, VI, VI_ALT1, VI_ALT3, RSVD4),
239 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, RSVD4),
240 PINI(GPIO_PBB0, CAM, I2S4, VI, VI_ALT1, VI_ALT3),
241 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, RSVD4),
242 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, RSVD4),
243 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, RSVD4),
244 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, RSVD4),
245 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, RSVD4),
246 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, RSVD4),
247 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, RSVD4),
248 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
249 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
250 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
251 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
252 PINI(KB_ROW0, SYS, KBC, RSVD2, DTV, RSVD4),
253 PINI(KB_ROW1, SYS, KBC, RSVD2, DTV, RSVD4),
254 PINI(KB_ROW2, SYS, KBC, RSVD2, DTV, SOC),
255 PINI(KB_ROW3, SYS, KBC, DISPA, RSVD3, DISPB),
256 PINI(KB_ROW4, SYS, KBC, DISPA, SPI2, DISPB),
257 PINI(KB_ROW5, SYS, KBC, DISPA, SPI2, DISPB),
258 PINI(KB_ROW6, SYS, KBC, DISPA, RSVD3, DISPB),
259 PINI(KB_ROW7, SYS, KBC, RSVD2, CLDVFS, UARTA),
260 PINI(KB_ROW8, SYS, KBC, RSVD2, RSVD3, UARTA),
261 PINI(KB_ROW9, SYS, KBC, RSVD2, RSVD3, UARTA),
262 PINI(KB_ROW10, SYS, KBC, RSVD2, RSVD3, UARTA),
263 PIN_RESERVED, /* Reserved by t114: 0x32e8 - 0x32f8 */
268 PINI(KB_COL0, SYS, KBC, USB, SPI2, EMC_DLL),
269 PINI(KB_COL1, SYS, KBC, RSVD2, SPI2, EMC_DLL),
270 PINI(KB_COL2, SYS, KBC, RSVD2, SPI2, RSVD4),
271 PINI(KB_COL3, SYS, KBC, DISPA, PWM2, UARTA),
272 PINI(KB_COL4, SYS, KBC, OWR, SDMMC3, UARTA),
273 PINI(KB_COL5, SYS, KBC, RSVD2, SDMMC1, RSVD4),
274 PINI(KB_COL6, SYS, KBC, RSVD2, SPI2, RSVD4),
275 PINI(KB_COL7, SYS, KBC, RSVD2, SPI2, RSVD4),
276 PINI(CLK_32K_OUT, SYS, BLINK, SOC, RSVD3, RSVD4),
277 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
278 PINI(CORE_PWR_REQ, SYS, PWRON, RSVD2, RSVD3, RSVD4),
279 PINI(CPU_PWR_REQ, SYS, CPU, RSVD2, RSVD3, RSVD4),
280 PINI(PWR_INT_N, SYS, PMI, RSVD2, RSVD3, RSVD4),
281 PINI(CLK_32K_IN, SYS, CLK, RSVD2, RSVD3, RSVD4),
282 PINI(OWR, SYS, OWR, RSVD2, RSVD3, RSVD4),
283 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, RSVD4),
284 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, RSVD4),
285 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, RSVD4),
286 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, RSVD4),
287 PINI(CLK1_REQ, AUDIO, DAP, DAP1, RSVD3, RSVD4),
288 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, DAP2, RSVD3, RSVD4),
289 PINI(SPDIF_IN, AUDIO, SPDIF, USB, RSVD3, RSVD4),
290 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, RSVD3, RSVD4),
291 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, RSVD4),
292 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, RSVD4),
293 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, RSVD4),
294 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, RSVD4),
295 PINI(DVFS_PWM, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
296 PINI(GPIO_X1_AUD, AUDIO, SPI6, RSVD2, RSVD3, RSVD4),
297 PINI(GPIO_X3_AUD, AUDIO, SPI6, SPI1, RSVD3, RSVD4),
298 PINI(DVFS_CLK, AUDIO, SPI6, CLDVFS, RSVD3, RSVD4),
299 PINI(GPIO_X4_AUD, AUDIO, RSVD1, SPI1, SPI2, DAP2),
300 PINI(GPIO_X5_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
301 PINI(GPIO_X6_AUD, AUDIO, SPI6, SPI1, SPI2, RSVD4),
302 PINI(GPIO_X7_AUD, AUDIO, RSVD1, SPI1, SPI2, RSVD4),
303 PIN_RESERVED, /* Reserved by t114: 0x3388 - 0x338c */
305 PINI(SDMMC3_CLK, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
306 PINI(SDMMC3_CMD, SDMMC3, SDMMC3, PWM3, UARTA, SPI3),
307 PINI(SDMMC3_DAT0, SDMMC3, SDMMC3, RSVD2, RSVD3, SPI3),
308 PINI(SDMMC3_DAT1, SDMMC3, SDMMC3, PWM2, UARTA, SPI3),
309 PINI(SDMMC3_DAT2, SDMMC3, SDMMC3, PWM1, DISPA, SPI3),
310 PINI(SDMMC3_DAT3, SDMMC3, SDMMC3, PWM0, DISPB, SPI3),
311 PIN_RESERVED, /* Reserved by t114: 0x33a8 - 0x33dc */
325 PINI(HDMI_CEC, SYS, CEC, SDMMC3, RSVD3, SOC),
326 PINI(SDMMC1_WP_N, SDMMC1, SDMMC1, CLK12, SPI4, UARTA),
327 PINI(SDMMC3_CD_N, SYS, SDMMC3, OWR, RSVD3, RSVD4),
328 PINI(GPIO_W2_AUD, AUDIO, SPI6, RSVD2, SPI2, I2C1),
329 PINI(GPIO_W3_AUD, AUDIO, SPI6, SPI1, SPI2, I2C1),
330 PINI(USB_VBUS_EN0, LCD, USB, RSVD2, RSVD3, RSVD4),
331 PINI(USB_VBUS_EN1, LCD, USB, RSVD2, RSVD3, RSVD4),
332 PINI(SDMMC3_CLK_LB_IN, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
333 PINI(SDMMC3_CLK_LB_OUT, SDMMC3, SDMMC3, RSVD2, RSVD3, RSVD4),
334 PIN_RESERVED, /* Reserved by t114: 0x3404 */
335 PINO(RESET_OUT_N, SYS, RSVD1, RSVD2, RSVD3, RESET_OUT_N),
338 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
340 struct pmux_tri_ctlr *pmt =
341 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
342 u32 *tri = &pmt->pmt_ctl[pin];
345 /* Error check on pin */
346 assert(pmux_pingrp_isvalid(pin));
350 reg |= PMUX_TRISTATE_MASK;
352 reg &= ~PMUX_TRISTATE_MASK;
356 void pinmux_tristate_enable(enum pmux_pingrp pin)
358 pinmux_set_tristate(pin, 1);
361 void pinmux_tristate_disable(enum pmux_pingrp pin)
363 pinmux_set_tristate(pin, 0);
366 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
368 struct pmux_tri_ctlr *pmt =
369 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
370 u32 *pull = &pmt->pmt_ctl[pin];
373 /* Error check on pin and pupd */
374 assert(pmux_pingrp_isvalid(pin));
375 assert(pmux_pin_pupd_isvalid(pupd));
378 reg &= ~(0x3 << PMUX_PULL_SHIFT);
379 reg |= (pupd << PMUX_PULL_SHIFT);
383 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
385 struct pmux_tri_ctlr *pmt =
386 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
387 u32 *muxctl = &pmt->pmt_ctl[pin];
391 /* Error check on pin and func */
392 assert(pmux_pingrp_isvalid(pin));
393 assert(pmux_func_isvalid(func));
395 if (func & PMUX_FUNC_RSVD1) {
398 /* Search for the appropriate function */
399 for (i = 0; i < 4; i++) {
400 if (tegra_soc_pingroups[pin].funcs[i] == func) {
409 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
410 reg |= (mux << PMUX_MUXCTL_SHIFT);
415 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
417 struct pmux_tri_ctlr *pmt =
418 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
419 u32 *pin_io = &pmt->pmt_ctl[pin];
422 /* Error check on pin and io */
423 assert(pmux_pingrp_isvalid(pin));
424 assert(pmux_pin_io_isvalid(io));
427 reg &= ~(0x1 << PMUX_IO_SHIFT);
428 reg |= (io & 0x1) << PMUX_IO_SHIFT;
432 static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
434 struct pmux_tri_ctlr *pmt =
435 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
436 u32 *pin_lock = &pmt->pmt_ctl[pin];
439 /* Error check on pin and lock */
440 assert(pmux_pingrp_isvalid(pin));
441 assert(pmux_pin_lock_isvalid(lock));
443 if (lock == PMUX_PIN_LOCK_DEFAULT)
446 reg = readl(pin_lock);
447 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
448 if (lock == PMUX_PIN_LOCK_ENABLE)
449 reg |= (0x1 << PMUX_LOCK_SHIFT);
451 /* lock == DISABLE, which isn't possible */
452 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
455 writel(reg, pin_lock);
460 static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
462 struct pmux_tri_ctlr *pmt =
463 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
464 u32 *pin_od = &pmt->pmt_ctl[pin];
467 /* Error check on pin and od */
468 assert(pmux_pingrp_isvalid(pin));
469 assert(pmux_pin_od_isvalid(od));
471 if (od == PMUX_PIN_OD_DEFAULT)
475 reg &= ~(0x1 << PMUX_OD_SHIFT);
476 if (od == PMUX_PIN_OD_ENABLE)
477 reg |= (0x1 << PMUX_OD_SHIFT);
483 static int pinmux_set_ioreset(enum pmux_pingrp pin,
484 enum pmux_pin_ioreset ioreset)
486 struct pmux_tri_ctlr *pmt =
487 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
488 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
491 /* Error check on pin and ioreset */
492 assert(pmux_pingrp_isvalid(pin));
493 assert(pmux_pin_ioreset_isvalid(ioreset));
495 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
498 reg = readl(pin_ioreset);
499 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
500 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
501 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
502 writel(reg, pin_ioreset);
507 static int pinmux_set_rcv_sel(enum pmux_pingrp pin,
508 enum pmux_pin_rcv_sel rcv_sel)
510 struct pmux_tri_ctlr *pmt =
511 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
512 u32 *pin_rcv_sel = &pmt->pmt_ctl[pin];
515 /* Error check on pin and rcv_sel */
516 assert(pmux_pingrp_isvalid(pin));
517 assert(pmux_pin_rcv_sel_isvalid(rcv_sel));
519 if (rcv_sel == PMUX_PIN_RCV_SEL_DEFAULT)
522 reg = readl(pin_rcv_sel);
523 reg &= ~(0x1 << PMUX_RCV_SEL_SHIFT);
524 if (rcv_sel == PMUX_PIN_RCV_SEL_HIGH)
525 reg |= (0x1 << PMUX_RCV_SEL_SHIFT);
526 writel(reg, pin_rcv_sel);
531 void pinmux_config_pingroup(struct pingroup_config *config)
533 enum pmux_pingrp pin = config->pingroup;
535 pinmux_set_func(pin, config->func);
536 pinmux_set_pullupdown(pin, config->pull);
537 pinmux_set_tristate(pin, config->tristate);
538 pinmux_set_io(pin, config->io);
539 pinmux_set_lock(pin, config->lock);
540 pinmux_set_od(pin, config->od);
541 pinmux_set_ioreset(pin, config->ioreset);
542 pinmux_set_rcv_sel(pin, config->rcv_sel);
545 void pinmux_config_table(struct pingroup_config *config, int len)
549 for (i = 0; i < len; i++)
550 pinmux_config_pingroup(&config[i]);
553 static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad, int slwf)
555 struct pmux_tri_ctlr *pmt =
556 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
557 u32 *pad_slwf = &pmt->pmt_drive[pad];
560 /* Error check on pad and slwf */
561 assert(pmux_padgrp_isvalid(pad));
562 assert(pmux_pad_slw_isvalid(slwf));
564 /* NONE means unspecified/do not change/use POR value */
565 if (slwf == PGRP_SLWF_NONE)
568 reg = readl(pad_slwf);
569 reg &= ~PGRP_SLWF_MASK;
570 reg |= (slwf << PGRP_SLWF_SHIFT);
571 writel(reg, pad_slwf);
576 static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
578 struct pmux_tri_ctlr *pmt =
579 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
580 u32 *pad_slwr = &pmt->pmt_drive[pad];
583 /* Error check on pad and slwr */
584 assert(pmux_padgrp_isvalid(pad));
585 assert(pmux_pad_slw_isvalid(slwr));
587 /* NONE means unspecified/do not change/use POR value */
588 if (slwr == PGRP_SLWR_NONE)
591 reg = readl(pad_slwr);
592 reg &= ~PGRP_SLWR_MASK;
593 reg |= (slwr << PGRP_SLWR_SHIFT);
594 writel(reg, pad_slwr);
599 static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
601 struct pmux_tri_ctlr *pmt =
602 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
603 u32 *pad_drvup = &pmt->pmt_drive[pad];
606 /* Error check on pad and drvup */
607 assert(pmux_padgrp_isvalid(pad));
608 assert(pmux_pad_drv_isvalid(drvup));
610 /* NONE means unspecified/do not change/use POR value */
611 if (drvup == PGRP_DRVUP_NONE)
614 reg = readl(pad_drvup);
615 reg &= ~PGRP_DRVUP_MASK;
616 reg |= (drvup << PGRP_DRVUP_SHIFT);
617 writel(reg, pad_drvup);
622 static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
624 struct pmux_tri_ctlr *pmt =
625 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
626 u32 *pad_drvdn = &pmt->pmt_drive[pad];
629 /* Error check on pad and drvdn */
630 assert(pmux_padgrp_isvalid(pad));
631 assert(pmux_pad_drv_isvalid(drvdn));
633 /* NONE means unspecified/do not change/use POR value */
634 if (drvdn == PGRP_DRVDN_NONE)
637 reg = readl(pad_drvdn);
638 reg &= ~PGRP_DRVDN_MASK;
639 reg |= (drvdn << PGRP_DRVDN_SHIFT);
640 writel(reg, pad_drvdn);
645 static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
647 struct pmux_tri_ctlr *pmt =
648 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
649 u32 *pad_lpmd = &pmt->pmt_drive[pad];
652 /* Error check pad and lpmd value */
653 assert(pmux_padgrp_isvalid(pad));
654 assert(pmux_pad_lpmd_isvalid(lpmd));
656 /* NONE means unspecified/do not change/use POR value */
657 if (lpmd == PGRP_LPMD_NONE)
660 reg = readl(pad_lpmd);
661 reg &= ~PGRP_LPMD_MASK;
662 reg |= (lpmd << PGRP_LPMD_SHIFT);
663 writel(reg, pad_lpmd);
668 static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
670 struct pmux_tri_ctlr *pmt =
671 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
672 u32 *pad_schmt = &pmt->pmt_drive[pad];
675 /* Error check pad */
676 assert(pmux_padgrp_isvalid(pad));
678 /* NONE means unspecified/do not change/use POR value */
679 if (schmt == PGRP_SCHMT_NONE)
682 reg = readl(pad_schmt);
683 reg &= ~(1 << PGRP_SCHMT_SHIFT);
684 if (schmt == PGRP_SCHMT_ENABLE)
685 reg |= (0x1 << PGRP_SCHMT_SHIFT);
686 writel(reg, pad_schmt);
690 static int padgrp_set_hsm(enum pdrive_pingrp pad, enum pgrp_hsm hsm)
692 struct pmux_tri_ctlr *pmt =
693 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
694 u32 *pad_hsm = &pmt->pmt_drive[pad];
697 /* Error check pad */
698 assert(pmux_padgrp_isvalid(pad));
700 /* NONE means unspecified/do not change/use POR value */
701 if (hsm == PGRP_HSM_NONE)
704 reg = readl(pad_hsm);
705 reg &= ~(1 << PGRP_HSM_SHIFT);
706 if (hsm == PGRP_HSM_ENABLE)
707 reg |= (0x1 << PGRP_HSM_SHIFT);
708 writel(reg, pad_hsm);
713 void padctrl_config_pingroup(struct padctrl_config *config)
715 enum pdrive_pingrp pad = config->padgrp;
717 padgrp_set_drvup_slwf(pad, config->slwf);
718 padgrp_set_drvdn_slwr(pad, config->slwr);
719 padgrp_set_drvup(pad, config->drvup);
720 padgrp_set_drvdn(pad, config->drvdn);
721 padgrp_set_lpmd(pad, config->lpmd);
722 padgrp_set_schmt(pad, config->schmt);
723 padgrp_set_hsm(pad, config->hsm);
726 void padgrp_config_table(struct padctrl_config *config, int len)
730 for (i = 0; i < len; i++)
731 padctrl_config_pingroup(&config[i]);