2 * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
17 /* Tegra30 pin multiplexing functions */
21 #include <asm/arch/tegra.h>
22 #include <asm/arch/pinmux.h>
24 struct tegra_pingroup_desc {
26 enum pmux_func funcs[4];
27 enum pmux_vddio vddio;
31 #define PMUX_MUXCTL_SHIFT 0
32 #define PMUX_PULL_SHIFT 2
33 #define PMUX_TRISTATE_SHIFT 4
34 #define PMUX_TRISTATE_MASK (1 << PMUX_TRISTATE_SHIFT)
35 #define PMUX_IO_SHIFT 5
36 #define PMUX_OD_SHIFT 6
37 #define PMUX_LOCK_SHIFT 7
38 #define PMUX_IO_RESET_SHIFT 8
40 #define PGRP_HSM_SHIFT 2
41 #define PGRP_SCHMT_SHIFT 3
42 #define PGRP_LPMD_SHIFT 4
43 #define PGRP_LPMD_MASK (3 << PGRP_LPMD_SHIFT)
44 #define PGRP_DRVDN_SHIFT 12
45 #define PGRP_DRVDN_MASK (0x7F << PGRP_DRVDN_SHIFT)
46 #define PGRP_DRVUP_SHIFT 20
47 #define PGRP_DRVUP_MASK (0x7F << PGRP_DRVUP_SHIFT)
48 #define PGRP_SLWR_SHIFT 28
49 #define PGRP_SLWR_MASK (3 << PGRP_SLWR_SHIFT)
50 #define PGRP_SLWF_SHIFT 30
51 #define PGRP_SLWF_MASK (3 << PGRP_SLWF_SHIFT)
53 /* Convenient macro for defining pin group properties */
54 #define PIN(pg_name, vdd, f0, f1, f2, f3, iod) \
56 .vddio = PMUX_VDDIO_ ## vdd, \
63 .io = PMUX_PIN_ ## iod, \
66 /* Input and output pins */
67 #define PINI(pg_name, vdd, f0, f1, f2, f3) \
68 PIN(pg_name, vdd, f0, f1, f2, f3, INPUT)
69 #define PINO(pg_name, vdd, f0, f1, f2, f3) \
70 PIN(pg_name, vdd, f0, f1, f2, f3, OUTPUT)
72 const struct tegra_pingroup_desc tegra_soc_pingroups[PINGRP_COUNT] = {
73 /* NAME VDD f0 f1 f2 f3 */
74 PINI(ULPI_DATA0, BB, SPI3, HSI, UARTA, ULPI),
75 PINI(ULPI_DATA1, BB, SPI3, HSI, UARTA, ULPI),
76 PINI(ULPI_DATA2, BB, SPI3, HSI, UARTA, ULPI),
77 PINI(ULPI_DATA3, BB, SPI3, HSI, UARTA, ULPI),
78 PINI(ULPI_DATA4, BB, SPI2, HSI, UARTA, ULPI),
79 PINI(ULPI_DATA5, BB, SPI2, HSI, UARTA, ULPI),
80 PINI(ULPI_DATA6, BB, SPI2, HSI, UARTA, ULPI),
81 PINI(ULPI_DATA7, BB, SPI2, HSI, UARTA, ULPI),
82 PINI(ULPI_CLK, BB, SPI1, RSVD2, UARTD, ULPI),
83 PINI(ULPI_DIR, BB, SPI1, RSVD2, UARTD, ULPI),
84 PINI(ULPI_NXT, BB, SPI1, RSVD2, UARTD, ULPI),
85 PINI(ULPI_STP, BB, SPI1, RSVD2, UARTD, ULPI),
86 PINI(DAP3_FS, BB, I2S2, RSVD2, DISPA, DISPB),
87 PINI(DAP3_DIN, BB, I2S2, RSVD2, DISPA, DISPB),
88 PINI(DAP3_DOUT, BB, I2S2, RSVD2, DISPA, DISPB),
89 PINI(DAP3_SCLK, BB, I2S2, RSVD2, DISPA, DISPB),
90 PINI(GPIO_PV0, BB, RSVD1, RSVD2, RSVD3, RSVD4),
91 PINI(GPIO_PV1, BB, RSVD1, RSVD2, RSVD3, RSVD4),
92 PINI(SDMMC1_CLK, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
93 PINI(SDMMC1_CMD, SDMMC1, SDMMC1, RSVD2, RSVD3, UARTA),
94 PINI(SDMMC1_DAT3, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
95 PINI(SDMMC1_DAT2, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
96 PINI(SDMMC1_DAT1, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
97 PINI(SDMMC1_DAT0, SDMMC1, SDMMC1, RSVD2, UARTE, UARTA),
98 PINI(GPIO_PV2, SDMMC1, OWR, RSVD2, RSVD3, RSVD4),
99 PINI(GPIO_PV3, SDMMC1, CLK_12M_OUT, RSVD2, RSVD3, RSVD4),
100 PINI(CLK2_OUT, SDMMC1, EXTPERIPH2, RSVD2, RSVD3, RSVD4),
101 PINI(CLK2_REQ, SDMMC1, DAP, RSVD2, RSVD3, RSVD4),
102 PINO(LCD_PWR1, LCD, DISPA, DISPB, RSVD3, RSVD4),
103 PINO(LCD_PWR2, LCD, DISPA, DISPB, SPI5, HDCP),
104 PINO(LCD_SDIN, LCD, DISPA, DISPB, SPI5, RSVD4),
105 PINO(LCD_SDOUT, LCD, DISPA, DISPB, SPI5, HDCP),
106 PINO(LCD_WR_N, LCD, DISPA, DISPB, SPI5, HDCP),
107 PINO(LCD_CS0_N, LCD, DISPA, DISPB, SPI5, RSVD4),
108 PINO(LCD_DC0, LCD, DISPA, DISPB, RSVD3, RSVD4),
109 PINO(LCD_SCK, LCD, DISPA, DISPB, SPI5, HDCP),
110 PINO(LCD_PWR0, LCD, DISPA, DISPB, SPI5, HDCP),
111 PINO(LCD_PCLK, LCD, DISPA, DISPB, RSVD3, RSVD4),
112 PINO(LCD_DE, LCD, DISPA, DISPB, RSVD3, RSVD4),
113 PINO(LCD_HSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
114 PINO(LCD_VSYNC, LCD, DISPA, DISPB, RSVD3, RSVD4),
115 PINO(LCD_D0, LCD, DISPA, DISPB, RSVD3, RSVD4),
116 PINO(LCD_D1, LCD, DISPA, DISPB, RSVD3, RSVD4),
117 PINO(LCD_D2, LCD, DISPA, DISPB, RSVD3, RSVD4),
118 PINO(LCD_D3, LCD, DISPA, DISPB, RSVD3, RSVD4),
119 PINO(LCD_D4, LCD, DISPA, DISPB, RSVD3, RSVD4),
120 PINO(LCD_D5, LCD, DISPA, DISPB, RSVD3, RSVD4),
121 PINO(LCD_D6, LCD, DISPA, DISPB, RSVD3, RSVD4),
122 PINO(LCD_D7, LCD, DISPA, DISPB, RSVD3, RSVD4),
123 PINO(LCD_D8, LCD, DISPA, DISPB, RSVD3, RSVD4),
124 PINO(LCD_D9, LCD, DISPA, DISPB, RSVD3, RSVD4),
125 PINO(LCD_D10, LCD, DISPA, DISPB, RSVD3, RSVD4),
126 PINO(LCD_D11, LCD, DISPA, DISPB, RSVD3, RSVD4),
127 PINO(LCD_D12, LCD, DISPA, DISPB, RSVD3, RSVD4),
128 PINO(LCD_D13, LCD, DISPA, DISPB, RSVD3, RSVD4),
129 PINO(LCD_D14, LCD, DISPA, DISPB, RSVD3, RSVD4),
130 PINO(LCD_D15, LCD, DISPA, DISPB, RSVD3, RSVD4),
131 PINO(LCD_D16, LCD, DISPA, DISPB, RSVD3, RSVD4),
132 PINO(LCD_D17, LCD, DISPA, DISPB, RSVD3, RSVD4),
133 PINO(LCD_D18, LCD, DISPA, DISPB, RSVD3, RSVD4),
134 PINO(LCD_D19, LCD, DISPA, DISPB, RSVD3, RSVD4),
135 PINO(LCD_D20, LCD, DISPA, DISPB, RSVD3, RSVD4),
136 PINO(LCD_D21, LCD, DISPA, DISPB, RSVD3, RSVD4),
137 PINO(LCD_D22, LCD, DISPA, DISPB, RSVD3, RSVD4),
138 PINO(LCD_D23, LCD, DISPA, DISPB, RSVD3, RSVD4),
139 PINO(LCD_CS1_N, LCD, DISPA, DISPB, SPI5, RSVD4),
140 PINO(LCD_M1, LCD, DISPA, DISPB, RSVD3, RSVD4),
141 PINO(LCD_DC1, LCD, DISPA, DISPB, RSVD3, RSVD4),
142 PINI(HDMI_INT, LCD, HDMI, RSVD2, RSVD3, RSVD4),
143 PINI(DDC_SCL, LCD, I2C4, RSVD2, RSVD3, RSVD4),
144 PINI(DDC_SDA, LCD, I2C4, RSVD2, RSVD3, RSVD4),
145 PINI(CRT_HSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
146 PINI(CRT_VSYNC, LCD, CRT, RSVD2, RSVD3, RSVD4),
147 PINI(VI_D0, VI, DDR, RSVD2, VI, RSVD4),
148 PINI(VI_D1, VI, DDR, SDMMC2, VI, RSVD4),
149 PINI(VI_D2, VI, DDR, SDMMC2, VI, RSVD4),
150 PINI(VI_D3, VI, DDR, SDMMC2, VI, RSVD4),
151 PINI(VI_D4, VI, DDR, SDMMC2, VI, RSVD4),
152 PINI(VI_D5, VI, DDR, SDMMC2, VI, RSVD4),
153 PINI(VI_D6, VI, DDR, SDMMC2, VI, RSVD4),
154 PINI(VI_D7, VI, DDR, SDMMC2, VI, RSVD4),
155 PINI(VI_D8, VI, DDR, SDMMC2, VI, RSVD4),
156 PINI(VI_D9, VI, DDR, SDMMC2, VI, RSVD4),
157 PINI(VI_D10, VI, DDR, RSVD2, VI, RSVD4),
158 PINI(VI_D11, VI, DDR, RSVD2, VI, RSVD4),
159 PINI(VI_PCLK, VI, RSVD1, SDMMC2, VI, RSVD4),
160 PINI(VI_MCLK, VI, VI, VI, VI, VI),
161 PINI(VI_VSYNC, VI, DDR, RSVD2, VI, RSVD4),
162 PINI(VI_HSYNC, VI, DDR, RSVD2, VI, RSVD4),
163 PINI(UART2_RXD, UART, UARTB, SPDIF, UARTA, SPI4),
164 PINI(UART2_TXD, UART, UARTB, SPDIF, UARTA, SPI4),
165 PINI(UART2_RTS_N, UART, UARTA, UARTB, GMI, SPI4),
166 PINI(UART2_CTS_N, UART, UARTA, UARTB, GMI, SPI4),
167 PINI(UART3_TXD, UART, UARTC, RSVD2, GMI, RSVD4),
168 PINI(UART3_RXD, UART, UARTC, RSVD2, GMI, RSVD4),
169 PINI(UART3_CTS_N, UART, UARTC, RSVD2, GMI, RSVD4),
170 PINI(UART3_RTS_N, UART, UARTC, PWM0, GMI, RSVD4),
171 PINI(GPIO_PU0, UART, OWR, UARTA, GMI, RSVD4),
172 PINI(GPIO_PU1, UART, RSVD1, UARTA, GMI, RSVD4),
173 PINI(GPIO_PU2, UART, RSVD1, UARTA, GMI, RSVD4),
174 PINI(GPIO_PU3, UART, PWM0, UARTA, GMI, RSVD4),
175 PINI(GPIO_PU4, UART, PWM1, UARTA, GMI, RSVD4),
176 PINI(GPIO_PU5, UART, PWM2, UARTA, GMI, RSVD4),
177 PINI(GPIO_PU6, UART, PWM3, UARTA, GMI, RSVD4),
178 PINI(GEN1_I2C_SDA, UART, I2C1, RSVD2, RSVD3, RSVD4),
179 PINI(GEN1_I2C_SCL, UART, I2C1, RSVD2, RSVD3, RSVD4),
180 PINI(DAP4_FS, UART, I2S3, RSVD2, GMI, RSVD4),
181 PINI(DAP4_DIN, UART, I2S3, RSVD2, GMI, RSVD4),
182 PINI(DAP4_DOUT, UART, I2S3, RSVD2, GMI, RSVD4),
183 PINI(DAP4_SCLK, UART, I2S3, RSVD2, GMI, RSVD4),
184 PINI(CLK3_OUT, UART, EXTPERIPH3, RSVD2, RSVD3, RSVD4),
185 PINI(CLK3_REQ, UART, DEV3, RSVD2, RSVD3, RSVD4),
186 PINI(GMI_WP_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
187 PINI(GMI_IORDY, GMI, RSVD1, NAND, GMI, RSVD4),
188 PINI(GMI_WAIT, GMI, RSVD1, NAND, GMI, RSVD4),
189 PINI(GMI_ADV_N, GMI, RSVD1, NAND, GMI, RSVD4),
190 PINI(GMI_CLK, GMI, RSVD1, NAND, GMI, RSVD4),
191 PINI(GMI_CS0_N, GMI, RSVD1, NAND, GMI, DTV),
192 PINI(GMI_CS1_N, GMI, RSVD1, NAND, GMI, DTV),
193 PINI(GMI_CS2_N, GMI, RSVD1, NAND, GMI, RSVD4),
194 PINI(GMI_CS3_N, GMI, RSVD1, NAND, GMI, GMI_ALT),
195 PINI(GMI_CS4_N, GMI, RSVD1, NAND, GMI, RSVD4),
196 PINI(GMI_CS6_N, GMI, NAND, NAND_ALT, GMI, SATA),
197 PINI(GMI_CS7_N, GMI, NAND, NAND_ALT, GMI, GMI_ALT),
198 PINI(GMI_AD0, GMI, RSVD1, NAND, GMI, RSVD4),
199 PINI(GMI_AD1, GMI, RSVD1, NAND, GMI, RSVD4),
200 PINI(GMI_AD2, GMI, RSVD1, NAND, GMI, RSVD4),
201 PINI(GMI_AD3, GMI, RSVD1, NAND, GMI, RSVD4),
202 PINI(GMI_AD4, GMI, RSVD1, NAND, GMI, RSVD4),
203 PINI(GMI_AD5, GMI, RSVD1, NAND, GMI, RSVD4),
204 PINI(GMI_AD6, GMI, RSVD1, NAND, GMI, RSVD4),
205 PINI(GMI_AD7, GMI, RSVD1, NAND, GMI, RSVD4),
206 PINI(GMI_AD8, GMI, PWM0, NAND, GMI, RSVD4),
207 PINI(GMI_AD9, GMI, PWM1, NAND, GMI, RSVD4),
208 PINI(GMI_AD10, GMI, PWM2, NAND, GMI, RSVD4),
209 PINI(GMI_AD11, GMI, PWM3, NAND, GMI, RSVD4),
210 PINI(GMI_AD12, GMI, RSVD1, NAND, GMI, RSVD4),
211 PINI(GMI_AD13, GMI, RSVD1, NAND, GMI, RSVD4),
212 PINI(GMI_AD14, GMI, RSVD1, NAND, GMI, RSVD4),
213 PINI(GMI_AD15, GMI, RSVD1, NAND, GMI, RSVD4),
214 PINI(GMI_A16, GMI, UARTD, SPI4, GMI, GMI_ALT),
215 PINI(GMI_A17, GMI, UARTD, SPI4, GMI, DTV),
216 PINI(GMI_A18, GMI, UARTD, SPI4, GMI, DTV),
217 PINI(GMI_A19, GMI, UARTD, SPI4, GMI, RSVD4),
218 PINI(GMI_WR_N, GMI, RSVD1, NAND, GMI, RSVD4),
219 PINI(GMI_OE_N, GMI, RSVD1, NAND, GMI, RSVD4),
220 PINI(GMI_DQS, GMI, RSVD1, NAND, GMI, RSVD4),
221 PINI(GMI_RST_N, GMI, NAND, NAND_ALT, GMI, RSVD4),
222 PINI(GEN2_I2C_SCL, GMI, I2C2, HDCP, GMI, RSVD4),
223 PINI(GEN2_I2C_SDA, GMI, I2C2, HDCP, GMI, RSVD4),
224 PINI(SDMMC4_CLK, SDMMC4, RSVD1, NAND, GMI, SDMMC4),
225 PINI(SDMMC4_CMD, SDMMC4, I2C3, NAND, GMI, SDMMC4),
226 PINI(SDMMC4_DAT0, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
227 PINI(SDMMC4_DAT1, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
228 PINI(SDMMC4_DAT2, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
229 PINI(SDMMC4_DAT3, SDMMC4, UARTE, SPI3, GMI, SDMMC4),
230 PINI(SDMMC4_DAT4, SDMMC4, I2C3, I2S4, GMI, SDMMC4),
231 PINI(SDMMC4_DAT5, SDMMC4, VGP3, I2S4, GMI, SDMMC4),
232 PINI(SDMMC4_DAT6, SDMMC4, VGP4, I2S4, GMI, SDMMC4),
233 PINI(SDMMC4_DAT7, SDMMC4, VGP5, I2S4, GMI, SDMMC4),
234 PINI(SDMMC4_RST_N, SDMMC4, VGP6, RSVD2, RSVD3, SDMMC4),
235 PINI(CAM_MCLK, CAM, VI, RSVD2, VI_ALT2, SDMMC4),
236 PINI(GPIO_PCC1, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
237 PINI(GPIO_PBB0, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
238 PINI(CAM_I2C_SCL, CAM, VGP1, I2C3, RSVD3, SDMMC4),
239 PINI(CAM_I2C_SDA, CAM, VGP2, I2C3, RSVD3, SDMMC4),
240 PINI(GPIO_PBB3, CAM, VGP3, DISPA, DISPB, SDMMC4),
241 PINI(GPIO_PBB4, CAM, VGP4, DISPA, DISPB, SDMMC4),
242 PINI(GPIO_PBB5, CAM, VGP5, DISPA, DISPB, SDMMC4),
243 PINI(GPIO_PBB6, CAM, VGP6, DISPA, DISPB, SDMMC4),
244 PINI(GPIO_PBB7, CAM, I2S4, RSVD2, RSVD3, SDMMC4),
245 PINI(GPIO_PCC2, CAM, I2S4, RSVD2, RSVD3, RSVD4),
246 PINI(JTAG_RTCK, SYS, RTCK, RSVD2, RSVD3, RSVD4),
247 PINI(PWR_I2C_SCL, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
248 PINI(PWR_I2C_SDA, SYS, I2CPWR, RSVD2, RSVD3, RSVD4),
249 PINI(KB_ROW0, SYS, KBC, NAND, RSVD3, RSVD4),
250 PINI(KB_ROW1, SYS, KBC, NAND, RSVD3, RSVD4),
251 PINI(KB_ROW2, SYS, KBC, NAND, RSVD3, RSVD4),
252 PINI(KB_ROW3, SYS, KBC, NAND, RSVD3, RSVD4),
253 PINI(KB_ROW4, SYS, KBC, NAND, TRACE, RSVD4),
254 PINI(KB_ROW5, SYS, KBC, NAND, TRACE, OWR),
255 PINI(KB_ROW6, SYS, KBC, NAND, SDMMC2, MIO),
256 PINI(KB_ROW7, SYS, KBC, NAND, SDMMC2, MIO),
257 PINI(KB_ROW8, SYS, KBC, NAND, SDMMC2, MIO),
258 PINI(KB_ROW9, SYS, KBC, NAND, SDMMC2, MIO),
259 PINI(KB_ROW10, SYS, KBC, NAND, SDMMC2, MIO),
260 PINI(KB_ROW11, SYS, KBC, NAND, SDMMC2, MIO),
261 PINI(KB_ROW12, SYS, KBC, NAND, SDMMC2, MIO),
262 PINI(KB_ROW13, SYS, KBC, NAND, SDMMC2, MIO),
263 PINI(KB_ROW14, SYS, KBC, NAND, SDMMC2, MIO),
264 PINI(KB_ROW15, SYS, KBC, NAND, SDMMC2, MIO),
265 PINI(KB_COL0, SYS, KBC, NAND, TRACE, TEST),
266 PINI(KB_COL1, SYS, KBC, NAND, TRACE, TEST),
267 PINI(KB_COL2, SYS, KBC, NAND, TRACE, RSVD4),
268 PINI(KB_COL3, SYS, KBC, NAND, TRACE, RSVD4),
269 PINI(KB_COL4, SYS, KBC, NAND, TRACE, RSVD4),
270 PINI(KB_COL5, SYS, KBC, NAND, TRACE, RSVD4),
271 PINI(KB_COL6, SYS, KBC, NAND, TRACE, MIO),
272 PINI(KB_COL7, SYS, KBC, NAND, TRACE, MIO),
273 PINI(CLK_32K_OUT, SYS, BLINK, RSVD2, RSVD3, RSVD4),
274 PINI(SYS_CLK_REQ, SYS, SYSCLK, RSVD2, RSVD3, RSVD4),
275 PINI(CORE_PWR_REQ, SYS, CORE_PWR_REQ, RSVD2, RSVD3, RSVD4),
276 PINI(CPU_PWR_REQ, SYS, CPU_PWR_REQ, RSVD2, RSVD3, RSVD4),
277 PINI(PWR_INT_N, SYS, PWR_INT_N, RSVD2, RSVD3, RSVD4),
278 PINI(CLK_32K_IN, SYS, CLK_32K_IN, RSVD2, RSVD3, RSVD4),
279 PINI(OWR, SYS, OWR, CEC, RSVD3, RSVD4),
280 PINI(DAP1_FS, AUDIO, I2S0, HDA, GMI, SDMMC2),
281 PINI(DAP1_DIN, AUDIO, I2S0, HDA, GMI, SDMMC2),
282 PINI(DAP1_DOUT, AUDIO, I2S0, HDA, GMI, SDMMC2),
283 PINI(DAP1_SCLK, AUDIO, I2S0, HDA, GMI, SDMMC2),
284 PINI(CLK1_REQ, AUDIO, DAP, HDA, RSVD3, RSVD4),
285 PINI(CLK1_OUT, AUDIO, EXTPERIPH1, RSVD2, RSVD3, RSVD4),
286 PINI(SPDIF_IN, AUDIO, SPDIF, HDA, I2C1, SDMMC2),
287 PINI(SPDIF_OUT, AUDIO, SPDIF, RSVD2, I2C1, SDMMC2),
288 PINI(DAP2_FS, AUDIO, I2S1, HDA, RSVD3, GMI),
289 PINI(DAP2_DIN, AUDIO, I2S1, HDA, RSVD3, GMI),
290 PINI(DAP2_DOUT, AUDIO, I2S1, HDA, RSVD3, GMI),
291 PINI(DAP2_SCLK, AUDIO, I2S1, HDA, RSVD3, GMI),
292 PINI(SPI2_MOSI, AUDIO, SPI6, SPI2, GMI, GMI),
293 PINI(SPI2_MISO, AUDIO, SPI6, SPI2, GMI, GMI),
294 PINI(SPI2_CS0_N, AUDIO, SPI6, SPI2, GMI, GMI),
295 PINI(SPI2_SCK, AUDIO, SPI6, SPI2, GMI, GMI),
296 PINI(SPI1_MOSI, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
297 PINI(SPI1_SCK, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
298 PINI(SPI1_CS0_N, AUDIO, SPI2, SPI1, SPI2_ALT, GMI),
299 PINI(SPI1_MISO, AUDIO, SPI3, SPI1, SPI2_ALT, RSVD4),
300 PINI(SPI2_CS1_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
301 PINI(SPI2_CS2_N, AUDIO, SPI3, SPI2, SPI2_ALT, I2C1),
302 PINI(SDMMC3_CLK, SDMMC3, UARTA, PWM2, SDMMC3, SPI3),
303 PINI(SDMMC3_CMD, SDMMC3, UARTA, PWM3, SDMMC3, SPI2),
304 PINI(SDMMC3_DAT0, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
305 PINI(SDMMC3_DAT1, SDMMC3, RSVD1, RSVD2, SDMMC3, SPI3),
306 PINI(SDMMC3_DAT2, SDMMC3, RSVD1, PWM1, SDMMC3, SPI3),
307 PINI(SDMMC3_DAT3, SDMMC3, RSVD1, PWM0, SDMMC3, SPI3),
308 PINI(SDMMC3_DAT4, SDMMC3, PWM1, SPI4, SDMMC3, SPI2),
309 PINI(SDMMC3_DAT5, SDMMC3, PWM0, SPI4, SDMMC3, SPI2),
310 PINI(SDMMC3_DAT6, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
311 PINI(SDMMC3_DAT7, SDMMC3, SPDIF, SPI4, SDMMC3, SPI2),
312 PINI(PEX_L0_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
313 PINI(PEX_L0_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
314 PINI(PEX_L0_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
315 PINI(PEX_WAKE_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
316 PINI(PEX_L1_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
317 PINI(PEX_L1_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
318 PINI(PEX_L1_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
319 PINI(PEX_L2_PRSNT_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
320 PINI(PEX_L2_RST_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
321 PINI(PEX_L2_CLKREQ_N, PEXCTL, PCIE, HDA, RSVD3, RSVD4),
322 PINI(HDMI_CEC, SYS, CEC, RSVD2, RSVD3, RSVD4),
325 void pinmux_set_tristate(enum pmux_pingrp pin, int enable)
327 struct pmux_tri_ctlr *pmt =
328 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
329 u32 *tri = &pmt->pmt_ctl[pin];
332 /* Error check on pin */
333 assert(pmux_pingrp_isvalid(pin));
337 reg |= PMUX_TRISTATE_MASK;
339 reg &= ~PMUX_TRISTATE_MASK;
343 void pinmux_tristate_enable(enum pmux_pingrp pin)
345 pinmux_set_tristate(pin, 1);
348 void pinmux_tristate_disable(enum pmux_pingrp pin)
350 pinmux_set_tristate(pin, 0);
353 void pinmux_set_pullupdown(enum pmux_pingrp pin, enum pmux_pull pupd)
355 struct pmux_tri_ctlr *pmt =
356 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
357 u32 *pull = &pmt->pmt_ctl[pin];
360 /* Error check on pin and pupd */
361 assert(pmux_pingrp_isvalid(pin));
362 assert(pmux_pin_pupd_isvalid(pupd));
365 reg &= ~(0x3 << PMUX_PULL_SHIFT);
366 reg |= (pupd << PMUX_PULL_SHIFT);
370 void pinmux_set_func(enum pmux_pingrp pin, enum pmux_func func)
372 struct pmux_tri_ctlr *pmt =
373 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
374 u32 *muxctl = &pmt->pmt_ctl[pin];
378 /* Error check on pin and func */
379 assert(pmux_pingrp_isvalid(pin));
380 assert(pmux_func_isvalid(func));
382 if (func & PMUX_FUNC_RSVD1) {
385 /* Search for the appropriate function */
386 for (i = 0; i < 4; i++) {
387 if (tegra_soc_pingroups[pin].funcs[i] == func) {
396 reg &= ~(0x3 << PMUX_MUXCTL_SHIFT);
397 reg |= (mux << PMUX_MUXCTL_SHIFT);
402 void pinmux_set_io(enum pmux_pingrp pin, enum pmux_pin_io io)
404 struct pmux_tri_ctlr *pmt =
405 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
406 u32 *pin_io = &pmt->pmt_ctl[pin];
409 /* Error check on pin and io */
410 assert(pmux_pingrp_isvalid(pin));
411 assert(pmux_pin_io_isvalid(io));
414 reg &= ~(0x1 << PMUX_IO_SHIFT);
415 reg |= (io & 0x1) << PMUX_IO_SHIFT;
419 static int pinmux_set_lock(enum pmux_pingrp pin, enum pmux_pin_lock lock)
421 struct pmux_tri_ctlr *pmt =
422 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
423 u32 *pin_lock = &pmt->pmt_ctl[pin];
426 /* Error check on pin and lock */
427 assert(pmux_pingrp_isvalid(pin));
428 assert(pmux_pin_lock_isvalid(lock));
430 if (lock == PMUX_PIN_LOCK_DEFAULT)
433 reg = readl(pin_lock);
434 reg &= ~(0x1 << PMUX_LOCK_SHIFT);
435 if (lock == PMUX_PIN_LOCK_ENABLE)
436 reg |= (0x1 << PMUX_LOCK_SHIFT);
438 /* lock == DISABLE, which isn't possible */
439 printf("%s: Warning: lock == %d, DISABLE is not allowed!\n",
442 writel(reg, pin_lock);
447 static int pinmux_set_od(enum pmux_pingrp pin, enum pmux_pin_od od)
449 struct pmux_tri_ctlr *pmt =
450 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
451 u32 *pin_od = &pmt->pmt_ctl[pin];
454 /* Error check on pin and od */
455 assert(pmux_pingrp_isvalid(pin));
456 assert(pmux_pin_od_isvalid(od));
458 if (od == PMUX_PIN_OD_DEFAULT)
462 reg &= ~(0x1 << PMUX_OD_SHIFT);
463 if (od == PMUX_PIN_OD_ENABLE)
464 reg |= (0x1 << PMUX_OD_SHIFT);
470 static int pinmux_set_ioreset(enum pmux_pingrp pin,
471 enum pmux_pin_ioreset ioreset)
473 struct pmux_tri_ctlr *pmt =
474 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
475 u32 *pin_ioreset = &pmt->pmt_ctl[pin];
478 /* Error check on pin and ioreset */
479 assert(pmux_pingrp_isvalid(pin));
480 assert(pmux_pin_ioreset_isvalid(ioreset));
482 if (ioreset == PMUX_PIN_IO_RESET_DEFAULT)
485 reg = readl(pin_ioreset);
486 reg &= ~(0x1 << PMUX_IO_RESET_SHIFT);
487 if (ioreset == PMUX_PIN_IO_RESET_ENABLE)
488 reg |= (0x1 << PMUX_IO_RESET_SHIFT);
489 writel(reg, pin_ioreset);
494 void pinmux_config_pingroup(struct pingroup_config *config)
496 enum pmux_pingrp pin = config->pingroup;
498 pinmux_set_func(pin, config->func);
499 pinmux_set_pullupdown(pin, config->pull);
500 pinmux_set_tristate(pin, config->tristate);
501 pinmux_set_io(pin, config->io);
502 pinmux_set_lock(pin, config->lock);
503 pinmux_set_od(pin, config->od);
504 pinmux_set_ioreset(pin, config->ioreset);
507 void pinmux_config_table(struct pingroup_config *config, int len)
511 for (i = 0; i < len; i++)
512 pinmux_config_pingroup(&config[i]);
515 static int padgrp_set_drvup_slwf(enum pdrive_pingrp pad,
518 struct pmux_tri_ctlr *pmt =
519 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
520 u32 *pad_slwf = &pmt->pmt_drive[pad];
523 /* Error check on pad and slwf */
524 assert(pmux_padgrp_isvalid(pad));
525 assert(pmux_pad_slw_isvalid(slwf));
527 /* NONE means unspecified/do not change/use POR value */
528 if (slwf == PGRP_SLWF_NONE)
531 reg = readl(pad_slwf);
532 reg &= ~PGRP_SLWF_MASK;
533 reg |= (slwf << PGRP_SLWF_SHIFT);
534 writel(reg, pad_slwf);
539 static int padgrp_set_drvdn_slwr(enum pdrive_pingrp pad, int slwr)
541 struct pmux_tri_ctlr *pmt =
542 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
543 u32 *pad_slwr = &pmt->pmt_drive[pad];
546 /* Error check on pad and slwr */
547 assert(pmux_padgrp_isvalid(pad));
548 assert(pmux_pad_slw_isvalid(slwr));
550 /* NONE means unspecified/do not change/use POR value */
551 if (slwr == PGRP_SLWR_NONE)
554 reg = readl(pad_slwr);
555 reg &= ~PGRP_SLWR_MASK;
556 reg |= (slwr << PGRP_SLWR_SHIFT);
557 writel(reg, pad_slwr);
562 static int padgrp_set_drvup(enum pdrive_pingrp pad, int drvup)
564 struct pmux_tri_ctlr *pmt =
565 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
566 u32 *pad_drvup = &pmt->pmt_drive[pad];
569 /* Error check on pad and drvup */
570 assert(pmux_padgrp_isvalid(pad));
571 assert(pmux_pad_drv_isvalid(drvup));
573 /* NONE means unspecified/do not change/use POR value */
574 if (drvup == PGRP_DRVUP_NONE)
577 reg = readl(pad_drvup);
578 reg &= ~PGRP_DRVUP_MASK;
579 reg |= (drvup << PGRP_DRVUP_SHIFT);
580 writel(reg, pad_drvup);
585 static int padgrp_set_drvdn(enum pdrive_pingrp pad, int drvdn)
587 struct pmux_tri_ctlr *pmt =
588 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
589 u32 *pad_drvdn = &pmt->pmt_drive[pad];
592 /* Error check on pad and drvdn */
593 assert(pmux_padgrp_isvalid(pad));
594 assert(pmux_pad_drv_isvalid(drvdn));
596 /* NONE means unspecified/do not change/use POR value */
597 if (drvdn == PGRP_DRVDN_NONE)
600 reg = readl(pad_drvdn);
601 reg &= ~PGRP_DRVDN_MASK;
602 reg |= (drvdn << PGRP_DRVDN_SHIFT);
603 writel(reg, pad_drvdn);
608 static int padgrp_set_lpmd(enum pdrive_pingrp pad, enum pgrp_lpmd lpmd)
610 struct pmux_tri_ctlr *pmt =
611 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
612 u32 *pad_lpmd = &pmt->pmt_drive[pad];
615 /* Error check pad and lpmd value */
616 assert(pmux_padgrp_isvalid(pad));
617 assert(pmux_pad_lpmd_isvalid(lpmd));
619 /* NONE means unspecified/do not change/use POR value */
620 if (lpmd == PGRP_LPMD_NONE)
623 reg = readl(pad_lpmd);
624 reg &= ~PGRP_LPMD_MASK;
625 reg |= (lpmd << PGRP_LPMD_SHIFT);
626 writel(reg, pad_lpmd);
631 static int padgrp_set_schmt(enum pdrive_pingrp pad, enum pgrp_schmt schmt)
633 struct pmux_tri_ctlr *pmt =
634 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
635 u32 *pad_schmt = &pmt->pmt_drive[pad];
638 /* Error check pad */
639 assert(pmux_padgrp_isvalid(pad));
641 reg = readl(pad_schmt);
642 reg &= ~(1 << PGRP_SCHMT_SHIFT);
643 if (schmt == PGRP_SCHMT_ENABLE)
644 reg |= (0x1 << PGRP_SCHMT_SHIFT);
645 writel(reg, pad_schmt);
649 static int padgrp_set_hsm(enum pdrive_pingrp pad,
652 struct pmux_tri_ctlr *pmt =
653 (struct pmux_tri_ctlr *)NV_PA_APB_MISC_BASE;
654 u32 *pad_hsm = &pmt->pmt_drive[pad];
657 /* Error check pad */
658 assert(pmux_padgrp_isvalid(pad));
660 reg = readl(pad_hsm);
661 reg &= ~(1 << PGRP_HSM_SHIFT);
662 if (hsm == PGRP_HSM_ENABLE)
663 reg |= (0x1 << PGRP_HSM_SHIFT);
664 writel(reg, pad_hsm);
669 void padctrl_config_pingroup(struct padctrl_config *config)
671 enum pdrive_pingrp pad = config->padgrp;
673 padgrp_set_drvup_slwf(pad, config->slwf);
674 padgrp_set_drvdn_slwr(pad, config->slwr);
675 padgrp_set_drvup(pad, config->drvup);
676 padgrp_set_drvdn(pad, config->drvdn);
677 padgrp_set_lpmd(pad, config->lpmd);
678 padgrp_set_schmt(pad, config->schmt);
679 padgrp_set_hsm(pad, config->hsm);
682 void padgrp_config_table(struct padctrl_config *config, int len)
686 for (i = 0; i < len; i++)
687 padctrl_config_pingroup(&config[i]);