arch/arm/dts/exynos5420-peach-pit.dts

   1 /*
   2  * SAMSUNG/GOOGLE Peach-Pit board device tree source
   3  *
   4  * Copyright (c) 2013 Samsung Electronics Co., Ltd.
   5  *              http://www.samsung.com
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 /dts-v1/;
  11 /include/ "exynos54xx.dtsi"
  12
  13 / {
  14         model = "Samsung/Google Peach Pit board based on Exynos5420";
  15
  16         compatible = "google,pit-rev#", "google,pit",
  17                 "google,peach", "samsung,exynos5420", "samsung,exynos5";
  18
  19         config {
  20                 google,bad-wake-gpios = <&gpio 0x56 0>; /* gpx0-6 */
  21                 hwid = "PIT TEST A-A 7848";
  22                 lazy-init = <1>;
  23         };
  24
  25         aliases {
  26                 serial0 = "/serial@12C30000";
  27                 console = "/serial@12C30000";
  28                 pmic = "/i2c@12ca0000";
  29         };
  30
  31         dmc {
  32                 mem-manuf = "samsung";
  33                 mem-type = "ddr3";
  34                 clock-frequency = <800000000>;
  35                 arm-frequency = <1700000000>;
  36         };
  37
  38         tmu@10060000 {
  39                 samsung,min-temp        = <25>;
  40                 samsung,max-temp        = <125>;
  41                 samsung,start-warning   = <95>;
  42                 samsung,start-tripping  = <105>;
  43                 samsung,hw-tripping     = <110>;
  44                 samsung,efuse-min-value = <40>;
  45                 samsung,efuse-value     = <55>;
  46                 samsung,efuse-max-value = <100>;
  47                 samsung,slope           = <274761730>;
  48                 samsung,dc-value        = <25>;
  49         };
  50
  51         /* MAX77802 is on i2c bus 4 */
  52         i2c@12ca0000 {
  53                 clock-frequency = <400000>;
  54                 power-regulator@9 {
  55                         compatible = "maxim,max77802-pmic";
  56                         reg = <0x9>;
  57                 };
  58         };
  59
  60         i2c@12cd0000 { /* i2c7 */
  61                 clock-frequency = <100000>;
  62                soundcodec@20 {
  63                       reg = <0x20>;
  64                       compatible = "maxim,max98090-codec";
  65                };
  66
  67                 edp-lvds-bridge@48 {
  68                         compatible = "parade,ps8625";
  69                         reg = <0x48>;
  70                 };
  71         };
  72
  73         sound@3830000 {
  74                 samsung,codec-type = "max98090";
  75         };
  76
  77         i2c@12e10000 { /* i2c9 */
  78                 clock-frequency = <400000>;
  79                 tpm@20 {
  80                         compatible = "infineon,slb9645-tpm";
  81                         reg = <0x20>;
  82                 };
  83         };
  84
  85         spi@12d30000 { /* spi1 */
  86                 spi-max-frequency = <50000000>;
  87                 firmware_storage_spi: flash@0 {
  88                         reg = <0>;
  89
  90                         /*
  91                          * A region for the kernel to store a panic event
  92                          * which the firmware will add to the log.
  93                         */
  94                         elog-panic-event-offset = <0x01e00000 0x100000>;
  95
  96                         elog-shrink-size = <0x400>;
  97                         elog-full-threshold = <0xc00>;
  98                 };
  99         };
 100
 101         spi@12d40000 { /* spi2 */
 102                 spi-max-frequency = <4000000>;
 103                 spi-deactivate-delay = <200>;
 104                 cros-ec@0 {
 105                         reg = <0>;
 106                         compatible = "google,cros-ec";
 107                         spi-half-duplex;
 108                         spi-max-timeout-ms = <1100>;
 109                         spi-frame-header = <0xec>;
 110                         ec-interrupt = <&gpio 93 1>; /* GPX1_5 */
 111
 112                         /*
 113                          * This describes the flash memory within the EC. Note
 114                          * that the STM32L flash erases to 0, not 0xff.
 115                          */
 116                         #address-cells = <1>;
 117                         #size-cells = <1>;
 118                         flash@8000000 {
 119                                 reg = <0x08000000 0x20000>;
 120                                 erase-value = <0>;
 121                         };
 122                 };
 123         };
 124
 125         xhci@12000000 {
 126                 samsung,vbus-gpio = <&gpio 0x40 0>; /* H00 */
 127         };
 128
 129         xhci@12400000 {
 130                 samsung,vbus-gpio = <&gpio 0x41 0>; /* H01 */
 131         };
 132
 133         fimd@14400000 {
 134                 samsung,vl-freq = <60>;
 135                 samsung,vl-col = <1366>;
 136                 samsung,vl-row = <768>;
 137                 samsung,vl-width = <1366>;
 138                 samsung,vl-height = <768>;
 139
 140                 samsung,vl-clkp;
 141                 samsung,vl-dp;
 142                 samsung,vl-bpix = <4>;
 143
 144                 samsung,vl-hspw = <32>;
 145                 samsung,vl-hbpd = <40>;
 146                 samsung,vl-hfpd = <40>;
 147                 samsung,vl-vspw = <6>;
 148                 samsung,vl-vbpd = <10>;
 149                 samsung,vl-vfpd = <12>;
 150                 samsung,vl-cmd-allow-len = <0xf>;
 151
 152                 samsung,winid = <3>;
 153                 samsung,interface-mode = <1>;
 154                 samsung,dp-enabled = <1>;
 155                 samsung,dual-lcd-enabled = <0>;
 156         };
 157 };