arch/arm/dts/sun6i-a31.dtsi

   1 /*
   2  * Copyright 2013 Maxime Ripard
   3  *
   4  * Maxime Ripard <maxime.ripard@free-electrons.com>
   5  *
   6  * This file is dual-licensed: you can use it either under the terms
   7  * of the GPL or the X11 license, at your option. Note that this dual
   8  * licensing only applies to this file, and not this project as a
   9  * whole.
  10  *
  11  *  a) This file is free software; you can redistribute it and/or
  12  *     modify it under the terms of the GNU General Public License as
  13  *     published by the Free Software Foundation; either version 2 of the
  14  *     License, or (at your option) any later version.
  15  *
  16  *     This file is distributed in the hope that it will be useful,
  17  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
  18  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  19  *     GNU General Public License for more details.
  20  *
  21  * Or, alternatively,
  22  *
  23  *  b) Permission is hereby granted, free of charge, to any person
  24  *     obtaining a copy of this software and associated documentation
  25  *     files (the "Software"), to deal in the Software without
  26  *     restriction, including without limitation the rights to use,
  27  *     copy, modify, merge, publish, distribute, sublicense, and/or
  28  *     sell copies of the Software, and to permit persons to whom the
  29  *     Software is furnished to do so, subject to the following
  30  *     conditions:
  31  *
  32  *     The above copyright notice and this permission notice shall be
  33  *     included in all copies or substantial portions of the Software.
  34  *
  35  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  36  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
  37  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  38  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
  39  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
  40  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  41  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  42  *     OTHER DEALINGS IN THE SOFTWARE.
  43  */
  44
  45 #include "skeleton.dtsi"
  46
  47 #include <dt-bindings/interrupt-controller/arm-gic.h>
  48 #include <dt-bindings/thermal/thermal.h>
  49
  50 #include <dt-bindings/pinctrl/sun4i-a10.h>
  51
  52 / {
  53         interrupt-parent = <&gic>;
  54
  55         aliases {
  56                 ethernet0 = &gmac;
  57         };
  58
  59         chosen {
  60                 #address-cells = <1>;
  61                 #size-cells = <1>;
  62                 ranges;
  63
  64                 framebuffer@0 {
  65                         compatible = "allwinner,simple-framebuffer",
  66                                      "simple-framebuffer";
  67                         allwinner,pipeline = "de_be0-lcd0-hdmi";
  68                         clocks = <&pll6 0>;
  69                         status = "disabled";
  70                 };
  71
  72                 framebuffer@1 {
  73                         compatible = "allwinner,simple-framebuffer",
  74                                      "simple-framebuffer";
  75                         allwinner,pipeline = "de_be0-lcd0";
  76                         clocks = <&pll6 0>;
  77                         status = "disabled";
  78                 };
  79         };
  80
  81         timer {
  82                 compatible = "arm,armv7-timer";
  83                 interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  84                              <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  85                              <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
  86                              <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
  87                 clock-frequency = <24000000>;
  88                 arm,cpu-registers-not-fw-configured;
  89         };
  90
  91         cpus {
  92                 enable-method = "allwinner,sun6i-a31";
  93                 #address-cells = <1>;
  94                 #size-cells = <0>;
  95
  96                 cpu0: cpu@0 {
  97                         compatible = "arm,cortex-a7";
  98                         device_type = "cpu";
  99                         reg = <0>;
 100                         clocks = <&cpu>;
 101                         clock-latency = <244144>; /* 8 32k periods */
 102                         operating-points = <
 103                                 /* kHz    uV */
 104                                 1008000 1200000
 105                                 864000  1200000
 106                                 720000  1100000
 107                                 480000  1000000
 108                                 >;
 109                         #cooling-cells = <2>;
 110                         cooling-min-level = <0>;
 111                         cooling-max-level = <3>;
 112                 };
 113
 114                 cpu@1 {
 115                         compatible = "arm,cortex-a7";
 116                         device_type = "cpu";
 117                         reg = <1>;
 118                 };
 119
 120                 cpu@2 {
 121                         compatible = "arm,cortex-a7";
 122                         device_type = "cpu";
 123                         reg = <2>;
 124                 };
 125
 126                 cpu@3 {
 127                         compatible = "arm,cortex-a7";
 128                         device_type = "cpu";
 129                         reg = <3>;
 130                 };
 131         };
 132
 133         thermal-zones {
 134                 cpu_thermal {
 135                         /* milliseconds */
 136                         polling-delay-passive = <250>;
 137                         polling-delay = <1000>;
 138                         thermal-sensors = <&rtp>;
 139
 140                         cooling-maps {
 141                                 map0 {
 142                                         trip = <&cpu_alert0>;
 143                                         cooling-device = <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
 144                                 };
 145                         };
 146
 147                         trips {
 148                                 cpu_alert0: cpu_alert0 {
 149                                         /* milliCelsius */
 150                                         temperature = <70000>;
 151                                         hysteresis = <2000>;
 152                                         type = "passive";
 153                                 };
 154
 155                                 cpu_crit: cpu_crit {
 156                                         /* milliCelsius */
 157                                         temperature = <100000>;
 158                                         hysteresis = <2000>;
 159                                         type = "critical";
 160                                 };
 161                         };
 162                 };
 163         };
 164
 165         memory {
 166                 reg = <0x40000000 0x80000000>;
 167         };
 168
 169         pmu {
 170                 compatible = "arm,cortex-a7-pmu", "arm,cortex-a15-pmu";
 171                 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
 172                              <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>,
 173                              <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>,
 174                              <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
 175         };
 176
 177         clocks {
 178                 #address-cells = <1>;
 179                 #size-cells = <1>;
 180                 ranges;
 181
 182                 osc24M: osc24M {
 183                         #clock-cells = <0>;
 184                         compatible = "fixed-clock";
 185                         clock-frequency = <24000000>;
 186                 };
 187
 188                 osc32k: clk@0 {
 189                         #clock-cells = <0>;
 190                         compatible = "fixed-clock";
 191                         clock-frequency = <32768>;
 192                         clock-output-names = "osc32k";
 193                 };
 194
 195                 pll1: clk@01c20000 {
 196                         #clock-cells = <0>;
 197                         compatible = "allwinner,sun6i-a31-pll1-clk";
 198                         reg = <0x01c20000 0x4>;
 199                         clocks = <&osc24M>;
 200                         clock-output-names = "pll1";
 201                 };
 202
 203                 pll6: clk@01c20028 {
 204                         #clock-cells = <1>;
 205                         compatible = "allwinner,sun6i-a31-pll6-clk";
 206                         reg = <0x01c20028 0x4>;
 207                         clocks = <&osc24M>;
 208                         clock-output-names = "pll6", "pll6x2";
 209                 };
 210
 211                 cpu: cpu@01c20050 {
 212                         #clock-cells = <0>;
 213                         compatible = "allwinner,sun4i-a10-cpu-clk";
 214                         reg = <0x01c20050 0x4>;
 215
 216                         /*
 217                          * PLL1 is listed twice here.
 218                          * While it looks suspicious, it's actually documented
 219                          * that way both in the datasheet and in the code from
 220                          * Allwinner.
 221                          */
 222                         clocks = <&osc32k>, <&osc24M>, <&pll1>, <&pll1>;
 223                         clock-output-names = "cpu";
 224                 };
 225
 226                 axi: axi@01c20050 {
 227                         #clock-cells = <0>;
 228                         compatible = "allwinner,sun4i-a10-axi-clk";
 229                         reg = <0x01c20050 0x4>;
 230                         clocks = <&cpu>;
 231                         clock-output-names = "axi";
 232                 };
 233
 234                 ahb1: ahb1@01c20054 {
 235                         #clock-cells = <0>;
 236                         compatible = "allwinner,sun6i-a31-ahb1-clk";
 237                         reg = <0x01c20054 0x4>;
 238                         clocks = <&osc32k>, <&osc24M>, <&axi>, <&pll6 0>;
 239                         clock-output-names = "ahb1";
 240
 241                         /*
 242                          * Clock AHB1 from PLL6, instead of CPU/AXI which
 243                          * has rate changes due to cpufreq. Also the DMA
 244                          * controller requires AHB1 clocked from PLL6.
 245                          */
 246                         assigned-clocks = <&ahb1>;
 247                         assigned-clock-parents = <&pll6 0>;
 248                 };
 249
 250                 ahb1_gates: clk@01c20060 {
 251                         #clock-cells = <1>;
 252                         compatible = "allwinner,sun6i-a31-ahb1-gates-clk";
 253                         reg = <0x01c20060 0x8>;
 254                         clocks = <&ahb1>;
 255                         clock-output-names = "ahb1_mipidsi", "ahb1_ss",
 256                                         "ahb1_dma", "ahb1_mmc0", "ahb1_mmc1",
 257                                         "ahb1_mmc2", "ahb1_mmc3", "ahb1_nand1",
 258                                         "ahb1_nand0", "ahb1_sdram",
 259                                         "ahb1_gmac", "ahb1_ts", "ahb1_hstimer",
 260                                         "ahb1_spi0", "ahb1_spi1", "ahb1_spi2",
 261                                         "ahb1_spi3", "ahb1_otg", "ahb1_ehci0",
 262                                         "ahb1_ehci1", "ahb1_ohci0",
 263                                         "ahb1_ohci1", "ahb1_ohci2", "ahb1_ve",
 264                                         "ahb1_lcd0", "ahb1_lcd1", "ahb1_csi",
 265                                         "ahb1_hdmi", "ahb1_de0", "ahb1_de1",
 266                                         "ahb1_fe0", "ahb1_fe1", "ahb1_mp",
 267                                         "ahb1_gpu", "ahb1_deu0", "ahb1_deu1",
 268                                         "ahb1_drc0", "ahb1_drc1";
 269                 };
 270
 271                 apb1: apb1@01c20054 {
 272                         #clock-cells = <0>;
 273                         compatible = "allwinner,sun4i-a10-apb0-clk";
 274                         reg = <0x01c20054 0x4>;
 275                         clocks = <&ahb1>;
 276                         clock-output-names = "apb1";
 277                 };
 278
 279                 apb1_gates: clk@01c20068 {
 280                         #clock-cells = <1>;
 281                         compatible = "allwinner,sun6i-a31-apb1-gates-clk";
 282                         reg = <0x01c20068 0x4>;
 283                         clocks = <&apb1>;
 284                         clock-output-names = "apb1_codec", "apb1_digital_mic",
 285                                         "apb1_pio", "apb1_daudio0",
 286                                         "apb1_daudio1";
 287                 };
 288
 289                 apb2: clk@01c20058 {
 290                         #clock-cells = <0>;
 291                         compatible = "allwinner,sun4i-a10-apb1-clk";
 292                         reg = <0x01c20058 0x4>;
 293                         clocks = <&osc32k>, <&osc24M>, <&pll6 0>, <&pll6 0>;
 294                         clock-output-names = "apb2";
 295                 };
 296
 297                 apb2_gates: clk@01c2006c {
 298                         #clock-cells = <1>;
 299                         compatible = "allwinner,sun6i-a31-apb2-gates-clk";
 300                         reg = <0x01c2006c 0x4>;
 301                         clocks = <&apb2>;
 302                         clock-output-names = "apb2_i2c0", "apb2_i2c1",
 303                                              "apb2_i2c2", "apb2_i2c3",
 304                                              "apb2_uart0", "apb2_uart1",
 305                                              "apb2_uart2", "apb2_uart3",
 306                                              "apb2_uart4", "apb2_uart5";
 307                 };
 308
 309                 mmc0_clk: clk@01c20088 {
 310                         #clock-cells = <1>;
 311                         compatible = "allwinner,sun4i-a10-mmc-clk";
 312                         reg = <0x01c20088 0x4>;
 313                         clocks = <&osc24M>, <&pll6 0>;
 314                         clock-output-names = "mmc0",
 315                                              "mmc0_output",
 316                                              "mmc0_sample";
 317                 };
 318
 319                 mmc1_clk: clk@01c2008c {
 320                         #clock-cells = <1>;
 321                         compatible = "allwinner,sun4i-a10-mmc-clk";
 322                         reg = <0x01c2008c 0x4>;
 323                         clocks = <&osc24M>, <&pll6 0>;
 324                         clock-output-names = "mmc1",
 325                                              "mmc1_output",
 326                                              "mmc1_sample";
 327                 };
 328
 329                 mmc2_clk: clk@01c20090 {
 330                         #clock-cells = <1>;
 331                         compatible = "allwinner,sun4i-a10-mmc-clk";
 332                         reg = <0x01c20090 0x4>;
 333                         clocks = <&osc24M>, <&pll6 0>;
 334                         clock-output-names = "mmc2",
 335                                              "mmc2_output",
 336                                              "mmc2_sample";
 337                 };
 338
 339                 mmc3_clk: clk@01c20094 {
 340                         #clock-cells = <1>;
 341                         compatible = "allwinner,sun4i-a10-mmc-clk";
 342                         reg = <0x01c20094 0x4>;
 343                         clocks = <&osc24M>, <&pll6 0>;
 344                         clock-output-names = "mmc3",
 345                                              "mmc3_output",
 346                                              "mmc3_sample";
 347                 };
 348
 349                 spi0_clk: clk@01c200a0 {
 350                         #clock-cells = <0>;
 351                         compatible = "allwinner,sun4i-a10-mod0-clk";
 352                         reg = <0x01c200a0 0x4>;
 353                         clocks = <&osc24M>, <&pll6 0>;
 354                         clock-output-names = "spi0";
 355                 };
 356
 357                 spi1_clk: clk@01c200a4 {
 358                         #clock-cells = <0>;
 359                         compatible = "allwinner,sun4i-a10-mod0-clk";
 360                         reg = <0x01c200a4 0x4>;
 361                         clocks = <&osc24M>, <&pll6 0>;
 362                         clock-output-names = "spi1";
 363                 };
 364
 365                 spi2_clk: clk@01c200a8 {
 366                         #clock-cells = <0>;
 367                         compatible = "allwinner,sun4i-a10-mod0-clk";
 368                         reg = <0x01c200a8 0x4>;
 369                         clocks = <&osc24M>, <&pll6 0>;
 370                         clock-output-names = "spi2";
 371                 };
 372
 373                 spi3_clk: clk@01c200ac {
 374                         #clock-cells = <0>;
 375                         compatible = "allwinner,sun4i-a10-mod0-clk";
 376                         reg = <0x01c200ac 0x4>;
 377                         clocks = <&osc24M>, <&pll6 0>;
 378                         clock-output-names = "spi3";
 379                 };
 380
 381                 usb_clk: clk@01c200cc {
 382                         #clock-cells = <1>;
 383                         #reset-cells = <1>;
 384                         compatible = "allwinner,sun6i-a31-usb-clk";
 385                         reg = <0x01c200cc 0x4>;
 386                         clocks = <&osc24M>;
 387                         clock-output-names = "usb_phy0", "usb_phy1", "usb_phy2",
 388                                              "usb_ohci0", "usb_ohci1",
 389                                              "usb_ohci2";
 390                 };
 391
 392                 /*
 393                  * The following two are dummy clocks, placeholders
 394                  * used in the gmac_tx clock. The gmac driver will
 395                  * choose one parent depending on the PHY interface
 396                  * mode, using clk_set_rate auto-reparenting.
 397                  *
 398                  * The actual TX clock rate is not controlled by the
 399                  * gmac_tx clock.
 400                  */
 401                 mii_phy_tx_clk: clk@1 {
 402                         #clock-cells = <0>;
 403                         compatible = "fixed-clock";
 404                         clock-frequency = <25000000>;
 405                         clock-output-names = "mii_phy_tx";
 406                 };
 407
 408                 gmac_int_tx_clk: clk@2 {
 409                         #clock-cells = <0>;
 410                         compatible = "fixed-clock";
 411                         clock-frequency = <125000000>;
 412                         clock-output-names = "gmac_int_tx";
 413                 };
 414
 415                 gmac_tx_clk: clk@01c200d0 {
 416                         #clock-cells = <0>;
 417                         compatible = "allwinner,sun7i-a20-gmac-clk";
 418                         reg = <0x01c200d0 0x4>;
 419                         clocks = <&mii_phy_tx_clk>, <&gmac_int_tx_clk>;
 420                         clock-output-names = "gmac_tx";
 421                 };
 422         };
 423
 424         soc@01c00000 {
 425                 compatible = "simple-bus";
 426                 #address-cells = <1>;
 427                 #size-cells = <1>;
 428                 ranges;
 429
 430                 dma: dma-controller@01c02000 {
 431                         compatible = "allwinner,sun6i-a31-dma";
 432                         reg = <0x01c02000 0x1000>;
 433                         interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
 434                         clocks = <&ahb1_gates 6>;
 435                         resets = <&ahb1_rst 6>;
 436                         #dma-cells = <1>;
 437                 };
 438
 439                 mmc0: mmc@01c0f000 {
 440                         compatible = "allwinner,sun5i-a13-mmc";
 441                         reg = <0x01c0f000 0x1000>;
 442                         clocks = <&ahb1_gates 8>,
 443                                  <&mmc0_clk 0>,
 444                                  <&mmc0_clk 1>,
 445                                  <&mmc0_clk 2>;
 446                         clock-names = "ahb",
 447                                       "mmc",
 448                                       "output",
 449                                       "sample";
 450                         resets = <&ahb1_rst 8>;
 451                         reset-names = "ahb";
 452                         interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
 453                         status = "disabled";
 454                         #address-cells = <1>;
 455                         #size-cells = <0>;
 456                 };
 457
 458                 mmc1: mmc@01c10000 {
 459                         compatible = "allwinner,sun5i-a13-mmc";
 460                         reg = <0x01c10000 0x1000>;
 461                         clocks = <&ahb1_gates 9>,
 462                                  <&mmc1_clk 0>,
 463                                  <&mmc1_clk 1>,
 464                                  <&mmc1_clk 2>;
 465                         clock-names = "ahb",
 466                                       "mmc",
 467                                       "output",
 468                                       "sample";
 469                         resets = <&ahb1_rst 9>;
 470                         reset-names = "ahb";
 471                         interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
 472                         status = "disabled";
 473                         #address-cells = <1>;
 474                         #size-cells = <0>;
 475                 };
 476
 477                 mmc2: mmc@01c11000 {
 478                         compatible = "allwinner,sun5i-a13-mmc";
 479                         reg = <0x01c11000 0x1000>;
 480                         clocks = <&ahb1_gates 10>,
 481                                  <&mmc2_clk 0>,
 482                                  <&mmc2_clk 1>,
 483                                  <&mmc2_clk 2>;
 484                         clock-names = "ahb",
 485                                       "mmc",
 486                                       "output",
 487                                       "sample";
 488                         resets = <&ahb1_rst 10>;
 489                         reset-names = "ahb";
 490                         interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
 491                         status = "disabled";
 492                         #address-cells = <1>;
 493                         #size-cells = <0>;
 494                 };
 495
 496                 mmc3: mmc@01c12000 {
 497                         compatible = "allwinner,sun5i-a13-mmc";
 498                         reg = <0x01c12000 0x1000>;
 499                         clocks = <&ahb1_gates 11>,
 500                                  <&mmc3_clk 0>,
 501                                  <&mmc3_clk 1>,
 502                                  <&mmc3_clk 2>;
 503                         clock-names = "ahb",
 504                                       "mmc",
 505                                       "output",
 506                                       "sample";
 507                         resets = <&ahb1_rst 11>;
 508                         reset-names = "ahb";
 509                         interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
 510                         status = "disabled";
 511                         #address-cells = <1>;
 512                         #size-cells = <0>;
 513                 };
 514
 515                 usbphy: phy@01c19400 {
 516                         compatible = "allwinner,sun6i-a31-usb-phy";
 517                         reg = <0x01c19400 0x10>,
 518                               <0x01c1a800 0x4>,
 519                               <0x01c1b800 0x4>;
 520                         reg-names = "phy_ctrl",
 521                                     "pmu1",
 522                                     "pmu2";
 523                         clocks = <&usb_clk 8>,
 524                                  <&usb_clk 9>,
 525                                  <&usb_clk 10>;
 526                         clock-names = "usb0_phy",
 527                                       "usb1_phy",
 528                                       "usb2_phy";
 529                         resets = <&usb_clk 0>,
 530                                  <&usb_clk 1>,
 531                                  <&usb_clk 2>;
 532                         reset-names = "usb0_reset",
 533                                       "usb1_reset",
 534                                       "usb2_reset";
 535                         status = "disabled";
 536                         #phy-cells = <1>;
 537                 };
 538
 539                 ehci0: usb@01c1a000 {
 540                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 541                         reg = <0x01c1a000 0x100>;
 542                         interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
 543                         clocks = <&ahb1_gates 26>;
 544                         resets = <&ahb1_rst 26>;
 545                         phys = <&usbphy 1>;
 546                         phy-names = "usb";
 547                         status = "disabled";
 548                 };
 549
 550                 ohci0: usb@01c1a400 {
 551                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 552                         reg = <0x01c1a400 0x100>;
 553                         interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
 554                         clocks = <&ahb1_gates 29>, <&usb_clk 16>;
 555                         resets = <&ahb1_rst 29>;
 556                         phys = <&usbphy 1>;
 557                         phy-names = "usb";
 558                         status = "disabled";
 559                 };
 560
 561                 ehci1: usb@01c1b000 {
 562                         compatible = "allwinner,sun6i-a31-ehci", "generic-ehci";
 563                         reg = <0x01c1b000 0x100>;
 564                         interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
 565                         clocks = <&ahb1_gates 27>;
 566                         resets = <&ahb1_rst 27>;
 567                         phys = <&usbphy 2>;
 568                         phy-names = "usb";
 569                         status = "disabled";
 570                 };
 571
 572                 ohci1: usb@01c1b400 {
 573                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 574                         reg = <0x01c1b400 0x100>;
 575                         interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 576                         clocks = <&ahb1_gates 30>, <&usb_clk 17>;
 577                         resets = <&ahb1_rst 30>;
 578                         phys = <&usbphy 2>;
 579                         phy-names = "usb";
 580                         status = "disabled";
 581                 };
 582
 583                 ohci2: usb@01c1c400 {
 584                         compatible = "allwinner,sun6i-a31-ohci", "generic-ohci";
 585                         reg = <0x01c1c400 0x100>;
 586                         interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
 587                         clocks = <&ahb1_gates 31>, <&usb_clk 18>;
 588                         resets = <&ahb1_rst 31>;
 589                         status = "disabled";
 590                 };
 591
 592                 pio: pinctrl@01c20800 {
 593                         compatible = "allwinner,sun6i-a31-pinctrl";
 594                         reg = <0x01c20800 0x400>;
 595                         interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
 596                                      <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>,
 597                                      <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
 598                                      <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
 599                         clocks = <&apb1_gates 5>;
 600                         gpio-controller;
 601                         interrupt-controller;
 602                         #interrupt-cells = <2>;
 603                         #size-cells = <0>;
 604                         #gpio-cells = <3>;
 605
 606                         uart0_pins_a: uart0@0 {
 607                                 allwinner,pins = "PH20", "PH21";
 608                                 allwinner,function = "uart0";
 609                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 610                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 611                         };
 612
 613                         i2c0_pins_a: i2c0@0 {
 614                                 allwinner,pins = "PH14", "PH15";
 615                                 allwinner,function = "i2c0";
 616                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 617                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 618                         };
 619
 620                         i2c1_pins_a: i2c1@0 {
 621                                 allwinner,pins = "PH16", "PH17";
 622                                 allwinner,function = "i2c1";
 623                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 624                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 625                         };
 626
 627                         i2c2_pins_a: i2c2@0 {
 628                                 allwinner,pins = "PH18", "PH19";
 629                                 allwinner,function = "i2c2";
 630                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 631                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 632                         };
 633
 634                         mmc0_pins_a: mmc0@0 {
 635                                 allwinner,pins = "PF0", "PF1", "PF2",
 636                                                  "PF3", "PF4", "PF5";
 637                                 allwinner,function = "mmc0";
 638                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 639                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 640                         };
 641
 642                         mmc1_pins_a: mmc1@0 {
 643                                 allwinner,pins = "PG0", "PG1", "PG2", "PG3",
 644                                                  "PG4", "PG5";
 645                                 allwinner,function = "mmc1";
 646                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 647                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 648                         };
 649
 650                         gmac_pins_mii_a: gmac_mii@0 {
 651                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 652                                                 "PA8", "PA9", "PA11",
 653                                                 "PA12", "PA13", "PA14", "PA19",
 654                                                 "PA20", "PA21", "PA22", "PA23",
 655                                                 "PA24", "PA26", "PA27";
 656                                 allwinner,function = "gmac";
 657                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
 658                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 659                         };
 660
 661                         gmac_pins_gmii_a: gmac_gmii@0 {
 662                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 663                                                 "PA4", "PA5", "PA6", "PA7",
 664                                                 "PA8", "PA9", "PA10", "PA11",
 665                                                 "PA12", "PA13", "PA14", "PA15",
 666                                                 "PA16", "PA17", "PA18", "PA19",
 667                                                 "PA20", "PA21", "PA22", "PA23",
 668                                                 "PA24", "PA25", "PA26", "PA27";
 669                                 allwinner,function = "gmac";
 670                                 /*
 671                                  * data lines in GMII mode run at 125MHz and
 672                                  * might need a higher signal drive strength
 673                                  */
 674                                 allwinner,drive = <SUN4I_PINCTRL_30_MA>;
 675                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 676                         };
 677
 678                         gmac_pins_rgmii_a: gmac_rgmii@0 {
 679                                 allwinner,pins = "PA0", "PA1", "PA2", "PA3",
 680                                                 "PA9", "PA10", "PA11",
 681                                                 "PA12", "PA13", "PA14", "PA19",
 682                                                 "PA20", "PA25", "PA26", "PA27";
 683                                 allwinner,function = "gmac";
 684                                 /*
 685                                  * data lines in RGMII mode use DDR mode
 686                                  * and need a higher signal drive strength
 687                                  */
 688                                 allwinner,drive = <SUN4I_PINCTRL_40_MA>;
 689                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
 690                         };
 691                 };
 692
 693                 ahb1_rst: reset@01c202c0 {
 694                         #reset-cells = <1>;
 695                         compatible = "allwinner,sun6i-a31-ahb1-reset";
 696                         reg = <0x01c202c0 0xc>;
 697                 };
 698
 699                 apb1_rst: reset@01c202d0 {
 700                         #reset-cells = <1>;
 701                         compatible = "allwinner,sun6i-a31-clock-reset";
 702                         reg = <0x01c202d0 0x4>;
 703                 };
 704
 705                 apb2_rst: reset@01c202d8 {
 706                         #reset-cells = <1>;
 707                         compatible = "allwinner,sun6i-a31-clock-reset";
 708                         reg = <0x01c202d8 0x4>;
 709                 };
 710
 711                 timer@01c20c00 {
 712                         compatible = "allwinner,sun4i-a10-timer";
 713                         reg = <0x01c20c00 0xa0>;
 714                         interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
 715                                      <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
 716                                      <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>,
 717                                      <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>,
 718                                      <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
 719                         clocks = <&osc24M>;
 720                 };
 721
 722                 wdt1: watchdog@01c20ca0 {
 723                         compatible = "allwinner,sun6i-a31-wdt";
 724                         reg = <0x01c20ca0 0x20>;
 725                 };
 726
 727                 rtp: rtp@01c25000 {
 728                         compatible = "allwinner,sun6i-a31-ts";
 729                         reg = <0x01c25000 0x100>;
 730                         interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
 731                         #thermal-sensor-cells = <0>;
 732                 };
 733
 734                 uart0: serial@01c28000 {
 735                         compatible = "snps,dw-apb-uart";
 736                         reg = <0x01c28000 0x400>;
 737                         interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
 738                         reg-shift = <2>;
 739                         reg-io-width = <4>;
 740                         clocks = <&apb2_gates 16>;
 741                         resets = <&apb2_rst 16>;
 742                         dmas = <&dma 6>, <&dma 6>;
 743                         dma-names = "rx", "tx";
 744                         status = "disabled";
 745                 };
 746
 747                 uart1: serial@01c28400 {
 748                         compatible = "snps,dw-apb-uart";
 749                         reg = <0x01c28400 0x400>;
 750                         interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
 751                         reg-shift = <2>;
 752                         reg-io-width = <4>;
 753                         clocks = <&apb2_gates 17>;
 754                         resets = <&apb2_rst 17>;
 755                         dmas = <&dma 7>, <&dma 7>;
 756                         dma-names = "rx", "tx";
 757                         status = "disabled";
 758                 };
 759
 760                 uart2: serial@01c28800 {
 761                         compatible = "snps,dw-apb-uart";
 762                         reg = <0x01c28800 0x400>;
 763                         interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
 764                         reg-shift = <2>;
 765                         reg-io-width = <4>;
 766                         clocks = <&apb2_gates 18>;
 767                         resets = <&apb2_rst 18>;
 768                         dmas = <&dma 8>, <&dma 8>;
 769                         dma-names = "rx", "tx";
 770                         status = "disabled";
 771                 };
 772
 773                 uart3: serial@01c28c00 {
 774                         compatible = "snps,dw-apb-uart";
 775                         reg = <0x01c28c00 0x400>;
 776                         interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
 777                         reg-shift = <2>;
 778                         reg-io-width = <4>;
 779                         clocks = <&apb2_gates 19>;
 780                         resets = <&apb2_rst 19>;
 781                         dmas = <&dma 9>, <&dma 9>;
 782                         dma-names = "rx", "tx";
 783                         status = "disabled";
 784                 };
 785
 786                 uart4: serial@01c29000 {
 787                         compatible = "snps,dw-apb-uart";
 788                         reg = <0x01c29000 0x400>;
 789                         interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
 790                         reg-shift = <2>;
 791                         reg-io-width = <4>;
 792                         clocks = <&apb2_gates 20>;
 793                         resets = <&apb2_rst 20>;
 794                         dmas = <&dma 10>, <&dma 10>;
 795                         dma-names = "rx", "tx";
 796                         status = "disabled";
 797                 };
 798
 799                 uart5: serial@01c29400 {
 800                         compatible = "snps,dw-apb-uart";
 801                         reg = <0x01c29400 0x400>;
 802                         interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
 803                         reg-shift = <2>;
 804                         reg-io-width = <4>;
 805                         clocks = <&apb2_gates 21>;
 806                         resets = <&apb2_rst 21>;
 807                         dmas = <&dma 22>, <&dma 22>;
 808                         dma-names = "rx", "tx";
 809                         status = "disabled";
 810                 };
 811
 812                 i2c0: i2c@01c2ac00 {
 813                         compatible = "allwinner,sun6i-a31-i2c";
 814                         reg = <0x01c2ac00 0x400>;
 815                         interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
 816                         clocks = <&apb2_gates 0>;
 817                         resets = <&apb2_rst 0>;
 818                         status = "disabled";
 819                         #address-cells = <1>;
 820                         #size-cells = <0>;
 821                 };
 822
 823                 i2c1: i2c@01c2b000 {
 824                         compatible = "allwinner,sun6i-a31-i2c";
 825                         reg = <0x01c2b000 0x400>;
 826                         interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
 827                         clocks = <&apb2_gates 1>;
 828                         resets = <&apb2_rst 1>;
 829                         status = "disabled";
 830                         #address-cells = <1>;
 831                         #size-cells = <0>;
 832                 };
 833
 834                 i2c2: i2c@01c2b400 {
 835                         compatible = "allwinner,sun6i-a31-i2c";
 836                         reg = <0x01c2b400 0x400>;
 837                         interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
 838                         clocks = <&apb2_gates 2>;
 839                         resets = <&apb2_rst 2>;
 840                         status = "disabled";
 841                         #address-cells = <1>;
 842                         #size-cells = <0>;
 843                 };
 844
 845                 i2c3: i2c@01c2b800 {
 846                         compatible = "allwinner,sun6i-a31-i2c";
 847                         reg = <0x01c2b800 0x400>;
 848                         interrupts = <GIC_SPI 9 IRQ_TYPE_LEVEL_HIGH>;
 849                         clocks = <&apb2_gates 3>;
 850                         resets = <&apb2_rst 3>;
 851                         status = "disabled";
 852                         #address-cells = <1>;
 853                         #size-cells = <0>;
 854                 };
 855
 856                 gmac: ethernet@01c30000 {
 857                         compatible = "allwinner,sun7i-a20-gmac";
 858                         reg = <0x01c30000 0x1054>;
 859                         interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
 860                         interrupt-names = "macirq";
 861                         clocks = <&ahb1_gates 17>, <&gmac_tx_clk>;
 862                         clock-names = "stmmaceth", "allwinner_gmac_tx";
 863                         resets = <&ahb1_rst 17>;
 864                         reset-names = "stmmaceth";
 865                         snps,pbl = <2>;
 866                         snps,fixed-burst;
 867                         snps,force_sf_dma_mode;
 868                         status = "disabled";
 869                         #address-cells = <1>;
 870                         #size-cells = <0>;
 871                 };
 872
 873                 timer@01c60000 {
 874                         compatible = "allwinner,sun6i-a31-hstimer",
 875                                      "allwinner,sun7i-a20-hstimer";
 876                         reg = <0x01c60000 0x1000>;
 877                         interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>,
 878                                      <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>,
 879                                      <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>,
 880                                      <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
 881                         clocks = <&ahb1_gates 19>;
 882                         resets = <&ahb1_rst 19>;
 883                 };
 884
 885                 spi0: spi@01c68000 {
 886                         compatible = "allwinner,sun6i-a31-spi";
 887                         reg = <0x01c68000 0x1000>;
 888                         interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
 889                         clocks = <&ahb1_gates 20>, <&spi0_clk>;
 890                         clock-names = "ahb", "mod";
 891                         dmas = <&dma 23>, <&dma 23>;
 892                         dma-names = "rx", "tx";
 893                         resets = <&ahb1_rst 20>;
 894                         status = "disabled";
 895                 };
 896
 897                 spi1: spi@01c69000 {
 898                         compatible = "allwinner,sun6i-a31-spi";
 899                         reg = <0x01c69000 0x1000>;
 900                         interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
 901                         clocks = <&ahb1_gates 21>, <&spi1_clk>;
 902                         clock-names = "ahb", "mod";
 903                         dmas = <&dma 24>, <&dma 24>;
 904                         dma-names = "rx", "tx";
 905                         resets = <&ahb1_rst 21>;
 906                         status = "disabled";
 907                 };
 908
 909                 spi2: spi@01c6a000 {
 910                         compatible = "allwinner,sun6i-a31-spi";
 911                         reg = <0x01c6a000 0x1000>;
 912                         interrupts = <GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
 913                         clocks = <&ahb1_gates 22>, <&spi2_clk>;
 914                         clock-names = "ahb", "mod";
 915                         dmas = <&dma 25>, <&dma 25>;
 916                         dma-names = "rx", "tx";
 917                         resets = <&ahb1_rst 22>;
 918                         status = "disabled";
 919                 };
 920
 921                 spi3: spi@01c6b000 {
 922                         compatible = "allwinner,sun6i-a31-spi";
 923                         reg = <0x01c6b000 0x1000>;
 924                         interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
 925                         clocks = <&ahb1_gates 23>, <&spi3_clk>;
 926                         clock-names = "ahb", "mod";
 927                         dmas = <&dma 26>, <&dma 26>;
 928                         dma-names = "rx", "tx";
 929                         resets = <&ahb1_rst 23>;
 930                         status = "disabled";
 931                 };
 932
 933                 gic: interrupt-controller@01c81000 {
 934                         compatible = "arm,cortex-a7-gic", "arm,cortex-a15-gic";
 935                         reg = <0x01c81000 0x1000>,
 936                               <0x01c82000 0x1000>,
 937                               <0x01c84000 0x2000>,
 938                               <0x01c86000 0x2000>;
 939                         interrupt-controller;
 940                         #interrupt-cells = <3>;
 941                         interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
 942                 };
 943
 944                 rtc: rtc@01f00000 {
 945                         compatible = "allwinner,sun6i-a31-rtc";
 946                         reg = <0x01f00000 0x54>;
 947                         interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
 948                                      <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
 949                 };
 950
 951                 nmi_intc: interrupt-controller@01f00c0c {
 952                         compatible = "allwinner,sun6i-a31-sc-nmi";
 953                         interrupt-controller;
 954                         #interrupt-cells = <2>;
 955                         reg = <0x01f00c0c 0x38>;
 956                         interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
 957                 };
 958
 959                 prcm@01f01400 {
 960                         compatible = "allwinner,sun6i-a31-prcm";
 961                         reg = <0x01f01400 0x200>;
 962
 963                         ar100: ar100_clk {
 964                                 compatible = "allwinner,sun6i-a31-ar100-clk";
 965                                 #clock-cells = <0>;
 966                                 clocks = <&osc32k>, <&osc24M>, <&pll6 0>,
 967                                          <&pll6 0>;
 968                                 clock-output-names = "ar100";
 969                         };
 970
 971                         ahb0: ahb0_clk {
 972                                 compatible = "fixed-factor-clock";
 973                                 #clock-cells = <0>;
 974                                 clock-div = <1>;
 975                                 clock-mult = <1>;
 976                                 clocks = <&ar100>;
 977                                 clock-output-names = "ahb0";
 978                         };
 979
 980                         apb0: apb0_clk {
 981                                 compatible = "allwinner,sun6i-a31-apb0-clk";
 982                                 #clock-cells = <0>;
 983                                 clocks = <&ahb0>;
 984                                 clock-output-names = "apb0";
 985                         };
 986
 987                         apb0_gates: apb0_gates_clk {
 988                                 compatible = "allwinner,sun6i-a31-apb0-gates-clk";
 989                                 #clock-cells = <1>;
 990                                 clocks = <&apb0>;
 991                                 clock-output-names = "apb0_pio", "apb0_ir",
 992                                                 "apb0_timer", "apb0_p2wi",
 993                                                 "apb0_uart", "apb0_1wire",
 994                                                 "apb0_i2c";
 995                         };
 996
 997                         ir_clk: ir_clk {
 998                                 #clock-cells = <0>;
 999                                 compatible = "allwinner,sun4i-a10-mod0-clk";
1000                                 clocks = <&osc32k>, <&osc24M>;
1001                                 clock-output-names = "ir";
1002                         };
1003
1004                         apb0_rst: apb0_rst {
1005                                 compatible = "allwinner,sun6i-a31-clock-reset";
1006                                 #reset-cells = <1>;
1007                         };
1008                 };
1009
1010                 cpucfg@01f01c00 {
1011                         compatible = "allwinner,sun6i-a31-cpuconfig";
1012                         reg = <0x01f01c00 0x300>;
1013                 };
1014
1015                 ir: ir@01f02000 {
1016                         compatible = "allwinner,sun5i-a13-ir";
1017                         clocks = <&apb0_gates 1>, <&ir_clk>;
1018                         clock-names = "apb", "ir";
1019                         resets = <&apb0_rst 1>;
1020                         interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1021                         reg = <0x01f02000 0x40>;
1022                         status = "disabled";
1023                 };
1024
1025                 r_pio: pinctrl@01f02c00 {
1026                         compatible = "allwinner,sun6i-a31-r-pinctrl";
1027                         reg = <0x01f02c00 0x400>;
1028                         interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>,
1029                                      <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
1030                         clocks = <&apb0_gates 0>;
1031                         resets = <&apb0_rst 0>;
1032                         gpio-controller;
1033                         interrupt-controller;
1034                         #interrupt-cells = <2>;
1035                         #size-cells = <0>;
1036                         #gpio-cells = <3>;
1037
1038                         ir_pins_a: ir@0 {
1039                                 allwinner,pins = "PL4";
1040                                 allwinner,function = "s_ir";
1041                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1042                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1043                         };
1044
1045                         p2wi_pins: p2wi {
1046                                 allwinner,pins = "PL0", "PL1";
1047                                 allwinner,function = "s_p2wi";
1048                                 allwinner,drive = <SUN4I_PINCTRL_10_MA>;
1049                                 allwinner,pull = <SUN4I_PINCTRL_NO_PULL>;
1050                         };
1051                 };
1052
1053                 p2wi: i2c@01f03400 {
1054                         compatible = "allwinner,sun6i-a31-p2wi";
1055                         reg = <0x01f03400 0x400>;
1056                         interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
1057                         clocks = <&apb0_gates 3>;
1058                         clock-frequency = <100000>;
1059                         resets = <&apb0_rst 3>;
1060                         pinctrl-names = "default";
1061                         pinctrl-0 = <&p2wi_pins>;
1062                         status = "disabled";
1063                         #address-cells = <1>;
1064                         #size-cells = <0>;
1065                 };
1066         };
1067 };