arch/arm/dts/tegra20-tamonten.dtsi

   1 #include "tegra20.dtsi"
   2
   3 / {
   4         model = "Avionic Design Tamonten SOM";
   5         compatible = "ad,tamonten", "nvidia,tegra20";
   6
   7         memory {
   8                 reg = <0x00000000 0x20000000>;
   9         };
  10
  11         host1x {
  12                 hdmi {
  13                         vdd-supply = <&hdmi_vdd_reg>;
  14                         pll-supply = <&hdmi_pll_reg>;
  15
  16                         nvidia,ddc-i2c-bus = <&hdmi_ddc>;
  17                         nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
  18                                 GPIO_ACTIVE_HIGH>;
  19                 };
  20         };
  21
  22         pinmux {
  23                 pinctrl-names = "default";
  24                 pinctrl-0 = <&state_default>;
  25
  26                 state_default: pinmux {
  27                         ata {
  28                                 nvidia,pins = "ata";
  29                                 nvidia,function = "ide";
  30                         };
  31                         atb {
  32                                 nvidia,pins = "atb", "gma", "gme";
  33                                 nvidia,function = "sdio4";
  34                         };
  35                         atc {
  36                                 nvidia,pins = "atc";
  37                                 nvidia,function = "nand";
  38                         };
  39                         atd {
  40                                 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
  41                                         "spia", "spib", "spic";
  42                                 nvidia,function = "gmi";
  43                         };
  44                         cdev1 {
  45                                 nvidia,pins = "cdev1";
  46                                 nvidia,function = "plla_out";
  47                         };
  48                         cdev2 {
  49                                 nvidia,pins = "cdev2";
  50                                 nvidia,function = "pllp_out4";
  51                         };
  52                         crtp {
  53                                 nvidia,pins = "crtp";
  54                                 nvidia,function = "crt";
  55                         };
  56                         csus {
  57                                 nvidia,pins = "csus";
  58                                 nvidia,function = "vi_sensor_clk";
  59                         };
  60                         dap1 {
  61                                 nvidia,pins = "dap1";
  62                                 nvidia,function = "dap1";
  63                         };
  64                         dap2 {
  65                                 nvidia,pins = "dap2";
  66                                 nvidia,function = "dap2";
  67                         };
  68                         dap3 {
  69                                 nvidia,pins = "dap3";
  70                                 nvidia,function = "dap3";
  71                         };
  72                         dap4 {
  73                                 nvidia,pins = "dap4";
  74                                 nvidia,function = "dap4";
  75                         };
  76                         dta {
  77                                 nvidia,pins = "dta", "dtd";
  78                                 nvidia,function = "sdio2";
  79                         };
  80                         dtb {
  81                                 nvidia,pins = "dtb", "dtc", "dte";
  82                                 nvidia,function = "rsvd1";
  83                         };
  84                         dtf {
  85                                 nvidia,pins = "dtf";
  86                                 nvidia,function = "i2c3";
  87                         };
  88                         gmc {
  89                                 nvidia,pins = "gmc";
  90                                 nvidia,function = "uartd";
  91                         };
  92                         gpu7 {
  93                                 nvidia,pins = "gpu7";
  94                                 nvidia,function = "rtck";
  95                         };
  96                         gpv {
  97                                 nvidia,pins = "gpv", "slxa", "slxk";
  98                                 nvidia,function = "pcie";
  99                         };
 100                         hdint {
 101                                 nvidia,pins = "hdint";
 102                                 nvidia,function = "hdmi";
 103                         };
 104                         i2cp {
 105                                 nvidia,pins = "i2cp";
 106                                 nvidia,function = "i2cp";
 107                         };
 108                         irrx {
 109                                 nvidia,pins = "irrx", "irtx";
 110                                 nvidia,function = "uarta";
 111                         };
 112                         kbca {
 113                                 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
 114                                         "kbce", "kbcf";
 115                                 nvidia,function = "kbc";
 116                         };
 117                         lcsn {
 118                                 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
 119                                         "ld3", "ld4", "ld5", "ld6", "ld7",
 120                                         "ld8", "ld9", "ld10", "ld11", "ld12",
 121                                         "ld13", "ld14", "ld15", "ld16", "ld17",
 122                                         "ldc", "ldi", "lhp0", "lhp1", "lhp2",
 123                                         "lhs", "lm0", "lm1", "lpp", "lpw0",
 124                                         "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
 125                                         "lsda", "lsdi", "lspi", "lvp0", "lvp1",
 126                                         "lvs";
 127                                 nvidia,function = "displaya";
 128                         };
 129                         owc {
 130                                 nvidia,pins = "owc", "spdi", "spdo", "uac";
 131                                 nvidia,function = "rsvd2";
 132                         };
 133                         pmc {
 134                                 nvidia,pins = "pmc";
 135                                 nvidia,function = "pwr_on";
 136                         };
 137                         rm {
 138                                 nvidia,pins = "rm";
 139                                 nvidia,function = "i2c1";
 140                         };
 141                         sdb {
 142                                 nvidia,pins = "sdb", "sdc", "sdd";
 143                                 nvidia,function = "pwm";
 144                         };
 145                         sdio1 {
 146                                 nvidia,pins = "sdio1";
 147                                 nvidia,function = "sdio1";
 148                         };
 149                         slxc {
 150                                 nvidia,pins = "slxc", "slxd";
 151                                 nvidia,function = "spdif";
 152                         };
 153                         spid {
 154                                 nvidia,pins = "spid", "spie", "spif";
 155                                 nvidia,function = "spi1";
 156                         };
 157                         spig {
 158                                 nvidia,pins = "spig", "spih";
 159                                 nvidia,function = "spi2_alt";
 160                         };
 161                         uaa {
 162                                 nvidia,pins = "uaa", "uab", "uda";
 163                                 nvidia,function = "ulpi";
 164                         };
 165                         uad {
 166                                 nvidia,pins = "uad";
 167                                 nvidia,function = "irda";
 168                         };
 169                         uca {
 170                                 nvidia,pins = "uca", "ucb";
 171                                 nvidia,function = "uartc";
 172                         };
 173                         conf_ata {
 174                                 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
 175                                         "cdev1", "cdev2", "dap1", "dtb", "gma",
 176                                         "gmb", "gmc", "gmd", "gme", "gpu7",
 177                                         "gpv", "i2cp", "pta", "rm", "slxa",
 178                                         "slxk", "spia", "spib", "uac";
 179                                 nvidia,pull = <0>;
 180                                 nvidia,tristate = <0>;
 181                         };
 182                         conf_ck32 {
 183                                 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
 184                                         "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
 185                                 nvidia,pull = <0>;
 186                         };
 187                         conf_csus {
 188                                 nvidia,pins = "csus", "spid", "spif";
 189                                 nvidia,pull = <1>;
 190                                 nvidia,tristate = <1>;
 191                         };
 192                         conf_crtp {
 193                                 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
 194                                         "dtc", "dte", "dtf", "gpu", "sdio1",
 195                                         "slxc", "slxd", "spdi", "spdo", "spig",
 196                                         "uda";
 197                                 nvidia,pull = <0>;
 198                                 nvidia,tristate = <1>;
 199                         };
 200                         conf_ddc {
 201                                 nvidia,pins = "ddc", "dta", "dtd", "kbca",
 202                                         "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
 203                                         "sdc";
 204                                 nvidia,pull = <2>;
 205                                 nvidia,tristate = <0>;
 206                         };
 207                         conf_hdint {
 208                                 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
 209                                         "lpw1", "lsc1", "lsck", "lsda", "lsdi",
 210                                         "lvp0", "owc", "sdb";
 211                                 nvidia,tristate = <1>;
 212                         };
 213                         conf_irrx {
 214                                 nvidia,pins = "irrx", "irtx", "sdd", "spic",
 215                                         "spie", "spih", "uaa", "uab", "uad",
 216                                         "uca", "ucb";
 217                                 nvidia,pull = <2>;
 218                                 nvidia,tristate = <1>;
 219                         };
 220                         conf_lc {
 221                                 nvidia,pins = "lc", "ls";
 222                                 nvidia,pull = <2>;
 223                         };
 224                         conf_ld0 {
 225                                 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
 226                                         "ld5", "ld6", "ld7", "ld8", "ld9",
 227                                         "ld10", "ld11", "ld12", "ld13", "ld14",
 228                                         "ld15", "ld16", "ld17", "ldi", "lhp0",
 229                                         "lhp1", "lhp2", "lhs", "lm0", "lpp",
 230                                         "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
 231                                         "lvs", "pmc";
 232                                 nvidia,tristate = <0>;
 233                         };
 234                         conf_ld17_0 {
 235                                 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
 236                                         "ld23_22";
 237                                 nvidia,pull = <1>;
 238                         };
 239                 };
 240
 241                 state_i2cmux_ddc: pinmux_i2cmux_ddc {
 242                         ddc {
 243                                 nvidia,pins = "ddc";
 244                                 nvidia,function = "i2c2";
 245                         };
 246                         pta {
 247                                 nvidia,pins = "pta";
 248                                 nvidia,function = "rsvd4";
 249                         };
 250                 };
 251
 252                 state_i2cmux_pta: pinmux_i2cmux_pta {
 253                         ddc {
 254                                 nvidia,pins = "ddc";
 255                                 nvidia,function = "rsvd4";
 256                         };
 257                         pta {
 258                                 nvidia,pins = "pta";
 259                                 nvidia,function = "i2c2";
 260                         };
 261                 };
 262
 263                 state_i2cmux_idle: pinmux_i2cmux_idle {
 264                         ddc {
 265                                 nvidia,pins = "ddc";
 266                                 nvidia,function = "rsvd4";
 267                         };
 268                         pta {
 269                                 nvidia,pins = "pta";
 270                                 nvidia,function = "rsvd4";
 271                         };
 272                 };
 273         };
 274
 275         i2s@70002800 {
 276                 status = "okay";
 277         };
 278
 279         serial@70006300 {
 280                 status = "okay";
 281         };
 282
 283         nand-controller@70008000 {
 284                 nvidia,wp-gpios = <&gpio TEGRA_GPIO(C, 7) GPIO_ACTIVE_HIGH>;
 285                 nvidia,width = <8>;
 286                 nvidia,timing = <26 100 20 80 20 10 12 10 70>;
 287
 288                 nand@0 {
 289                         reg = <0>;
 290                         compatible = "hynix,hy27uf4g2b", "nand-flash";
 291                 };
 292         };
 293
 294         i2c@7000c000 {
 295                 clock-frequency = <400000>;
 296                 status = "okay";
 297         };
 298
 299         i2c@7000c400 {
 300                 clock-frequency = <100000>;
 301                 status = "okay";
 302         };
 303
 304         i2cmux {
 305                 compatible = "i2c-mux-pinctrl";
 306                 #address-cells = <1>;
 307                 #size-cells = <0>;
 308
 309                 i2c-parent = <&{/i2c@7000c400}>;
 310
 311                 pinctrl-names = "ddc", "pta", "idle";
 312                 pinctrl-0 = <&state_i2cmux_ddc>;
 313                 pinctrl-1 = <&state_i2cmux_pta>;
 314                 pinctrl-2 = <&state_i2cmux_idle>;
 315
 316                 hdmi_ddc: i2c@0 {
 317                         reg = <0>;
 318                         #address-cells = <1>;
 319                         #size-cells = <0>;
 320                 };
 321
 322                 i2c@1 {
 323                         reg = <1>;
 324                         #address-cells = <1>;
 325                         #size-cells = <0>;
 326                 };
 327         };
 328
 329         i2c@7000d000 {
 330                 clock-frequency = <400000>;
 331                 status = "okay";
 332
 333                 pmic: tps6586x@34 {
 334                         compatible = "ti,tps6586x";
 335                         reg = <0x34>;
 336                         interrupts = <0 86 0x4>;
 337
 338                         ti,system-power-controller;
 339
 340                         #gpio-cells = <2>;
 341                         gpio-controller;
 342
 343                         sys-supply = <&vdd_5v0_reg>;
 344                         vin-sm0-supply = <&sys_reg>;
 345                         vin-sm1-supply = <&sys_reg>;
 346                         vin-sm2-supply = <&sys_reg>;
 347                         vinldo01-supply = <&sm2_reg>;
 348                         vinldo23-supply = <&sm2_reg>;
 349                         vinldo4-supply = <&sm2_reg>;
 350                         vinldo678-supply = <&sm2_reg>;
 351                         vinldo9-supply = <&sm2_reg>;
 352
 353                         regulators {
 354                                 sys_reg: sys {
 355                                         regulator-name = "vdd_sys";
 356                                         regulator-always-on;
 357                                 };
 358
 359                                 sm0 {
 360                                         regulator-name = "vdd_sys_sm0,vdd_core";
 361                                         regulator-min-microvolt = <1200000>;
 362                                         regulator-max-microvolt = <1200000>;
 363                                         regulator-always-on;
 364                                 };
 365
 366                                 sm1 {
 367                                         regulator-name = "vdd_sys_sm1,vdd_cpu";
 368                                         regulator-min-microvolt = <1000000>;
 369                                         regulator-max-microvolt = <1000000>;
 370                                         regulator-always-on;
 371                                 };
 372
 373                                 sm2_reg: sm2 {
 374                                         regulator-name = "vdd_sys_sm2,vin_ldo*";
 375                                         regulator-min-microvolt = <3700000>;
 376                                         regulator-max-microvolt = <3700000>;
 377                                         regulator-always-on;
 378                                 };
 379
 380                                 ldo0 {
 381                                         regulator-name = "vdd_ldo0,vddio_pex_clk";
 382                                         regulator-min-microvolt = <3300000>;
 383                                         regulator-max-microvolt = <3300000>;
 384                                 };
 385
 386                                 ldo1 {
 387                                         regulator-name = "vdd_ldo1,avdd_pll*";
 388                                         regulator-min-microvolt = <1100000>;
 389                                         regulator-max-microvolt = <1100000>;
 390                                         regulator-always-on;
 391                                 };
 392
 393                                 ldo2 {
 394                                         regulator-name = "vdd_ldo2,vdd_rtc";
 395                                         regulator-min-microvolt = <1200000>;
 396                                         regulator-max-microvolt = <1200000>;
 397                                 };
 398
 399                                 ldo3 {
 400                                         regulator-name = "vdd_ldo3,avdd_usb*";
 401                                         regulator-min-microvolt = <3300000>;
 402                                         regulator-max-microvolt = <3300000>;
 403                                         regulator-always-on;
 404                                 };
 405
 406                                 ldo4 {
 407                                         regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
 408                                         regulator-min-microvolt = <1800000>;
 409                                         regulator-max-microvolt = <1800000>;
 410                                         regulator-always-on;
 411                                 };
 412
 413                                 ldo5 {
 414                                         regulator-name = "vdd_ldo5,vcore_mmc";
 415                                         regulator-min-microvolt = <2850000>;
 416                                         regulator-max-microvolt = <2850000>;
 417                                 };
 418
 419                                 ldo6 {
 420                                         regulator-name = "vdd_ldo6,avdd_vdac";
 421                                         /*
 422                                          * According to the Tegra 2 Automotive
 423                                          * DataSheet, a typical value for this
 424                                          * would be 2.8V, but the PMIC only
 425                                          * supports 2.85V.
 426                                          */
 427                                         regulator-min-microvolt = <2850000>;
 428                                         regulator-max-microvolt = <2850000>;
 429                                 };
 430
 431                                 hdmi_vdd_reg: ldo7 {
 432                                         regulator-name = "vdd_ldo7,avdd_hdmi";
 433                                         regulator-min-microvolt = <3300000>;
 434                                         regulator-max-microvolt = <3300000>;
 435                                 };
 436
 437                                 hdmi_pll_reg: ldo8 {
 438                                         regulator-name = "vdd_ldo8,avdd_hdmi_pll";
 439                                         regulator-min-microvolt = <1800000>;
 440                                         regulator-max-microvolt = <1800000>;
 441                                 };
 442
 443                                 ldo9 {
 444                                         regulator-name = "vdd_ldo9,vdd_ddr_rx,avdd_cam";
 445                                         /*
 446                                          * According to the Tegra 2 Automotive
 447                                          * DataSheet, a typical value for this
 448                                          * would be 2.8V, but the PMIC only
 449                                          * supports 2.85V.
 450                                          */
 451                                         regulator-min-microvolt = <2850000>;
 452                                         regulator-max-microvolt = <2850000>;
 453                                         regulator-always-on;
 454                                 };
 455
 456                                 ldo_rtc {
 457                                         regulator-name = "vdd_rtc_out";
 458                                         regulator-min-microvolt = <3300000>;
 459                                         regulator-max-microvolt = <3300000>;
 460                                         regulator-always-on;
 461                                 };
 462                         };
 463                 };
 464
 465                 temperature-sensor@4c {
 466                         compatible = "onnn,nct1008";
 467                         reg = <0x4c>;
 468                 };
 469         };
 470
 471         pmc {
 472                 nvidia,invert-interrupt;
 473         };
 474
 475         usb@c5008000 {
 476                 status = "okay";
 477         };
 478
 479         sdhci@c8000600 {
 480                 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
 481                 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
 482                 bus-width = <4>;
 483                 status = "okay";
 484         };
 485
 486         regulators {
 487                 compatible = "simple-bus";
 488
 489                 #address-cells = <1>;
 490                 #size-cells = <0>;
 491
 492                 vdd_5v0_reg: regulator@0 {
 493                         compatible = "regulator-fixed";
 494                         reg = <0>;
 495                         regulator-name = "vdd_5v0";
 496                         regulator-min-microvolt = <5000000>;
 497                         regulator-max-microvolt = <5000000>;
 498                         regulator-always-on;
 499                 };
 500         };
 501 };