arch/arm/dts/tegra20.dtsi

   1 /include/ "skeleton.dtsi"
   2
   3 / {
   4         compatible = "nvidia,tegra20";
   5         interrupt-parent = <&intc>;
   6
   7         tegra_car: clock@60006000 {
   8                 compatible = "nvidia,tegra20-car";
   9                 reg = <0x60006000 0x1000>;
  10                 #clock-cells = <1>;
  11         };
  12
  13         clocks {
  14                 #address-cells = <1>;
  15                 #size-cells = <0>;
  16
  17                 osc: clock {
  18                         compatible = "fixed-clock";
  19                         #clock-cells = <0>;
  20                 };
  21         };
  22
  23         intc: interrupt-controller@50041000 {
  24                 compatible = "nvidia,tegra20-gic";
  25                 interrupt-controller;
  26                 #interrupt-cells = <1>;
  27                 reg = < 0x50041000 0x1000 >,
  28                       < 0x50040100 0x0100 >;
  29         };
  30
  31         i2c@7000c000 {
  32                 #address-cells = <1>;
  33                 #size-cells = <0>;
  34                 compatible = "nvidia,tegra20-i2c";
  35                 reg = <0x7000C000 0x100>;
  36                 interrupts = < 70 >;
  37                 /* PERIPH_ID_I2C1, PLL_P_OUT3 */
  38                 clocks = <&tegra_car 12>, <&tegra_car 124>;
  39         };
  40
  41         i2c@7000c400 {
  42                 #address-cells = <1>;
  43                 #size-cells = <0>;
  44                 compatible = "nvidia,tegra20-i2c";
  45                 reg = <0x7000C400 0x100>;
  46                 interrupts = < 116 >;
  47                 /* PERIPH_ID_I2C2, PLL_P_OUT3 */
  48                 clocks = <&tegra_car 54>, <&tegra_car 124>;
  49         };
  50
  51         i2c@7000c500 {
  52                 #address-cells = <1>;
  53                 #size-cells = <0>;
  54                 compatible = "nvidia,tegra20-i2c";
  55                 reg = <0x7000C500 0x100>;
  56                 interrupts = < 124 >;
  57                 /* PERIPH_ID_I2C3, PLL_P_OUT3 */
  58                 clocks = <&tegra_car 67>, <&tegra_car 124>;
  59         };
  60
  61         i2c@7000d000 {
  62                 #address-cells = <1>;
  63                 #size-cells = <0>;
  64                 compatible = "nvidia,tegra20-i2c-dvc";
  65                 reg = <0x7000D000 0x200>;
  66                 interrupts = < 85 >;
  67                 /* PERIPH_ID_DVC_I2C, PLL_P_OUT3 */
  68                 clocks = <&tegra_car 47>, <&tegra_car 124>;
  69         };
  70
  71         i2s@70002800 {
  72                 #address-cells = <1>;
  73                 #size-cells = <0>;
  74                 compatible = "nvidia,tegra20-i2s";
  75                 reg = <0x70002800 0x200>;
  76                 interrupts = < 45 >;
  77                 dma-channel = < 2 >;
  78         };
  79
  80         i2s@70002a00 {
  81                 #address-cells = <1>;
  82                 #size-cells = <0>;
  83                 compatible = "nvidia,tegra20-i2s";
  84                 reg = <0x70002a00 0x200>;
  85                 interrupts = < 35 >;
  86                 dma-channel = < 1 >;
  87         };
  88
  89         das@70000c00 {
  90                 #address-cells = <1>;
  91                 #size-cells = <0>;
  92                 compatible = "nvidia,tegra20-das";
  93                 reg = <0x70000c00 0x80>;
  94         };
  95
  96         gpio: gpio@6000d000 {
  97                 compatible = "nvidia,tegra20-gpio";
  98                 reg = < 0x6000d000 0x1000 >;
  99                 interrupts = < 64 65 66 67 87 119 121 >;
 100                 #gpio-cells = <2>;
 101                 gpio-controller;
 102         };
 103
 104         pinmux: pinmux@70000000 {
 105                 compatible = "nvidia,tegra20-pinmux";
 106                 reg = < 0x70000014 0x10    /* Tri-state registers */
 107                         0x70000080 0x20    /* Mux registers */
 108                         0x700000a0 0x14    /* Pull-up/down registers */
 109                         0x70000868 0xa8 >; /* Pad control registers */
 110         };
 111
 112         serial@70006000 {
 113                 compatible = "nvidia,tegra20-uart";
 114                 reg = <0x70006000 0x40>;
 115                 reg-shift = <2>;
 116                 interrupts = < 68 >;
 117         };
 118
 119         serial@70006040 {
 120                 compatible = "nvidia,tegra20-uart";
 121                 reg = <0x70006040 0x40>;
 122                 reg-shift = <2>;
 123                 interrupts = < 69 >;
 124         };
 125
 126         serial@70006200 {
 127                 compatible = "nvidia,tegra20-uart";
 128                 reg = <0x70006200 0x100>;
 129                 reg-shift = <2>;
 130                 interrupts = < 78 >;
 131         };
 132
 133         serial@70006300 {
 134                 compatible = "nvidia,tegra20-uart";
 135                 reg = <0x70006300 0x100>;
 136                 reg-shift = <2>;
 137                 interrupts = < 122 >;
 138         };
 139
 140         serial@70006400 {
 141                 compatible = "nvidia,tegra20-uart";
 142                 reg = <0x70006400 0x100>;
 143                 reg-shift = <2>;
 144                 interrupts = < 123 >;
 145         };
 146
 147         sdhci@c8000000 {
 148                 compatible = "nvidia,tegra20-sdhci";
 149                 reg = <0xc8000000 0x200>;
 150                 interrupts = < 46 >;
 151         };
 152
 153         sdhci@c8000200 {
 154                 compatible = "nvidia,tegra20-sdhci";
 155                 reg = <0xc8000200 0x200>;
 156                 interrupts = < 47 >;
 157         };
 158
 159         sdhci@c8000400 {
 160                 compatible = "nvidia,tegra20-sdhci";
 161                 reg = <0xc8000400 0x200>;
 162                 interrupts = < 51 >;
 163         };
 164
 165         sdhci@c8000600 {
 166                 compatible = "nvidia,tegra20-sdhci";
 167                 reg = <0xc8000600 0x200>;
 168                 interrupts = < 63 >;
 169         };
 170
 171         usb@c5000000 {
 172                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 173                 reg = <0xc5000000 0x4000>;
 174                 interrupts = < 52 >;
 175                 phy_type = "utmi";
 176                 clocks = <&tegra_car 22>;       /* PERIPH_ID_USBD */
 177                 nvidia,has-legacy-mode;
 178         };
 179
 180         usb@c5004000 {
 181                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 182                 reg = <0xc5004000 0x4000>;
 183                 interrupts = < 53 >;
 184                 phy_type = "ulpi";
 185                 clocks = <&tegra_car 58>;       /* PERIPH_ID_USB2 */
 186         };
 187
 188         usb@c5008000 {
 189                 compatible = "nvidia,tegra20-ehci", "usb-ehci";
 190                 reg = <0xc5008000 0x4000>;
 191                 interrupts = < 129 >;
 192                 phy_type = "utmi";
 193                 clocks = <&tegra_car 59>;       /* PERIPH_ID_USB3 */
 194         };
 195
 196         emc@7000f400 {
 197                 #address-cells = < 1 >;
 198                 #size-cells = < 0 >;
 199                 compatible = "nvidia,tegra20-emc";
 200                 reg = <0x7000f400 0x200>;
 201         };
 202
 203         kbc@7000e200 {
 204                 compatible = "nvidia,tegra20-kbc";
 205                 reg = <0x7000e200 0x0078>;
 206         };
 207
 208         nand: nand-controller@70008000 {
 209                 #address-cells = <1>;
 210                 #size-cells = <0>;
 211                 compatible = "nvidia,tegra20-nand";
 212                 reg = <0x70008000 0x100>;
 213         };
 214
 215         pwm: pwm@7000a000 {
 216                 compatible = "nvidia,tegra20-pwm";
 217                 reg = <0x7000a000 0x100>;
 218                 #pwm-cells = <2>;
 219         };
 220
 221         host1x {
 222                 compatible = "nvidia,tegra20-host1x", "simple-bus";
 223                 reg = <0x50000000 0x00024000>;
 224                 interrupts = <0 65 0x04   /* mpcore syncpt */
 225                               0 67 0x04>; /* mpcore general */
 226                 status = "disabled";
 227
 228                 #address-cells = <1>;
 229                 #size-cells = <1>;
 230
 231                 ranges = <0x54000000 0x54000000 0x04000000>;
 232
 233                 /* video-encoding/decoding */
 234                 mpe {
 235                         reg = <0x54040000 0x00040000>;
 236                         interrupts = <0 68 0x04>;
 237                         status = "disabled";
 238                 };
 239
 240                 /* video input */
 241                 vi {
 242                         reg = <0x54080000 0x00040000>;
 243                         interrupts = <0 69 0x04>;
 244                         status = "disabled";
 245                 };
 246
 247                 /* EPP */
 248                 epp {
 249                         reg = <0x540c0000 0x00040000>;
 250                         interrupts = <0 70 0x04>;
 251                         status = "disabled";
 252                 };
 253
 254                 /* ISP */
 255                 isp {
 256                         reg = <0x54100000 0x00040000>;
 257                         interrupts = <0 71 0x04>;
 258                         status = "disabled";
 259                 };
 260
 261                 /* 2D engine */
 262                 gr2d {
 263                         reg = <0x54140000 0x00040000>;
 264                         interrupts = <0 72 0x04>;
 265                         status = "disabled";
 266                 };
 267
 268                 /* 3D engine */
 269                 gr3d {
 270                         reg = <0x54180000 0x00040000>;
 271                         status = "disabled";
 272                 };
 273
 274                 /* display controllers */
 275                 dc@54200000 {
 276                         compatible = "nvidia,tegra20-dc";
 277                         reg = <0x54200000 0x00040000>;
 278                         interrupts = <0 73 0x04>;
 279                         status = "disabled";
 280
 281                         rgb {
 282                                 status = "disabled";
 283                         };
 284                 };
 285
 286                 dc@54240000 {
 287                         compatible = "nvidia,tegra20-dc";
 288                         reg = <0x54240000 0x00040000>;
 289                         interrupts = <0 74 0x04>;
 290                         status = "disabled";
 291
 292                         rgb {
 293                                 status = "disabled";
 294                         };
 295                 };
 296
 297                 /* outputs */
 298                 hdmi {
 299                         compatible = "nvidia,tegra20-hdmi";
 300                         reg = <0x54280000 0x00040000>;
 301                         interrupts = <0 75 0x04>;
 302                         status = "disabled";
 303                 };
 304
 305                 tvo {
 306                         compatible = "nvidia,tegra20-tvo";
 307                         reg = <0x542c0000 0x00040000>;
 308                         interrupts = <0 76 0x04>;
 309                         status = "disabled";
 310                 };
 311
 312                 dsi {
 313                         compatible = "nvidia,tegra20-dsi";
 314                         reg = <0x54300000 0x00040000>;
 315                         status = "disabled";
 316                 };
 317         };
 318
 319 };