arch/arm/dts/zynq-zc702.dts

   1 /*
   2  * Xilinx ZC702 board DTS
   3  *
   4  *  Copyright (C) 2011 - 2015 Xilinx
   5  *  Copyright (C) 2012 National Instruments Corp.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 /dts-v1/;
  10 #include "zynq-7000.dtsi"
  11
  12 / {
  13         model = "Zynq ZC702 Development Board";
  14         compatible = "xlnx,zynq-zc702", "xlnx,zynq-7000";
  15
  16         aliases {
  17                 ethernet0 = &gem0;
  18                 i2c0 = &i2c0;
  19                 serial0 = &uart1;
  20         };
  21
  22         memory {
  23                 device_type = "memory";
  24                 reg = <0x0 0x40000000>;
  25         };
  26
  27         chosen {
  28                 bootargs = "earlyprintk";
  29                 stdout-path = "serial0:115200n8";
  30         };
  31
  32         gpio-keys {
  33                 compatible = "gpio-keys";
  34                 #address-cells = <1>;
  35                 #size-cells = <0>;
  36                 autorepeat;
  37                 sw14 {
  38                         label = "sw14";
  39                         gpios = <&gpio0 12 0>;
  40                         linux,code = <108>; /* down */
  41                         gpio-key,wakeup;
  42                         autorepeat;
  43                 };
  44                 sw13 {
  45                         label = "sw13";
  46                         gpios = <&gpio0 14 0>;
  47                         linux,code = <103>; /* up */
  48                         gpio-key,wakeup;
  49                         autorepeat;
  50                 };
  51         };
  52
  53         leds {
  54                 compatible = "gpio-leds";
  55
  56                 ds23 {
  57                         label = "ds23";
  58                         gpios = <&gpio0 10 0>;
  59                         linux,default-trigger = "heartbeat";
  60                 };
  61         };
  62
  63         usb_phy0: phy0 {
  64                 compatible = "usb-nop-xceiv";
  65                 #phy-cells = <0>;
  66         };
  67 };
  68
  69 &amba {
  70         ocm: sram@fffc0000 {
  71                 compatible = "mmio-sram";
  72                 reg = <0xfffc0000 0x10000>;
  73         };
  74 };
  75
  76 &can0 {
  77         status = "okay";
  78         pinctrl-names = "default";
  79         pinctrl-0 = <&pinctrl_can0_default>;
  80 };
  81
  82 &clkc {
  83         ps-clk-frequency = <33333333>;
  84 };
  85
  86 &gem0 {
  87         status = "okay";
  88         phy-mode = "rgmii-id";
  89         phy-handle = <&ethernet_phy>;
  90         pinctrl-names = "default";
  91         pinctrl-0 = <&pinctrl_gem0_default>;
  92
  93         ethernet_phy: ethernet-phy@7 {
  94                 reg = <7>;
  95         };
  96 };
  97
  98 &gpio0 {
  99         pinctrl-names = "default";
 100         pinctrl-0 = <&pinctrl_gpio0_default>;
 101 };
 102
 103 &i2c0 {
 104         status = "okay";
 105         clock-frequency = <400000>;
 106         pinctrl-names = "default";
 107         pinctrl-0 = <&pinctrl_i2c0_default>;
 108
 109         i2cswitch@74 {
 110                 compatible = "nxp,pca9548";
 111                 #address-cells = <1>;
 112                 #size-cells = <0>;
 113                 reg = <0x74>;
 114
 115                 i2c@0 {
 116                         #address-cells = <1>;
 117                         #size-cells = <0>;
 118                         reg = <0>;
 119                         si570: clock-generator@5d {
 120                                 #clock-cells = <0>;
 121                                 compatible = "silabs,si570";
 122                                 temperature-stability = <50>;
 123                                 reg = <0x5d>;
 124                                 factory-fout = <156250000>;
 125                                 clock-frequency = <148500000>;
 126                         };
 127                 };
 128
 129                 i2c@2 {
 130                         #address-cells = <1>;
 131                         #size-cells = <0>;
 132                         reg = <2>;
 133                         eeprom@54 {
 134                                 compatible = "at,24c08";
 135                                 reg = <0x54>;
 136                         };
 137                 };
 138
 139                 i2c@3 {
 140                         #address-cells = <1>;
 141                         #size-cells = <0>;
 142                         reg = <3>;
 143                         gpio@21 {
 144                                 compatible = "ti,tca6416";
 145                                 reg = <0x21>;
 146                                 gpio-controller;
 147                                 #gpio-cells = <2>;
 148                         };
 149                 };
 150
 151                 i2c@4 {
 152                         #address-cells = <1>;
 153                         #size-cells = <0>;
 154                         reg = <4>;
 155                         rtc@51 {
 156                                 compatible = "nxp,pcf8563";
 157                                 reg = <0x51>;
 158                         };
 159                 };
 160
 161                 i2c@7 {
 162                         #address-cells = <1>;
 163                         #size-cells = <0>;
 164                         reg = <7>;
 165                         hwmon@52 {
 166                                 compatible = "ti,ucd9248";
 167                                 reg = <52>;
 168                         };
 169                         hwmon@53 {
 170                                 compatible = "ti,ucd9248";
 171                                 reg = <53>;
 172                         };
 173                         hwmon@54 {
 174                                 compatible = "ti,ucd9248";
 175                                 reg = <54>;
 176                         };
 177                 };
 178         };
 179 };
 180
 181 &pinctrl0 {
 182         pinctrl_can0_default: can0-default {
 183                 mux {
 184                         function = "can0";
 185                         groups = "can0_9_grp";
 186                 };
 187
 188                 conf {
 189                         groups = "can0_9_grp";
 190                         slew-rate = <0>;
 191                         io-standard = <1>;
 192                 };
 193
 194                 conf-rx {
 195                         pins = "MIO46";
 196                         bias-high-impedance;
 197                 };
 198
 199                 conf-tx {
 200                         pins = "MIO47";
 201                         bias-disable;
 202                 };
 203         };
 204
 205         pinctrl_gem0_default: gem0-default {
 206                 mux {
 207                         function = "ethernet0";
 208                         groups = "ethernet0_0_grp";
 209                 };
 210
 211                 conf {
 212                         groups = "ethernet0_0_grp";
 213                         slew-rate = <0>;
 214                         io-standard = <4>;
 215                 };
 216
 217                 conf-rx {
 218                         pins = "MIO22", "MIO23", "MIO24", "MIO25", "MIO26", "MIO27";
 219                         bias-high-impedance;
 220                         low-power-disable;
 221                 };
 222
 223                 conf-tx {
 224                         pins = "MIO16", "MIO17", "MIO18", "MIO19", "MIO20", "MIO21";
 225                         bias-disable;
 226                         low-power-enable;
 227                 };
 228
 229                 mux-mdio {
 230                         function = "mdio0";
 231                         groups = "mdio0_0_grp";
 232                 };
 233
 234                 conf-mdio {
 235                         groups = "mdio0_0_grp";
 236                         slew-rate = <0>;
 237                         io-standard = <1>;
 238                         bias-disable;
 239                 };
 240         };
 241
 242         pinctrl_gpio0_default: gpio0-default {
 243                 mux {
 244                         function = "gpio0";
 245                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 246                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 247                                  "gpio0_13_grp", "gpio0_14_grp";
 248                 };
 249
 250                 conf {
 251                         groups = "gpio0_7_grp", "gpio0_8_grp", "gpio0_9_grp",
 252                                  "gpio0_10_grp", "gpio0_11_grp", "gpio0_12_grp",
 253                                  "gpio0_13_grp", "gpio0_14_grp";
 254                         slew-rate = <0>;
 255                         io-standard = <1>;
 256                 };
 257
 258                 conf-pull-up {
 259                         pins = "MIO9", "MIO10", "MIO11", "MIO12", "MIO13", "MIO14";
 260                         bias-pull-up;
 261                 };
 262
 263                 conf-pull-none {
 264                         pins = "MIO7", "MIO8";
 265                         bias-disable;
 266                 };
 267         };
 268
 269         pinctrl_i2c0_default: i2c0-default {
 270                 mux {
 271                         groups = "i2c0_10_grp";
 272                         function = "i2c0";
 273                 };
 274
 275                 conf {
 276                         groups = "i2c0_10_grp";
 277                         bias-pull-up;
 278                         slew-rate = <0>;
 279                         io-standard = <1>;
 280                 };
 281         };
 282
 283         pinctrl_sdhci0_default: sdhci0-default {
 284                 mux {
 285                         groups = "sdio0_2_grp";
 286                         function = "sdio0";
 287                 };
 288
 289                 conf {
 290                         groups = "sdio0_2_grp";
 291                         slew-rate = <0>;
 292                         io-standard = <1>;
 293                         bias-disable;
 294                 };
 295
 296                 mux-cd {
 297                         groups = "gpio0_0_grp";
 298                         function = "sdio0_cd";
 299                 };
 300
 301                 conf-cd {
 302                         groups = "gpio0_0_grp";
 303                         bias-high-impedance;
 304                         bias-pull-up;
 305                         slew-rate = <0>;
 306                         io-standard = <1>;
 307                 };
 308
 309                 mux-wp {
 310                         groups = "gpio0_15_grp";
 311                         function = "sdio0_wp";
 312                 };
 313
 314                 conf-wp {
 315                         groups = "gpio0_15_grp";
 316                         bias-high-impedance;
 317                         bias-pull-up;
 318                         slew-rate = <0>;
 319                         io-standard = <1>;
 320                 };
 321         };
 322
 323         pinctrl_uart1_default: uart1-default {
 324                 mux {
 325                         groups = "uart1_10_grp";
 326                         function = "uart1";
 327                 };
 328
 329                 conf {
 330                         groups = "uart1_10_grp";
 331                         slew-rate = <0>;
 332                         io-standard = <1>;
 333                 };
 334
 335                 conf-rx {
 336                         pins = "MIO49";
 337                         bias-high-impedance;
 338                 };
 339
 340                 conf-tx {
 341                         pins = "MIO48";
 342                         bias-disable;
 343                 };
 344         };
 345
 346         pinctrl_usb0_default: usb0-default {
 347                 mux {
 348                         groups = "usb0_0_grp";
 349                         function = "usb0";
 350                 };
 351
 352                 conf {
 353                         groups = "usb0_0_grp";
 354                         slew-rate = <0>;
 355                         io-standard = <1>;
 356                 };
 357
 358                 conf-rx {
 359                         pins = "MIO29", "MIO31", "MIO36";
 360                         bias-high-impedance;
 361                 };
 362
 363                 conf-tx {
 364                         pins = "MIO28", "MIO30", "MIO32", "MIO33", "MIO34",
 365                                "MIO35", "MIO37", "MIO38", "MIO39";
 366                         bias-disable;
 367                 };
 368         };
 369 };
 370
 371 &sdhci0 {
 372         status = "okay";
 373         pinctrl-names = "default";
 374         pinctrl-0 = <&pinctrl_sdhci0_default>;
 375 };
 376
 377 &uart1 {
 378         status = "okay";
 379         pinctrl-names = "default";
 380         pinctrl-0 = <&pinctrl_uart1_default>;
 381 };
 382
 383 &usb0 {
 384         status = "okay";
 385         dr_mode = "host";
 386         usb-phy = <&usb_phy0>;
 387         pinctrl-names = "default";
 388         pinctrl-0 = <&pinctrl_usb0_default>;
 389 };