6 * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR /PURPOSE. See the
16 * GNU General Public License for more details.
19 #ifndef _CLOCKS_AM33XX_H_
20 #define _CLOCKS_AM33XX_H_
25 #ifndef CONFIG_SYS_MPU_CLK
26 /* default to 500 MHz */
29 #define MPUPLL_M CONFIG_SYS_MPU_CLK
34 /* Core PLL Fdll = 1 GHZ, */
35 #define COREPLL_M 1000
38 #define COREPLL_M4 10 /* CORE_CLKOUTM4 = 200 MHZ */
39 #define COREPLL_M5 8 /* CORE_CLKOUTM5 = 250 MHZ */
40 #define COREPLL_M6 4 /* CORE_CLKOUTM6 = 500 MHZ */
43 * USB PHY clock is 960 MHZ. Since, this comes directly from Fdll, Fdll
44 * frequency needs to be set to 960 MHZ. Hence,
45 * For clkout = 192 MHZ, Fdll = 960 MHZ, divider values are given below
51 /* DDR Freq is 266 MHZ for now */
52 /* Set Fdll = 400 MHZ , Fdll = M * 2 * CLKINP/ N + 1; clkout = Fdll /(2 * M2) */
53 #ifndef CONFIG_SYS_DDR_CLK
56 #define DDRPLL_M CONFIG_SYS_DDR_CLK
65 extern void pll_init(void);
66 extern void enable_emif_clocks(void);
68 #endif /* endif _CLOCKS_AM33XX_H_ */