arch/arm/include/asm/arch-am33xx/hardware_am33xx.h

   1 /*
   2  * hardware_am33xx.h
   3  *
   4  * AM33xx hardware specific header
   5  *
   6  * Copyright (C) 2013, Texas Instruments, Incorporated - http://www.ti.com/
   7  *
   8  * SPDX-License-Identifier:     GPL-2.0+
   9  */
  10
  11 #ifndef __AM33XX_HARDWARE_AM33XX_H
  12 #define __AM33XX_HARDWARE_AM33XX_H
  13
  14 /* Module base addresses */
  15
  16 /* UART Base Address */
  17 #define UART0_BASE                      0x44E09000
  18
  19 /* GPIO Base address */
  20 #define GPIO2_BASE                      0x481AC000
  21
  22 /* Watchdog Timer */
  23 #define WDT_BASE                        0x44E35000
  24
  25 /* Control Module Base Address */
  26 #define CTRL_BASE                       0x44E10000
  27 #define CTRL_DEVICE_BASE                0x44E10600
  28
  29 /* PRCM Base Address */
  30 #define PRCM_BASE                       0x44E00000
  31 #define CM_PER                          0x44E00000
  32 #define CM_WKUP                         0x44E00400
  33 #define CM_DPLL                         0x44E00500
  34 #define CM_RTC                          0x44E00800
  35
  36 #define PRM_RSTCTRL                     (PRCM_BASE + 0x0F00)
  37 #define PRM_RSTST                       (PRM_RSTCTRL + 8)
  38
  39 /* VTP Base address */
  40 #define VTP0_CTRL_ADDR                  0x44E10E0C
  41 #define VTP1_CTRL_ADDR                  0x48140E10
  42
  43 /* DDR Base address */
  44 #define DDR_PHY_CMD_ADDR                0x44E12000
  45 #define DDR_PHY_DATA_ADDR               0x44E120C8
  46 #define DDR_PHY_CMD_ADDR2               0x47C0C800
  47 #define DDR_PHY_DATA_ADDR2              0x47C0C8C8
  48 #define DDR_DATA_REGS_NR                2
  49
  50 #define DDRPHY_0_CONFIG_BASE            (CTRL_BASE + 0x1400)
  51 #define DDRPHY_CONFIG_BASE              DDRPHY_0_CONFIG_BASE
  52
  53 /* CPSW Config space */
  54 #define CPSW_MDIO_BASE                  0x4A101000
  55
  56 /* RTC base address */
  57 #define RTC_BASE                        0x44E3E000
  58
  59 /* OTG */
  60 #define USB0_OTG_BASE                   0x47401000
  61 #define USB1_OTG_BASE                   0x47401800
  62
  63 /* LCD Controller */
  64 #define LCD_CNTL_BASE                   0x4830E000
  65
  66 /* PWMSS */
  67 #define PWMSS0_BASE                     0x48300000
  68 #define AM33XX_ECAP0_BASE               0x48300100
  69
  70 #endif /* __AM33XX_HARDWARE_AM33XX_H */