arch/arm/include/asm/arch-keystone/hardware-k2hk.h

   1 /*
   2  * K2HK: SoC definitions
   3  *
   4  * (C) Copyright 2012-2014
   5  *     Texas Instruments Incorporated, <www.ti.com>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9 #ifndef __ASM_ARCH_HARDWARE_K2HK_H
  10 #define __ASM_ARCH_HARDWARE_K2HK_H
  11
  12 #define K2HK_PLL_CNTRL_BASE             0x02310000
  13 #define CLOCK_BASE                      K2HK_PLL_CNTRL_BASE
  14 #define KS2_RSTCTRL                     (K2HK_PLL_CNTRL_BASE + 0xe8)
  15 #define KS2_RSTCTRL_KEY                 0x5a69
  16 #define KS2_RSTCTRL_MASK                0xffff0000
  17 #define KS2_RSTCTRL_SWRST               0xfffe0000
  18
  19 #define K2HK_PSC_BASE                   0x02350000
  20 #define KS2_DEVICE_STATE_CTRL_BASE      0x02620000
  21 #define JTAG_ID_REG                     (KS2_DEVICE_STATE_CTRL_BASE + 0x18)
  22 #define K2HK_DEVSTAT                    (KS2_DEVICE_STATE_CTRL_BASE + 0x20)
  23
  24 #define K2HK_MISC_CTRL                  (KS2_DEVICE_STATE_CTRL_BASE + 0xc7c)
  25
  26 #define ARM_PLL_EN                      BIT(13)
  27
  28 #define K2HK_SPI0_BASE                  0x21000400
  29 #define K2HK_SPI1_BASE                  0x21000600
  30 #define K2HK_SPI2_BASE                  0x21000800
  31 #define K2HK_SPI_BASE                   K2HK_SPI0_BASE
  32
  33 /* Chip configuration unlock codes and registers */
  34 #define KEYSTONE_KICK0                 (KS2_DEVICE_STATE_CTRL_BASE + 0x38)
  35 #define KEYSTONE_KICK1                 (KS2_DEVICE_STATE_CTRL_BASE + 0x3c)
  36 #define KEYSTONE_KICK0_MAGIC           0x83e70b13
  37 #define KEYSTONE_KICK1_MAGIC           0x95a4f1e0
  38
  39 /* PA SS Registers */
  40 #define KS2_PASS_BASE                  0x02000000
  41
  42 /* PLL control registers */
  43 #define K2HK_MAINPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x350)
  44 #define K2HK_MAINPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x354)
  45 #define K2HK_PASSPLLCTL0               (KS2_DEVICE_STATE_CTRL_BASE + 0x358)
  46 #define K2HK_PASSPLLCTL1               (KS2_DEVICE_STATE_CTRL_BASE + 0x35C)
  47 #define K2HK_DDR3APLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x360)
  48 #define K2HK_DDR3APLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x364)
  49 #define K2HK_DDR3BPLLCTL0              (KS2_DEVICE_STATE_CTRL_BASE + 0x368)
  50 #define K2HK_DDR3BPLLCTL1              (KS2_DEVICE_STATE_CTRL_BASE + 0x36C)
  51 #define K2HK_ARMPLLCTL0                (KS2_DEVICE_STATE_CTRL_BASE + 0x370)
  52 #define K2HK_ARMPLLCTL1                (KS2_DEVICE_STATE_CTRL_BASE + 0x374)
  53
  54 /* Power and Sleep Controller (PSC) Domains */
  55 #define K2HK_LPSC_MOD                  0
  56 #define K2HK_LPSC_DUMMY1               1
  57 #define K2HK_LPSC_USB                  2
  58 #define K2HK_LPSC_EMIF25_SPI           3
  59 #define K2HK_LPSC_TSIP                 4
  60 #define K2HK_LPSC_DEBUGSS_TRC          5
  61 #define K2HK_LPSC_TETB_TRC             6
  62 #define K2HK_LPSC_PKTPROC              7
  63 #define KS2_LPSC_PA                    K2HK_LPSC_PKTPROC
  64 #define K2HK_LPSC_SGMII                8
  65 #define KS2_LPSC_CPGMAC                K2HK_LPSC_SGMII
  66 #define K2HK_LPSC_CRYPTO               9
  67 #define K2HK_LPSC_PCIE                 10
  68 #define K2HK_LPSC_SRIO                 11
  69 #define K2HK_LPSC_VUSR0                12
  70 #define K2HK_LPSC_CHIP_SRSS            13
  71 #define K2HK_LPSC_MSMC                 14
  72 #define K2HK_LPSC_GEM_0                15
  73 #define K2HK_LPSC_GEM_1                16
  74 #define K2HK_LPSC_GEM_2                17
  75 #define K2HK_LPSC_GEM_3                18
  76 #define K2HK_LPSC_GEM_4                19
  77 #define K2HK_LPSC_GEM_5                20
  78 #define K2HK_LPSC_GEM_6                21
  79 #define K2HK_LPSC_GEM_7                22
  80 #define K2HK_LPSC_EMIF4F_DDR3A         23
  81 #define K2HK_LPSC_EMIF4F_DDR3B         24
  82 #define K2HK_LPSC_TAC                  25
  83 #define K2HK_LPSC_RAC                  26
  84 #define K2HK_LPSC_RAC_1                27
  85 #define K2HK_LPSC_FFTC_A               28
  86 #define K2HK_LPSC_FFTC_B               29
  87 #define K2HK_LPSC_FFTC_C               30
  88 #define K2HK_LPSC_FFTC_D               31
  89 #define K2HK_LPSC_FFTC_E               32
  90 #define K2HK_LPSC_FFTC_F               33
  91 #define K2HK_LPSC_AI2                  34
  92 #define K2HK_LPSC_TCP3D_0              35
  93 #define K2HK_LPSC_TCP3D_1              36
  94 #define K2HK_LPSC_TCP3D_2              37
  95 #define K2HK_LPSC_TCP3D_3              38
  96 #define K2HK_LPSC_VCP2X4_A             39
  97 #define K2HK_LPSC_CP2X4_B              40
  98 #define K2HK_LPSC_VCP2X4_C             41
  99 #define K2HK_LPSC_VCP2X4_D             42
 100 #define K2HK_LPSC_VCP2X4_E             43
 101 #define K2HK_LPSC_VCP2X4_F             44
 102 #define K2HK_LPSC_VCP2X4_G             45
 103 #define K2HK_LPSC_VCP2X4_H             46
 104 #define K2HK_LPSC_BCP                  47
 105 #define K2HK_LPSC_DXB                  48
 106 #define K2HK_LPSC_VUSR1                49
 107 #define K2HK_LPSC_XGE                  50
 108 #define K2HK_LPSC_ARM_SREFLEX          51
 109 #define K2HK_LPSC_TETRIS               52
 110
 111 /* DDR3A definitions */
 112 #define K2HK_DDR3A_EMIF_CTRL_BASE      0x21010000
 113 #define K2HK_DDR3A_EMIF_DATA_BASE      0x80000000
 114 #define K2HK_DDR3A_DDRPHYC             0x02329000
 115 /* DDR3B definitions */
 116 #define K2HK_DDR3B_EMIF_CTRL_BASE      0x21020000
 117 #define K2HK_DDR3B_EMIF_DATA_BASE      0x60000000
 118 #define K2HK_DDR3B_DDRPHYC             0x02328000
 119
 120 /* Queue manager */
 121 #define DEVICE_QM_MANAGER_BASE         0x02a02000
 122 #define DEVICE_QM_DESC_SETUP_BASE      0x02a03000
 123 #define DEVICE_QM_MANAGER_QUEUES_BASE  0x02a80000
 124 #define DEVICE_QM_MANAGER_Q_PROXY_BASE 0x02ac0000
 125 #define DEVICE_QM_QUEUE_STATUS_BASE    0x02a40000
 126 #define DEVICE_QM_NUM_LINKRAMS         2
 127 #define DEVICE_QM_NUM_MEMREGIONS       20
 128
 129 #define DEVICE_PA_CDMA_GLOBAL_CFG_BASE  0x02004000
 130 #define DEVICE_PA_CDMA_TX_CHAN_CFG_BASE 0x02004400
 131 #define DEVICE_PA_CDMA_RX_CHAN_CFG_BASE 0x02004800
 132 #define DEVICE_PA_CDMA_RX_FLOW_CFG_BASE 0x02005000
 133
 134 #define DEVICE_PA_CDMA_RX_NUM_CHANNELS  24
 135 #define DEVICE_PA_CDMA_RX_NUM_FLOWS     32
 136 #define DEVICE_PA_CDMA_TX_NUM_CHANNELS  9
 137
 138 /* MSMC control */
 139 #define K2HK_MSMC_CTRL_BASE             0x0bc00000
 140
 141 #endif /* __ASM_ARCH_HARDWARE_H */