2 * Copyright 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ARCH_ARM_MACH_MX6_CCM_REGS_H__
8 #define __ARCH_ARM_MACH_MX6_CCM_REGS_H__
10 #define CCM_CCOSR 0x020c4060
11 #define CCM_CCGR0 0x020C4068
12 #define CCM_CCGR1 0x020C406c
13 #define CCM_CCGR2 0x020C4070
14 #define CCM_CCGR3 0x020C4074
15 #define CCM_CCGR4 0x020C4078
16 #define CCM_CCGR5 0x020C407c
17 #define CCM_CCGR6 0x020C4080
19 #define PMU_MISC2 0x020C8170
27 u32 cacrr; /* 0x0010*/
31 u32 cscmr2; /* 0x0020 */
35 u32 cdcdr; /* 0x0030 */
39 u32 cscdr4; /* 0x0040 */
43 u32 ctor; /* 0x0050 */
47 u32 ccosr; /* 0x0060 */
51 u32 CCGR2; /* 0x0070 */
55 u32 CCGR6; /* 0x0080 */
59 u32 analog_pll_sys; /* 0x4000 */
60 u32 analog_pll_sys_set;
61 u32 analog_pll_sys_clr;
62 u32 analog_pll_sys_tog;
63 u32 analog_usb1_pll_480_ctrl; /* 0x4010 */
64 u32 analog_usb1_pll_480_ctrl_set;
65 u32 analog_usb1_pll_480_ctrl_clr;
66 u32 analog_usb1_pll_480_ctrl_tog;
67 u32 analog_reserved0[4];
68 u32 analog_pll_528; /* 0x4030 */
69 u32 analog_pll_528_set;
70 u32 analog_pll_528_clr;
71 u32 analog_pll_528_tog;
72 u32 analog_pll_528_ss; /* 0x4040 */
73 u32 analog_reserved1[3];
74 u32 analog_pll_528_num; /* 0x4050 */
75 u32 analog_reserved2[3];
76 u32 analog_pll_528_denom; /* 0x4060 */
77 u32 analog_reserved3[3];
78 u32 analog_pll_audio; /* 0x4070 */
79 u32 analog_pll_audio_set;
80 u32 analog_pll_audio_clr;
81 u32 analog_pll_audio_tog;
82 u32 analog_pll_audio_num; /* 0x4080*/
83 u32 analog_reserved4[3];
84 u32 analog_pll_audio_denom; /* 0x4090 */
85 u32 analog_reserved5[3];
86 u32 analog_pll_video; /* 0x40a0 */
87 u32 analog_pll_video_set;
88 u32 analog_pll_video_clr;
89 u32 analog_pll_video_tog;
90 u32 analog_pll_video_num; /* 0x40b0 */
91 u32 analog_reserved6[3];
92 u32 analog_pll_vedio_denon; /* 0x40c0 */
93 u32 analog_reserved7[7];
94 u32 analog_pll_enet; /* 0x40e0 */
95 u32 analog_pll_enet_set;
96 u32 analog_pll_enet_clr;
97 u32 analog_pll_enet_tog;
98 u32 analog_pfd_480; /* 0x40f0 */
99 u32 analog_pfd_480_set;
100 u32 analog_pfd_480_clr;
101 u32 analog_pfd_480_tog;
102 u32 analog_pfd_528; /* 0x4100 */
103 u32 analog_pfd_528_set;
104 u32 analog_pfd_528_clr;
105 u32 analog_pfd_528_tog;
109 /* Define the bits in register CCR */
110 #define MXC_CCM_CCR_RBC_EN (1 << 27)
111 #define MXC_CCM_CCR_REG_BYPASS_CNT_MASK (0x3F << 21)
112 #define MXC_CCM_CCR_REG_BYPASS_CNT_OFFSET 21
113 #define MXC_CCM_CCR_WB_COUNT_MASK 0x7
114 #define MXC_CCM_CCR_WB_COUNT_OFFSET (1 << 16)
115 #define MXC_CCM_CCR_COSC_EN (1 << 12)
117 #define MXC_CCM_CCR_OSCNT_MASK 0x7F
119 #define MXC_CCM_CCR_OSCNT_MASK 0xFF
121 #define MXC_CCM_CCR_OSCNT_OFFSET 0
123 /* Define the bits in register CCDR */
124 #define MXC_CCM_CCDR_MMDC_CH1_HS_MASK (1 << 16)
125 #define MXC_CCM_CCDR_MMDC_CH0_HS_MASK (1 << 17)
127 /* Define the bits in register CSR */
128 #define MXC_CCM_CSR_COSC_READY (1 << 5)
129 #define MXC_CCM_CSR_REF_EN_B (1 << 0)
131 /* Define the bits in register CCSR */
132 #define MXC_CCM_CCSR_PDF_540M_AUTO_DIS (1 << 15)
133 #define MXC_CCM_CCSR_PDF_720M_AUTO_DIS (1 << 14)
134 #define MXC_CCM_CCSR_PDF_454M_AUTO_DIS (1 << 13)
135 #define MXC_CCM_CCSR_PDF_508M_AUTO_DIS (1 << 12)
136 #define MXC_CCM_CCSR_PDF_594M_AUTO_DIS (1 << 11)
137 #define MXC_CCM_CCSR_PDF_352M_AUTO_DIS (1 << 10)
138 #define MXC_CCM_CCSR_PDF_400M_AUTO_DIS (1 << 9)
139 #define MXC_CCM_CCSR_STEP_SEL (1 << 8)
140 #define MXC_CCM_CCSR_PLL1_SW_CLK_SEL (1 << 2)
141 #define MXC_CCM_CCSR_PLL2_SW_CLK_SEL (1 << 1)
142 #define MXC_CCM_CCSR_PLL3_SW_CLK_SEL (1 << 0)
144 /* Define the bits in register CACRR */
145 #define MXC_CCM_CACRR_ARM_PODF_OFFSET 0
146 #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
148 /* Define the bits in register CBCDR */
149 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_MASK (0x7 << 27)
150 #define MXC_CCM_CBCDR_PERIPH_CLK2_PODF_OFFSET 27
151 #define MXC_CCM_CBCDR_PERIPH2_CLK2_SEL (1 << 26)
152 #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (1 << 25)
154 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_MASK (0x7 << 19)
155 #define MXC_CCM_CBCDR_MMDC_CH0_PODF_OFFSET 19
157 #define MXC_CCM_CBCDR_AXI_PODF_MASK (0x7 << 16)
158 #define MXC_CCM_CBCDR_AXI_PODF_OFFSET 16
159 #define MXC_CCM_CBCDR_AHB_PODF_MASK (0x7 << 10)
160 #define MXC_CCM_CBCDR_AHB_PODF_OFFSET 10
161 #define MXC_CCM_CBCDR_IPG_PODF_MASK (0x3 << 8)
162 #define MXC_CCM_CBCDR_IPG_PODF_OFFSET 8
163 #define MXC_CCM_CBCDR_AXI_ALT_SEL (1 << 7)
164 #define MXC_CCM_CBCDR_AXI_SEL (1 << 6)
165 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_MASK (0x7 << 3)
166 #define MXC_CCM_CBCDR_MMDC_CH1_PODF_OFFSET 3
167 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_MASK (0x7 << 0)
168 #define MXC_CCM_CBCDR_PERIPH2_CLK2_PODF_OFFSET 0
170 /* Define the bits in register CBCMR */
171 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_MASK (0x7 << 29)
172 #define MXC_CCM_CBCMR_GPU3D_SHADER_PODF_OFFSET 29
173 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_MASK (0x7 << 26)
174 #define MXC_CCM_CBCMR_GPU3D_CORE_PODF_OFFSET 26
175 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_MASK (0x7 << 23)
176 #define MXC_CCM_CBCMR_GPU2D_CORE_PODF_OFFSET 23
177 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_MASK (0x3 << 21)
178 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK_SEL_OFFSET 21
179 #define MXC_CCM_CBCMR_PRE_PERIPH2_CLK2_SEL (1 << 20)
180 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_MASK (0x3 << 18)
181 #define MXC_CCM_CBCMR_PRE_PERIPH_CLK_SEL_OFFSET 18
183 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_MASK (0x3 << 16)
184 #define MXC_CCM_CBCMR_GPU2D_CLK_SEL_OFFSET 16
185 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_MASK (0x3 << 14)
186 #define MXC_CCM_CBCMR_VPU_AXI_CLK_SEL_OFFSET 14
188 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_MASK (0x3 << 12)
189 #define MXC_CCM_CBCMR_PERIPH_CLK2_SEL_OFFSET 12
191 #define MXC_CCM_CBCMR_VDOAXI_CLK_SEL (1 << 11)
193 #define MXC_CCM_CBCMR_PCIE_AXI_CLK_SEL (1 << 10)
194 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_MASK (0x3 << 8)
195 #define MXC_CCM_CBCMR_GPU3D_SHADER_CLK_SEL_OFFSET 8
196 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_MASK (0x3 << 4)
197 #define MXC_CCM_CBCMR_GPU3D_CORE_CLK_SEL_OFFSET 4
199 #define MXC_CCM_CBCMR_GPU3D_AXI_CLK_SEL (1 << 1)
200 #define MXC_CCM_CBCMR_GPU2D_AXI_CLK_SEL (1 << 0)
203 /* Define the bits in register CSCMR1 */
204 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_MASK (0x3 << 29)
205 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_OFFSET 29
207 #define MXC_CCM_CSCMR1_QSPI1_PODF_MASK (0x7 << 26)
208 #define MXC_CCM_CSCMR1_QSPI1_PODF_OFFSET 26
210 #define MXC_CCM_CSCMR1_ACLK_EMI_MASK (0x3 << 27)
211 #define MXC_CCM_CSCMR1_ACLK_EMI_OFFSET 27
213 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_MASK (0x7 << 23)
214 #define MXC_CCM_CSCMR1_ACLK_EMI_SLOW_PODF_OFFSET 23
215 /* ACLK_EMI_PODF is LCFIF2_PODF on MX6SX */
216 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_MASK (0x7 << 20)
217 #define MXC_CCM_CSCMR1_ACLK_EMI_PODF_OFFSET 20
218 #define MXC_CCM_CSCMR1_USDHC4_CLK_SEL (1 << 19)
219 #define MXC_CCM_CSCMR1_USDHC3_CLK_SEL (1 << 18)
220 #define MXC_CCM_CSCMR1_USDHC2_CLK_SEL (1 << 17)
221 #define MXC_CCM_CSCMR1_USDHC1_CLK_SEL (1 << 16)
222 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_MASK (0x3 << 14)
223 #define MXC_CCM_CSCMR1_SSI3_CLK_SEL_OFFSET 14
224 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_MASK (0x3 << 12)
225 #define MXC_CCM_CSCMR1_SSI2_CLK_SEL_OFFSET 12
226 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_MASK (0x3 << 10)
227 #define MXC_CCM_CSCMR1_SSI1_CLK_SEL_OFFSET 10
229 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_MASK (0x7 << 7)
230 #define MXC_CCM_CSCMR1_QSPI1_CLK_SEL_OFFSET 7
231 #define MXC_CCM_CSCMR1_PER_CLK_SEL_MASK (1 << 6)
232 #define MXC_CCM_CSCMR1_PER_CLK_SEL_OFFSET 6
234 #define MXC_CCM_CSCMR1_PERCLK_PODF_MASK 0x3F
236 /* Define the bits in register CSCMR2 */
238 #define MXC_CCM_CSCMR2_VID_CLK_SEL_MASK (0x7 << 21)
239 #define MXC_CCM_CSCMR2_VID_CLK_SEL_OFFSET 21
241 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_MASK (0x3 << 19)
242 #define MXC_CCM_CSCMR2_ESAI_PRE_SEL_OFFSET 19
243 #define MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV (1 << 11)
244 #define MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV (1 << 10)
246 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3 << 8)
247 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 8
248 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_MASK (0x3F << 2)
249 #define MXC_CCM_CSCMR2_CAN_CLK_PODF_OFFSET 2
251 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_MASK (0x3F << 2)
252 #define MXC_CCM_CSCMR2_CAN_CLK_SEL_OFFSET 2
255 /* Define the bits in register CSCDR1 */
257 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_MASK (0x7 << 25)
258 #define MXC_CCM_CSCDR1_VPU_AXI_PODF_OFFSET 25
260 #define MXC_CCM_CSCDR1_USDHC4_PODF_MASK (0x7 << 22)
261 #define MXC_CCM_CSCDR1_USDHC4_PODF_OFFSET 22
262 #define MXC_CCM_CSCDR1_USDHC3_PODF_MASK (0x7 << 19)
263 #define MXC_CCM_CSCDR1_USDHC3_PODF_OFFSET 19
264 #define MXC_CCM_CSCDR1_USDHC2_PODF_MASK (0x7 << 16)
265 #define MXC_CCM_CSCDR1_USDHC2_PODF_OFFSET 16
266 #define MXC_CCM_CSCDR1_USDHC1_PODF_MASK (0x7 << 11)
267 #define MXC_CCM_CSCDR1_USDHC1_PODF_OFFSET 11
269 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_OFFSET 8
270 #define MXC_CCM_CSCDR1_USBOH3_CLK_PRED_MASK (0x7 << 8)
271 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_OFFSET 6
272 #define MXC_CCM_CSCDR1_USBOH3_CLK_PODF_MASK (0x3 << 6)
275 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x1F
276 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
278 #define MXC_CCM_CSCDR1_UART_CLK_PODF_MASK 0x3F
280 #define MXC_CCM_CSCDR1_UART_CLK_SEL (1 << 6)
283 #define MXC_CCM_CSCDR1_UART_CLK_PODF_OFFSET 0
285 /* Define the bits in register CS1CDR */
286 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_MASK (0x3F << 25)
287 #define MXC_CCM_CS1CDR_ESAI_CLK_PODF_OFFSET 25
288 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_MASK (0x7 << 22)
289 #define MXC_CCM_CS1CDR_SSI3_CLK_PRED_OFFSET 22
290 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_MASK (0x3F << 16)
291 #define MXC_CCM_CS1CDR_SSI3_CLK_PODF_OFFSET 16
292 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_MASK (0x3 << 9)
293 #define MXC_CCM_CS1CDR_ESAI_CLK_PRED_OFFSET 9
294 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_MASK (0x7 << 6)
295 #define MXC_CCM_CS1CDR_SSI1_CLK_PRED_OFFSET 6
296 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_MASK 0x3F
297 #define MXC_CCM_CS1CDR_SSI1_CLK_PODF_OFFSET 0
299 /* Define the bits in register CS2CDR */
301 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_MASK (0x3F << 21)
302 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF_OFFSET 21
303 #define MXC_CCM_CS2CDR_QSPI2_CLK_PODF(v) (((v) & 0x3f) << 21)
304 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_MASK (0x7 << 18)
305 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED_OFFSET 18
306 #define MXC_CCM_CS2CDR_QSPI2_CLK_PRED(v) (((v) & 0x7) << 18)
307 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_MASK (0x7 << 15)
308 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL_OFFSET 15
309 #define MXC_CCM_CS2CDR_QSPI2_CLK_SEL(v) (((v) & 0x7) << 15)
311 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_MASK (0x3F << 21)
312 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF_OFFSET 21
313 #define MXC_CCM_CS2CDR_ENFC_CLK_PODF(v) (((v) & 0x3f) << 21)
314 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_MASK (0x7 << 18)
315 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED_OFFSET 18
316 #define MXC_CCM_CS2CDR_ENFC_CLK_PRED(v) (((v) & 0x7) << 18)
317 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_MASK (0x3 << 16)
318 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL_OFFSET 16
319 #define MXC_CCM_CS2CDR_ENFC_CLK_SEL(v) (((v) & 0x3) << 16)
321 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK (0x7 << 12)
322 #define MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET 12
323 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK (0x7 << 9)
324 #define MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET 9
325 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_MASK (0x7 << 6)
326 #define MXC_CCM_CS2CDR_SSI2_CLK_PRED_OFFSET 6
327 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_MASK 0x3F
328 #define MXC_CCM_CS2CDR_SSI2_CLK_PODF_OFFSET 0
330 /* Define the bits in register CDCDR */
332 #define MXC_CCM_CDCDR_HSI_TX_PODF_MASK (0x7 << 29)
333 #define MXC_CCM_CDCDR_HSI_TX_PODF_OFFSET 29
334 #define MXC_CCM_CDCDR_HSI_TX_CLK_SEL (1 << 28)
336 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_MASK (0x7 << 25)
337 #define MXC_CCM_CDCDR_SPDIF0_CLK_PRED_OFFSET 25
338 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_MASK (0x7 << 19)
339 #define MXC_CCM_CDCDR_SPDIF0_CLK_PODF_OFFSET 19
340 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_MASK (0x3 << 20)
341 #define MXC_CCM_CDCDR_SPDIF0_CLK_SEL_OFFSET 20
342 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_MASK (0x7 << 12)
343 #define MXC_CCM_CDCDR_SPDIF1_CLK_PRED_OFFSET 12
344 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_MASK (0x7 << 9)
345 #define MXC_CCM_CDCDR_SPDIF1_CLK_PODF_OFFSET 9
346 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_MASK (0x3 << 7)
347 #define MXC_CCM_CDCDR_SPDIF1_CLK_SEL_OFFSET 7
349 /* Define the bits in register CHSCCDR */
351 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_MASK (0x7 << 15)
352 #define MXC_CCM_CHSCCDR_ENET_PRE_CLK_SEL_OFFSET 15
353 #define MXC_CCM_CHSCCDR_ENET_PODF_MASK (0x7 << 12)
354 #define MXC_CCM_CHSCCDR_ENET_PODF_OFFSET 12
355 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_MASK (0x7 << 9)
356 #define MXC_CCM_CHSCCDR_ENET_CLK_SEL_OFFSET 9
357 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_MASK (0x7 << 6)
358 #define MXC_CCM_CHSCCDR_M4_PRE_CLK_SEL_OFFSET 6
359 #define MXC_CCM_CHSCCDR_M4_PODF_MASK (0x7 << 3)
360 #define MXC_CCM_CHSCCDR_M4_PODF_OFFSET 3
361 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_MASK (0x7)
362 #define MXC_CCM_CHSCCDR_M4_CLK_SEL_OFFSET 0
364 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
365 #define MXC_CCM_CHSCCDR_IPU1_DI1_PRE_CLK_SEL_OFFSET 15
366 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_MASK (0x7 << 12)
367 #define MXC_CCM_CHSCCDR_IPU1_DI1_PODF_OFFSET 12
368 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_MASK (0x7 << 9)
369 #define MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET 9
370 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
371 #define MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET 6
372 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK (0x7 << 3)
373 #define MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET 3
374 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_MASK (0x7)
375 #define MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET 0
378 #define CHSCCDR_CLK_SEL_LDB_DI0 3
379 #define CHSCCDR_PODF_DIVIDE_BY_3 2
380 #define CHSCCDR_IPU_PRE_CLK_540M_PFD 5
382 /* Define the bits in register CSCDR2 */
383 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_MASK (0x3F << 19)
384 #define MXC_CCM_CSCDR2_ECSPI_CLK_PODF_OFFSET 19
385 /* All IPU2_DI1 are LCDIF1 on MX6SX */
386 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_MASK (0x7 << 15)
387 #define MXC_CCM_CHSCCDR_IPU2_DI1_PRE_CLK_SEL_OFFSET 15
388 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_MASK (0x7 << 12)
389 #define MXC_CCM_CHSCCDR_IPU2_DI1_PODF_OFFSET 12
390 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_MASK (0x7 << 9)
391 #define MXC_CCM_CHSCCDR_IPU2_DI1_CLK_SEL_OFFSET 9
392 /* All IPU2_DI0 are LCDIF2 on MX6SX */
393 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_MASK (0x7 << 6)
394 #define MXC_CCM_CHSCCDR_IPU2_DI0_PRE_CLK_SEL_OFFSET 6
395 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_MASK (0x7 << 3)
396 #define MXC_CCM_CHSCCDR_IPU2_DI0_PODF_OFFSET 3
397 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_MASK 0x7
398 #define MXC_CCM_CHSCCDR_IPU2_DI0_CLK_SEL_OFFSET 0
400 /* Define the bits in register CSCDR3 */
401 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_MASK (0x7 << 16)
402 #define MXC_CCM_CSCDR3_IPU2_HSP_PODF_OFFSET 16
403 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_MASK (0x3 << 14)
404 #define MXC_CCM_CSCDR3_IPU2_HSP_CLK_SEL_OFFSET 14
405 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_MASK (0x7 << 11)
406 #define MXC_CCM_CSCDR3_IPU1_HSP_PODF_OFFSET 11
407 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_MASK (0x3 << 9)
408 #define MXC_CCM_CSCDR3_IPU1_HSP_CLK_SEL_OFFSET 9
410 /* Define the bits in register CDHIPR */
411 #define MXC_CCM_CDHIPR_ARM_PODF_BUSY (1 << 16)
412 #define MXC_CCM_CDHIPR_PERIPH_CLK_SEL_BUSY (1 << 5)
414 #define MXC_CCM_CDHIPR_MMDC_CH0_PODF_BUSY (1 << 4)
416 #define MXC_CCM_CDHIPR_PERIPH2_CLK_SEL_BUSY (1 << 3)
417 #define MXC_CCM_CDHIPR_MMDC_CH1_PODF_BUSY (1 << 2)
418 #define MXC_CCM_CDHIPR_AHB_PODF_BUSY (1 << 1)
419 #define MXC_CCM_CDHIPR_AXI_PODF_BUSY 1
421 /* Define the bits in register CLPCR */
422 #define MXC_CCM_CLPCR_MASK_L2CC_IDLE (1 << 27)
423 #define MXC_CCM_CLPCR_MASK_SCU_IDLE (1 << 26)
425 #define MXC_CCM_CLPCR_MASK_CORE3_WFI (1 << 25)
426 #define MXC_CCM_CLPCR_MASK_CORE2_WFI (1 << 24)
427 #define MXC_CCM_CLPCR_MASK_CORE1_WFI (1 << 23)
429 #define MXC_CCM_CLPCR_MASK_CORE0_WFI (1 << 22)
430 #define MXC_CCM_CLPCR_BYP_MMDC_CH1_LPM_HS (1 << 21)
432 #define MXC_CCM_CLPCR_BYP_MMDC_CH0_LPM_HS (1 << 19)
433 #define MXC_CCM_CLPCR_WB_CORE_AT_LPM (1 << 17)
435 #define MXC_CCM_CLPCR_WB_PER_AT_LPM (1 << 17)
436 #define MXC_CCM_CLPCR_COSC_PWRDOWN (1 << 11)
437 #define MXC_CCM_CLPCR_STBY_COUNT_MASK (0x3 << 9)
438 #define MXC_CCM_CLPCR_STBY_COUNT_OFFSET 9
439 #define MXC_CCM_CLPCR_VSTBY (1 << 8)
440 #define MXC_CCM_CLPCR_DIS_REF_OSC (1 << 7)
441 #define MXC_CCM_CLPCR_SBYOS (1 << 6)
442 #define MXC_CCM_CLPCR_ARM_CLK_DIS_ON_LPM (1 << 5)
444 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_MASK (0x3 << 3)
445 #define MXC_CCM_CLPCR_LPSR_CLK_SEL_OFFSET 3
446 #define MXC_CCM_CLPCR_BYPASS_PMIC_VFUNC_READY (1 << 2)
448 #define MXC_CCM_CLPCR_LPM_MASK 0x3
449 #define MXC_CCM_CLPCR_LPM_OFFSET 0
451 /* Define the bits in register CISR */
452 #define MXC_CCM_CISR_ARM_PODF_LOADED (1 << 26)
454 #define MXC_CCM_CISR_MMDC_CH0_PODF_LOADED (1 << 23)
456 #define MXC_CCM_CISR_PERIPH_CLK_SEL_LOADED (1 << 22)
457 #define MXC_CCM_CISR_MMDC_CH1_PODF_LOADED (1 << 21)
458 #define MXC_CCM_CISR_AHB_PODF_LOADED (1 << 20)
459 #define MXC_CCM_CISR_PERIPH2_CLK_SEL_LOADED (1 << 19)
460 #define MXC_CCM_CISR_AXI_PODF_LOADED (1 << 17)
461 #define MXC_CCM_CISR_COSC_READY (1 << 6)
462 #define MXC_CCM_CISR_LRF_PLL 1
464 /* Define the bits in register CIMR */
465 #define MXC_CCM_CIMR_MASK_ARM_PODF_LOADED (1 << 26)
467 #define MXC_CCM_CIMR_MASK_MMDC_CH0_PODF_LOADED (1 << 23)
469 #define MXC_CCM_CIMR_MASK_PERIPH_CLK_SEL_LOADED (1 << 22)
470 #define MXC_CCM_CIMR_MASK_MMDC_CH1_PODF_LOADED (1 << 21)
471 #define MXC_CCM_CIMR_MASK_AHB_PODF_LOADED (1 << 20)
472 #define MXC_CCM_CIMR_MASK_PERIPH2_CLK_SEL_LOADED (1 << 22)
473 #define MXC_CCM_CIMR_MASK_AXI_PODF_LOADED (1 << 17)
474 #define MXC_CCM_CIMR_MASK_COSC_READY (1 << 6)
475 #define MXC_CCM_CIMR_MASK_LRF_PLL 1
477 /* Define the bits in register CCOSR */
478 #define MXC_CCM_CCOSR_CKO2_EN_OFFSET (1 << 24)
479 #define MXC_CCM_CCOSR_CKO2_DIV_MASK (0x7 << 21)
480 #define MXC_CCM_CCOSR_CKO2_DIV_OFFSET 21
481 #define MXC_CCM_CCOSR_CKO2_SEL_OFFSET 16
482 #define MXC_CCM_CCOSR_CKO2_SEL_MASK (0x1F << 16)
483 #define MXC_CCM_CCOSR_CLK_OUT_SEL (0x1 << 8)
484 #define MXC_CCM_CCOSR_CKOL_EN (0x1 << 7)
485 #define MXC_CCM_CCOSR_CKOL_DIV_MASK (0x7 << 4)
486 #define MXC_CCM_CCOSR_CKOL_DIV_OFFSET 4
487 #define MXC_CCM_CCOSR_CKOL_SEL_MASK 0xF
488 #define MXC_CCM_CCOSR_CKOL_SEL_OFFSET 0
490 /* Define the bits in registers CGPR */
491 #define MXC_CCM_CGPR_FAST_PLL_EN (1 << 16)
492 #define MXC_CCM_CGPR_EFUSE_PROG_SUPPLY_GATE (1 << 4)
493 #define MXC_CCM_CGPR_MMDC_EXT_CLK_DIS (1 << 2)
494 #define MXC_CCM_CGPR_PMIC_DELAY_SCALER 1
496 /* Define the bits in registers CCGRx */
497 #define MXC_CCM_CCGR_CG_MASK 3
499 #define MXC_CCM_CCGR0_AIPS_TZ1_OFFSET 0
500 #define MXC_CCM_CCGR0_AIPS_TZ1_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ1_OFFSET)
501 #define MXC_CCM_CCGR0_AIPS_TZ2_OFFSET 2
502 #define MXC_CCM_CCGR0_AIPS_TZ2_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ2_OFFSET)
503 #define MXC_CCM_CCGR0_APBHDMA_OFFSET 4
504 #define MXC_CCM_CCGR0_APBHDMA_MASK (3 << MXC_CCM_CCGR0_APBHDMA_OFFSET)
505 #define MXC_CCM_CCGR0_ASRC_OFFSET 6
506 #define MXC_CCM_CCGR0_ASRC_MASK (3 << MXC_CCM_CCGR0_ASRC_OFFSET)
507 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET 8
508 #define MXC_CCM_CCGR0_CAAM_SECURE_MEM_MASK (3 << MXC_CCM_CCGR0_CAAM_SECURE_MEM_OFFSET)
509 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET 10
510 #define MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_ACLK_OFFSET)
511 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET 12
512 #define MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_MASK (3 << MXC_CCM_CCGR0_CAAM_WRAPPER_IPG_OFFSET)
513 #define MXC_CCM_CCGR0_CAN1_OFFSET 14
514 #define MXC_CCM_CCGR0_CAN1_MASK (3 << MXC_CCM_CCGR0_CAN1_OFFSET)
515 #define MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET 16
516 #define MXC_CCM_CCGR0_CAN1_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN1_SERIAL_OFFSET)
517 #define MXC_CCM_CCGR0_CAN2_OFFSET 18
518 #define MXC_CCM_CCGR0_CAN2_MASK (3 << MXC_CCM_CCGR0_CAN2_OFFSET)
519 #define MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET 20
520 #define MXC_CCM_CCGR0_CAN2_SERIAL_MASK (3 << MXC_CCM_CCGR0_CAN2_SERIAL_OFFSET)
521 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET 22
522 #define MXC_CCM_CCGR0_CHEETAH_DBG_CLK_MASK (3 << MXC_CCM_CCGR0_CHEETAH_DBG_CLK_OFFSET)
523 #define MXC_CCM_CCGR0_DCIC1_OFFSET 24
524 #define MXC_CCM_CCGR0_DCIC1_MASK (3 << MXC_CCM_CCGR0_DCIC1_OFFSET)
525 #define MXC_CCM_CCGR0_DCIC2_OFFSET 26
526 #define MXC_CCM_CCGR0_DCIC2_MASK (3 << MXC_CCM_CCGR0_DCIC2_OFFSET)
528 #define MXC_CCM_CCGR0_AIPS_TZ3_OFFSET 30
529 #define MXC_CCM_CCGR0_AIPS_TZ3_MASK (3 << MXC_CCM_CCGR0_AIPS_TZ3_OFFSET)
531 #define MXC_CCM_CCGR0_DTCP_OFFSET 28
532 #define MXC_CCM_CCGR0_DTCP_MASK (3 << MXC_CCM_CCGR0_DTCP_OFFSET)
535 #define MXC_CCM_CCGR1_ECSPI1S_OFFSET 0
536 #define MXC_CCM_CCGR1_ECSPI1S_MASK (3 << MXC_CCM_CCGR1_ECSPI1S_OFFSET)
537 #define MXC_CCM_CCGR1_ECSPI2S_OFFSET 2
538 #define MXC_CCM_CCGR1_ECSPI2S_MASK (3 << MXC_CCM_CCGR1_ECSPI2S_OFFSET)
539 #define MXC_CCM_CCGR1_ECSPI3S_OFFSET 4
540 #define MXC_CCM_CCGR1_ECSPI3S_MASK (3 << MXC_CCM_CCGR1_ECSPI3S_OFFSET)
541 #define MXC_CCM_CCGR1_ECSPI4S_OFFSET 6
542 #define MXC_CCM_CCGR1_ECSPI4S_MASK (3 << MXC_CCM_CCGR1_ECSPI4S_OFFSET)
543 #define MXC_CCM_CCGR1_ECSPI5S_OFFSET 8
544 #define MXC_CCM_CCGR1_ECSPI5S_MASK (3 << MXC_CCM_CCGR1_ECSPI5S_OFFSET)
546 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET 10
547 #define MXC_CCM_CCGR1_ENET_CLK_ENABLE_MASK (3 << MXC_CCM_CCGR1_ENET_CLK_ENABLE_OFFSET)
549 #define MXC_CCM_CCGR1_EPIT1S_OFFSET 12
550 #define MXC_CCM_CCGR1_EPIT1S_MASK (3 << MXC_CCM_CCGR1_EPIT1S_OFFSET)
551 #define MXC_CCM_CCGR1_EPIT2S_OFFSET 14
552 #define MXC_CCM_CCGR1_EPIT2S_MASK (3 << MXC_CCM_CCGR1_EPIT2S_OFFSET)
553 #define MXC_CCM_CCGR1_ESAIS_OFFSET 16
554 #define MXC_CCM_CCGR1_ESAIS_MASK (3 << MXC_CCM_CCGR1_ESAIS_OFFSET)
556 #define MXC_CCM_CCGR1_WAKEUP_OFFSET 18
557 #define MXC_CCM_CCGR1_WAKEUP_MASK (3 << MXC_CCM_CCGR1_WAKEUP_OFFSET)
559 #define MXC_CCM_CCGR1_GPT_BUS_OFFSET 20
560 #define MXC_CCM_CCGR1_GPT_BUS_MASK (3 << MXC_CCM_CCGR1_GPT_BUS_OFFSET)
561 #define MXC_CCM_CCGR1_GPT_SERIAL_OFFSET 22
562 #define MXC_CCM_CCGR1_GPT_SERIAL_MASK (3 << MXC_CCM_CCGR1_GPT_SERIAL_OFFSET)
564 #define MXC_CCM_CCGR1_GPU2D_OFFSET 24
565 #define MXC_CCM_CCGR1_GPU2D_MASK (3 << MXC_CCM_CCGR1_GPU2D_OFFSET)
567 #define MXC_CCM_CCGR1_GPU3D_OFFSET 26
568 #define MXC_CCM_CCGR1_GPU3D_MASK (3 << MXC_CCM_CCGR1_GPU3D_OFFSET)
570 #define MXC_CCM_CCGR1_OCRAM_S_OFFSET 28
571 #define MXC_CCM_CCGR1_OCRAM_S_MASK (3 << MXC_CCM_CCGR1_OCRAM_S_OFFSET)
572 #define MXC_CCM_CCGR1_CANFD_OFFSET 30
573 #define MXC_CCM_CCGR1_CANFD_MASK (3 << MXC_CCM_CCGR1_CANFD_OFFSET)
577 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET 0
578 #define MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_IAHBCLK_OFFSET)
580 #define MXC_CCM_CCGR2_CSI_OFFSET 2
581 #define MXC_CCM_CCGR2_CSI_MASK (3 << MXC_CCM_CCGR2_CSI_OFFSET)
584 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET 4
585 #define MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_MASK (3 << MXC_CCM_CCGR2_HDMI_TX_ISFRCLK_OFFSET)
587 #define MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET 6
588 #define MXC_CCM_CCGR2_I2C1_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C1_SERIAL_OFFSET)
589 #define MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET 8
590 #define MXC_CCM_CCGR2_I2C2_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C2_SERIAL_OFFSET)
591 #define MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET 10
592 #define MXC_CCM_CCGR2_I2C3_SERIAL_MASK (3 << MXC_CCM_CCGR2_I2C3_SERIAL_OFFSET)
593 #define MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET 12
594 #define MXC_CCM_CCGR2_OCOTP_CTRL_MASK (3 << MXC_CCM_CCGR2_OCOTP_CTRL_OFFSET)
595 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET 14
596 #define MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_MASK (3 << MXC_CCM_CCGR2_IOMUX_IPT_CLK_IO_OFFSET)
597 #define MXC_CCM_CCGR2_IPMUX1_OFFSET 16
598 #define MXC_CCM_CCGR2_IPMUX1_MASK (3 << MXC_CCM_CCGR2_IPMUX1_OFFSET)
599 #define MXC_CCM_CCGR2_IPMUX2_OFFSET 18
600 #define MXC_CCM_CCGR2_IPMUX2_MASK (3 << MXC_CCM_CCGR2_IPMUX2_OFFSET)
601 #define MXC_CCM_CCGR2_IPMUX3_OFFSET 20
602 #define MXC_CCM_CCGR2_IPMUX3_MASK (3 << MXC_CCM_CCGR2_IPMUX3_OFFSET)
603 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET 22
604 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC1_IPGS_OFFSET)
606 #define MXC_CCM_CCGR2_LCD_OFFSET 28
607 #define MXC_CCM_CCGR2_LCD_MASK (3 << MXC_CCM_CCGR2_LCD_OFFSET)
608 #define MXC_CCM_CCGR2_PXP_OFFSET 30
609 #define MXC_CCM_CCGR2_PXP_MASK (3 << MXC_CCM_CCGR2_PXP_OFFSET)
611 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET 24
612 #define MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_MASK (3 << MXC_CCM_CCGR2_IPSYNC_IP2APB_TZASC2_IPG_OFFSET)
613 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET 26
614 #define MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_MASK (3 << MXC_CCM_CCGR2_IPSYNC_VDOA_IPG_MASTER_CLK_OFFSET)
618 #define MXC_CCM_CCGR3_M4_OFFSET 2
619 #define MXC_CCM_CCGR3_M4_MASK (3 << MXC_CCM_CCGR3_M4_OFFSET)
620 #define MXC_CCM_CCGR3_ENET_OFFSET 4
621 #define MXC_CCM_CCGR3_ENET_MASK (3 << MXC_CCM_CCGR3_ENET_OFFSET)
622 #define MXC_CCM_CCGR3_QSPI_OFFSET 14
623 #define MXC_CCM_CCGR3_QSPI_MASK (3 << MXC_CCM_CCGR3_QSPI_OFFSET)
625 #define MXC_CCM_CCGR3_IPU1_IPU_OFFSET 0
626 #define MXC_CCM_CCGR3_IPU1_IPU_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_OFFSET)
627 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET 2
628 #define MXC_CCM_CCGR3_IPU1_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI0_OFFSET)
629 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET 4
630 #define MXC_CCM_CCGR3_IPU1_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU1_IPU_DI1_OFFSET)
632 #define MXC_CCM_CCGR3_IPU2_IPU_OFFSET 6
633 #define MXC_CCM_CCGR3_IPU2_IPU_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_OFFSET)
634 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET 8
635 #define MXC_CCM_CCGR3_IPU2_IPU_DI0_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI0_OFFSET)
636 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET 10
637 #define MXC_CCM_CCGR3_IPU2_IPU_DI1_MASK (3 << MXC_CCM_CCGR3_IPU2_IPU_DI1_OFFSET)
638 #define MXC_CCM_CCGR3_LDB_DI0_OFFSET 12
639 #define MXC_CCM_CCGR3_LDB_DI0_MASK (3 << MXC_CCM_CCGR3_LDB_DI0_OFFSET)
641 #define MXC_CCM_CCGR3_QSPI1_OFFSET 14
642 #define MXC_CCM_CCGR3_QSPI1_MASK (3 << MXC_CCM_CCGR3_QSPI1_OFFSET)
644 #define MXC_CCM_CCGR3_LDB_DI1_OFFSET 14
645 #define MXC_CCM_CCGR3_LDB_DI1_MASK (3 << MXC_CCM_CCGR3_LDB_DI1_OFFSET)
646 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET 16
647 #define MXC_CCM_CCGR3_MIPI_CORE_CFG_MASK (3 << MXC_CCM_CCGR3_MIPI_CORE_CFG_OFFSET)
649 #define MXC_CCM_CCGR3_MLB_OFFSET 18
650 #define MXC_CCM_CCGR3_MLB_MASK (3 << MXC_CCM_CCGR3_MLB_OFFSET)
651 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET 20
652 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P0_OFFSET)
654 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET 22
655 #define MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_ACLK_FAST_CORE_P1_OFFSET)
657 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET 24
658 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P0_OFFSET)
659 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET 26
660 #define MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_MASK (3 << MXC_CCM_CCGR3_MMDC_CORE_IPG_CLK_P1_OFFSET)
661 #define MXC_CCM_CCGR3_OCRAM_OFFSET 28
662 #define MXC_CCM_CCGR3_OCRAM_MASK (3 << MXC_CCM_CCGR3_OCRAM_OFFSET)
664 #define MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET 30
665 #define MXC_CCM_CCGR3_OPENVGAXICLK_MASK (3 << MXC_CCM_CCGR3_OPENVGAXICLK_OFFSET)
668 #define MXC_CCM_CCGR4_PCIE_OFFSET 0
669 #define MXC_CCM_CCGR4_PCIE_MASK (3 << MXC_CCM_CCGR4_PCIE_OFFSET)
671 #define MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET 10
672 #define MXC_CCM_CCGR4_QSPI2_ENFC_MASK (3 << MXC_CCM_CCGR4_QSPI2_ENFC_OFFSET)
674 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET 8
675 #define MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QFAST1_S133_OFFSET)
677 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET 12
678 #define MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER1_BCH_OFFSET)
679 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET 14
680 #define MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_MASK (3 << MXC_CCM_CCGR4_PL301_MX6QPER2_MAINCLK_ENABLE_OFFSET)
681 #define MXC_CCM_CCGR4_PWM1_OFFSET 16
682 #define MXC_CCM_CCGR4_PWM1_MASK (3 << MXC_CCM_CCGR4_PWM1_OFFSET)
683 #define MXC_CCM_CCGR4_PWM2_OFFSET 18
684 #define MXC_CCM_CCGR4_PWM2_MASK (3 << MXC_CCM_CCGR4_PWM2_OFFSET)
685 #define MXC_CCM_CCGR4_PWM3_OFFSET 20
686 #define MXC_CCM_CCGR4_PWM3_MASK (3 << MXC_CCM_CCGR4_PWM3_OFFSET)
687 #define MXC_CCM_CCGR4_PWM4_OFFSET 22
688 #define MXC_CCM_CCGR4_PWM4_MASK (3 << MXC_CCM_CCGR4_PWM4_OFFSET)
689 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET 24
690 #define MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_BCH_INPUT_APB_OFFSET)
691 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET 26
692 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_BCH_OFFSET)
693 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET 28
694 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_BCH_INPUT_GPMI_IO_OFFSET)
695 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET 30
696 #define MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_MASK (3 << MXC_CCM_CCGR4_RAWNAND_U_GPMI_INPUT_APB_OFFSET)
698 #define MXC_CCM_CCGR5_ROM_OFFSET 0
699 #define MXC_CCM_CCGR5_ROM_MASK (3 << MXC_CCM_CCGR5_ROM_OFFSET)
701 #define MXC_CCM_CCGR5_SATA_OFFSET 4
702 #define MXC_CCM_CCGR5_SATA_MASK (3 << MXC_CCM_CCGR5_SATA_OFFSET)
704 #define MXC_CCM_CCGR5_SDMA_OFFSET 6
705 #define MXC_CCM_CCGR5_SDMA_MASK (3 << MXC_CCM_CCGR5_SDMA_OFFSET)
706 #define MXC_CCM_CCGR5_SPBA_OFFSET 12
707 #define MXC_CCM_CCGR5_SPBA_MASK (3 << MXC_CCM_CCGR5_SPBA_OFFSET)
708 #define MXC_CCM_CCGR5_SPDIF_OFFSET 14
709 #define MXC_CCM_CCGR5_SPDIF_MASK (3 << MXC_CCM_CCGR5_SPDIF_OFFSET)
710 #define MXC_CCM_CCGR5_SSI1_OFFSET 18
711 #define MXC_CCM_CCGR5_SSI1_MASK (3 << MXC_CCM_CCGR5_SSI1_OFFSET)
712 #define MXC_CCM_CCGR5_SSI2_OFFSET 20
713 #define MXC_CCM_CCGR5_SSI2_MASK (3 << MXC_CCM_CCGR5_SSI2_OFFSET)
714 #define MXC_CCM_CCGR5_SSI3_OFFSET 22
715 #define MXC_CCM_CCGR5_SSI3_MASK (3 << MXC_CCM_CCGR5_SSI3_OFFSET)
716 #define MXC_CCM_CCGR5_UART_OFFSET 24
717 #define MXC_CCM_CCGR5_UART_MASK (3 << MXC_CCM_CCGR5_UART_OFFSET)
718 #define MXC_CCM_CCGR5_UART_SERIAL_OFFSET 26
719 #define MXC_CCM_CCGR5_UART_SERIAL_MASK (3 << MXC_CCM_CCGR5_UART_SERIAL_OFFSET)
721 #define MXC_CCM_CCGR5_SAI1_OFFSET 20
722 #define MXC_CCM_CCGR5_SAI1_MASK (3 << MXC_CCM_CCGR5_SAI1_OFFSET)
723 #define MXC_CCM_CCGR5_SAI2_OFFSET 30
724 #define MXC_CCM_CCGR5_SAI2_MASK (3 << MXC_CCM_CCGR5_SAI2_OFFSET)
727 #define MXC_CCM_CCGR6_USBOH3_OFFSET 0
728 #define MXC_CCM_CCGR6_USBOH3_MASK (3 << MXC_CCM_CCGR6_USBOH3_OFFSET)
729 #define MXC_CCM_CCGR6_USDHC1_OFFSET 2
730 #define MXC_CCM_CCGR6_USDHC1_MASK (3 << MXC_CCM_CCGR6_USDHC1_OFFSET)
731 #define MXC_CCM_CCGR6_USDHC2_OFFSET 4
732 #define MXC_CCM_CCGR6_USDHC2_MASK (3 << MXC_CCM_CCGR6_USDHC2_OFFSET)
733 #define MXC_CCM_CCGR6_USDHC3_OFFSET 6
734 #define MXC_CCM_CCGR6_USDHC3_MASK (3 << MXC_CCM_CCGR6_USDHC3_OFFSET)
735 #define MXC_CCM_CCGR6_USDHC4_OFFSET 8
736 #define MXC_CCM_CCGR6_USDHC4_MASK (3 << MXC_CCM_CCGR6_USDHC4_OFFSET)
737 #define MXC_CCM_CCGR6_EMI_SLOW_OFFSET 10
738 #define MXC_CCM_CCGR6_EMI_SLOW_MASK (3 << MXC_CCM_CCGR6_EMI_SLOW_OFFSET)
740 #define MXC_CCM_CCGR6_PWM8_OFFSET 16
741 #define MXC_CCM_CCGR6_PWM8_MASK (3 << MXC_CCM_CCGR6_PWM8_OFFSET)
742 #define MXC_CCM_CCGR6_VADC_OFFSET 20
743 #define MXC_CCM_CCGR6_VADC_MASK (3 << MXC_CCM_CCGR6_VADC_OFFSET)
744 #define MXC_CCM_CCGR6_GIS_OFFSET 22
745 #define MXC_CCM_CCGR6_GIS_MASK (3 << MXC_CCM_CCGR6_GIS_OFFSET)
746 #define MXC_CCM_CCGR6_I2C4_OFFSET 24
747 #define MXC_CCM_CCGR6_I2C4_MASK (3 << MXC_CCM_CCGR6_I2C4_OFFSET)
748 #define MXC_CCM_CCGR6_PWM5_OFFSET 26
749 #define MXC_CCM_CCGR6_PWM5_MASK (3 << MXC_CCM_CCGR6_PWM5_OFFSET)
750 #define MXC_CCM_CCGR6_PWM6_OFFSET 28
751 #define MXC_CCM_CCGR6_PWM6_MASK (3 << MXC_CCM_CCGR6_PWM6_OFFSET)
752 #define MXC_CCM_CCGR6_PWM7_OFFSET 30
753 #define MXC_CCM_CCGR6_PWM7_MASK (3 << MXC_CCM_CCGR6_PWM7_OFFSET)
755 #define MXC_CCM_CCGR6_VDOAXICLK_OFFSET 12
756 #define MXC_CCM_CCGR6_VDOAXICLK_MASK (3 << MXC_CCM_CCGR6_VDOAXICLK_OFFSET)
759 #define BM_ANADIG_PLL_SYS_LOCK 0x80000000
760 #define BP_ANADIG_PLL_SYS_RSVD0 20
761 #define BM_ANADIG_PLL_SYS_RSVD0 0x7FF00000
762 #define BF_ANADIG_PLL_SYS_RSVD0(v) \
763 (((v) << 20) & BM_ANADIG_PLL_SYS_RSVD0)
764 #define BM_ANADIG_PLL_SYS_PLL_SEL 0x00080000
765 #define BM_ANADIG_PLL_SYS_LVDS_24MHZ_SEL 0x00040000
766 #define BM_ANADIG_PLL_SYS_LVDS_SEL 0x00020000
767 #define BM_ANADIG_PLL_SYS_BYPASS 0x00010000
768 #define BP_ANADIG_PLL_SYS_BYPASS_CLK_SRC 14
769 #define BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC 0x0000C000
770 #define BF_ANADIG_PLL_SYS_BYPASS_CLK_SRC(v) \
771 (((v) << 14) & BM_ANADIG_PLL_SYS_BYPASS_CLK_SRC)
772 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__OSC_24M 0x0
773 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_1 0x1
774 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__ANACLK_2 0x2
775 #define BV_ANADIG_PLL_SYS_BYPASS_CLK_SRC__XOR 0x3
776 #define BM_ANADIG_PLL_SYS_ENABLE 0x00002000
777 #define BM_ANADIG_PLL_SYS_POWERDOWN 0x00001000
778 #define BM_ANADIG_PLL_SYS_HOLD_RING_OFF 0x00000800
779 #define BM_ANADIG_PLL_SYS_DOUBLE_CP 0x00000400
780 #define BM_ANADIG_PLL_SYS_HALF_CP 0x00000200
781 #define BM_ANADIG_PLL_SYS_DOUBLE_LF 0x00000100
782 #define BM_ANADIG_PLL_SYS_HALF_LF 0x00000080
783 #define BP_ANADIG_PLL_SYS_DIV_SELECT 0
784 #define BM_ANADIG_PLL_SYS_DIV_SELECT 0x0000007F
785 #define BF_ANADIG_PLL_SYS_DIV_SELECT(v) \
786 (((v) << 0) & BM_ANADIG_PLL_SYS_DIV_SELECT)
788 #define BM_ANADIG_USB1_PLL_480_CTRL_LOCK 0x80000000
789 #define BP_ANADIG_USB1_PLL_480_CTRL_RSVD1 17
790 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD1 0x7FFE0000
791 #define BF_ANADIG_USB1_PLL_480_CTRL_RSVD1(v) \
792 (((v) << 17) & BM_ANADIG_USB1_PLL_480_CTRL_RSVD1)
793 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS 0x00010000
794 #define BP_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 14
795 #define BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC 0x0000C000
796 #define BF_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC(v) \
797 (((v) << 14) & BM_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC)
798 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__OSC_24M 0x0
799 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_1 0x1
800 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__ANACLK_2 0x2
801 #define BV_ANADIG_USB1_PLL_480_CTRL_BYPASS_CLK_SRC__XOR 0x3
802 #define BM_ANADIG_USB1_PLL_480_CTRL_ENABLE 0x00002000
803 #define BM_ANADIG_USB1_PLL_480_CTRL_POWER 0x00001000
804 #define BM_ANADIG_USB1_PLL_480_CTRL_HOLD_RING_OFF 0x00000800
805 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_CP 0x00000400
806 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_CP 0x00000200
807 #define BM_ANADIG_USB1_PLL_480_CTRL_DOUBLE_LF 0x00000100
808 #define BM_ANADIG_USB1_PLL_480_CTRL_HALF_LF 0x00000080
809 #define BM_ANADIG_USB1_PLL_480_CTRL_EN_USB_CLKS 0x00000040
810 #define BM_ANADIG_USB1_PLL_480_CTRL_RSVD0 0x00000020
811 #define BP_ANADIG_USB1_PLL_480_CTRL_CONTROL0 2
812 #define BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0 0x0000001C
813 #define BF_ANADIG_USB1_PLL_480_CTRL_CONTROL0(v) \
814 (((v) << 2) & BM_ANADIG_USB1_PLL_480_CTRL_CONTROL0)
815 #define BP_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0
816 #define BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT 0x00000003
817 #define BF_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT(v) \
818 (((v) << 0) & BM_ANADIG_USB1_PLL_480_CTRL_DIV_SELECT)
820 #define BM_ANADIG_PLL_528_LOCK 0x80000000
821 #define BP_ANADIG_PLL_528_RSVD1 19
822 #define BM_ANADIG_PLL_528_RSVD1 0x7FF80000
823 #define BF_ANADIG_PLL_528_RSVD1(v) \
824 (((v) << 19) & BM_ANADIG_PLL_528_RSVD1)
825 #define BM_ANADIG_PLL_528_PFD_OFFSET_EN 0x00040000
826 #define BM_ANADIG_PLL_528_DITHER_ENABLE 0x00020000
827 #define BM_ANADIG_PLL_528_BYPASS 0x00010000
828 #define BP_ANADIG_PLL_528_BYPASS_CLK_SRC 14
829 #define BM_ANADIG_PLL_528_BYPASS_CLK_SRC 0x0000C000
830 #define BF_ANADIG_PLL_528_BYPASS_CLK_SRC(v) \
831 (((v) << 14) & BM_ANADIG_PLL_528_BYPASS_CLK_SRC)
832 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__OSC_24M 0x0
833 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_1 0x1
834 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__ANACLK_2 0x2
835 #define BV_ANADIG_PLL_528_BYPASS_CLK_SRC__XOR 0x3
836 #define BM_ANADIG_PLL_528_ENABLE 0x00002000
837 #define BM_ANADIG_PLL_528_POWERDOWN 0x00001000
838 #define BM_ANADIG_PLL_528_HOLD_RING_OFF 0x00000800
839 #define BM_ANADIG_PLL_528_DOUBLE_CP 0x00000400
840 #define BM_ANADIG_PLL_528_HALF_CP 0x00000200
841 #define BM_ANADIG_PLL_528_DOUBLE_LF 0x00000100
842 #define BM_ANADIG_PLL_528_HALF_LF 0x00000080
843 #define BP_ANADIG_PLL_528_RSVD0 1
844 #define BM_ANADIG_PLL_528_RSVD0 0x0000007E
845 #define BF_ANADIG_PLL_528_RSVD0(v) \
846 (((v) << 1) & BM_ANADIG_PLL_528_RSVD0)
847 #define BM_ANADIG_PLL_528_DIV_SELECT 0x00000001
849 #define BP_ANADIG_PLL_528_SS_STOP 16
850 #define BM_ANADIG_PLL_528_SS_STOP 0xFFFF0000
851 #define BF_ANADIG_PLL_528_SS_STOP(v) \
852 (((v) << 16) & BM_ANADIG_PLL_528_SS_STOP)
853 #define BM_ANADIG_PLL_528_SS_ENABLE 0x00008000
854 #define BP_ANADIG_PLL_528_SS_STEP 0
855 #define BM_ANADIG_PLL_528_SS_STEP 0x00007FFF
856 #define BF_ANADIG_PLL_528_SS_STEP(v) \
857 (((v) << 0) & BM_ANADIG_PLL_528_SS_STEP)
859 #define BP_ANADIG_PLL_528_NUM_RSVD0 30
860 #define BM_ANADIG_PLL_528_NUM_RSVD0 0xC0000000
861 #define BF_ANADIG_PLL_528_NUM_RSVD0(v) \
862 (((v) << 30) & BM_ANADIG_PLL_528_NUM_RSVD0)
863 #define BP_ANADIG_PLL_528_NUM_A 0
864 #define BM_ANADIG_PLL_528_NUM_A 0x3FFFFFFF
865 #define BF_ANADIG_PLL_528_NUM_A(v) \
866 (((v) << 0) & BM_ANADIG_PLL_528_NUM_A)
868 #define BP_ANADIG_PLL_528_DENOM_RSVD0 30
869 #define BM_ANADIG_PLL_528_DENOM_RSVD0 0xC0000000
870 #define BF_ANADIG_PLL_528_DENOM_RSVD0(v) \
871 (((v) << 30) & BM_ANADIG_PLL_528_DENOM_RSVD0)
872 #define BP_ANADIG_PLL_528_DENOM_B 0
873 #define BM_ANADIG_PLL_528_DENOM_B 0x3FFFFFFF
874 #define BF_ANADIG_PLL_528_DENOM_B(v) \
875 (((v) << 0) & BM_ANADIG_PLL_528_DENOM_B)
877 #define BM_ANADIG_PLL_AUDIO_LOCK 0x80000000
878 #define BP_ANADIG_PLL_AUDIO_RSVD0 22
879 #define BM_ANADIG_PLL_AUDIO_RSVD0 0x7FC00000
880 #define BF_ANADIG_PLL_AUDIO_RSVD0(v) \
881 (((v) << 22) & BM_ANADIG_PLL_AUDIO_RSVD0)
882 #define BM_ANADIG_PLL_AUDIO_SSC_EN 0x00200000
883 #define BP_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 19
884 #define BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT 0x00180000
885 #define BF_ANADIG_PLL_AUDIO_TEST_DIV_SELECT(v) \
886 (((v) << 19) & BM_ANADIG_PLL_AUDIO_TEST_DIV_SELECT)
887 #define BM_ANADIG_PLL_AUDIO_PFD_OFFSET_EN 0x00040000
888 #define BM_ANADIG_PLL_AUDIO_DITHER_ENABLE 0x00020000
889 #define BM_ANADIG_PLL_AUDIO_BYPASS 0x00010000
890 #define BP_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 14
891 #define BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC 0x0000C000
892 #define BF_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC(v) \
893 (((v) << 14) & BM_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC)
894 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__OSC_24M 0x0
895 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_1 0x1
896 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__ANACLK_2 0x2
897 #define BV_ANADIG_PLL_AUDIO_BYPASS_CLK_SRC__XOR 0x3
898 #define BM_ANADIG_PLL_AUDIO_ENABLE 0x00002000
899 #define BM_ANADIG_PLL_AUDIO_POWERDOWN 0x00001000
900 #define BM_ANADIG_PLL_AUDIO_HOLD_RING_OFF 0x00000800
901 #define BM_ANADIG_PLL_AUDIO_DOUBLE_CP 0x00000400
902 #define BM_ANADIG_PLL_AUDIO_HALF_CP 0x00000200
903 #define BM_ANADIG_PLL_AUDIO_DOUBLE_LF 0x00000100
904 #define BM_ANADIG_PLL_AUDIO_HALF_LF 0x00000080
905 #define BP_ANADIG_PLL_AUDIO_DIV_SELECT 0
906 #define BM_ANADIG_PLL_AUDIO_DIV_SELECT 0x0000007F
907 #define BF_ANADIG_PLL_AUDIO_DIV_SELECT(v) \
908 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DIV_SELECT)
910 #define BP_ANADIG_PLL_AUDIO_NUM_RSVD0 30
911 #define BM_ANADIG_PLL_AUDIO_NUM_RSVD0 0xC0000000
912 #define BF_ANADIG_PLL_AUDIO_NUM_RSVD0(v) \
913 (((v) << 30) & BM_ANADIG_PLL_AUDIO_NUM_RSVD0)
914 #define BP_ANADIG_PLL_AUDIO_NUM_A 0
915 #define BM_ANADIG_PLL_AUDIO_NUM_A 0x3FFFFFFF
916 #define BF_ANADIG_PLL_AUDIO_NUM_A(v) \
917 (((v) << 0) & BM_ANADIG_PLL_AUDIO_NUM_A)
919 #define BP_ANADIG_PLL_AUDIO_DENOM_RSVD0 30
920 #define BM_ANADIG_PLL_AUDIO_DENOM_RSVD0 0xC0000000
921 #define BF_ANADIG_PLL_AUDIO_DENOM_RSVD0(v) \
922 (((v) << 30) & BM_ANADIG_PLL_AUDIO_DENOM_RSVD0)
923 #define BP_ANADIG_PLL_AUDIO_DENOM_B 0
924 #define BM_ANADIG_PLL_AUDIO_DENOM_B 0x3FFFFFFF
925 #define BF_ANADIG_PLL_AUDIO_DENOM_B(v) \
926 (((v) << 0) & BM_ANADIG_PLL_AUDIO_DENOM_B)
928 #define BM_ANADIG_PLL_VIDEO_LOCK 0x80000000
929 #define BP_ANADIG_PLL_VIDEO_RSVD0 22
930 #define BM_ANADIG_PLL_VIDEO_RSVD0 0x7FC00000
931 #define BF_ANADIG_PLL_VIDEO_RSVD0(v) \
932 (((v) << 22) & BM_ANADIG_PLL_VIDEO_RSVD0)
933 #define BM_ANADIG_PLL_VIDEO_SSC_EN 0x00200000
934 #define BP_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 19
935 #define BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT 0x00180000
936 #define BF_ANADIG_PLL_VIDEO_TEST_DIV_SELECT(v) \
937 (((v) << 19) & BM_ANADIG_PLL_VIDEO_TEST_DIV_SELECT)
938 #define BM_ANADIG_PLL_VIDEO_PFD_OFFSET_EN 0x00040000
939 #define BM_ANADIG_PLL_VIDEO_DITHER_ENABLE 0x00020000
940 #define BM_ANADIG_PLL_VIDEO_BYPASS 0x00010000
941 #define BP_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 14
942 #define BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC 0x0000C000
943 #define BF_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC(v) \
944 (((v) << 14) & BM_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC)
945 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__OSC_24M 0x0
946 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_1 0x1
947 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__ANACLK_2 0x2
948 #define BV_ANADIG_PLL_VIDEO_BYPASS_CLK_SRC__XOR 0x3
949 #define BM_ANADIG_PLL_VIDEO_ENABLE 0x00002000
950 #define BM_ANADIG_PLL_VIDEO_POWERDOWN 0x00001000
951 #define BM_ANADIG_PLL_VIDEO_HOLD_RING_OFF 0x00000800
952 #define BM_ANADIG_PLL_VIDEO_DOUBLE_CP 0x00000400
953 #define BM_ANADIG_PLL_VIDEO_HALF_CP 0x00000200
954 #define BM_ANADIG_PLL_VIDEO_DOUBLE_LF 0x00000100
955 #define BM_ANADIG_PLL_VIDEO_HALF_LF 0x00000080
956 #define BP_ANADIG_PLL_VIDEO_DIV_SELECT 0
957 #define BM_ANADIG_PLL_VIDEO_DIV_SELECT 0x0000007F
958 #define BF_ANADIG_PLL_VIDEO_DIV_SELECT(v) \
959 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DIV_SELECT)
961 #define BP_ANADIG_PLL_VIDEO_NUM_RSVD0 30
962 #define BM_ANADIG_PLL_VIDEO_NUM_RSVD0 0xC0000000
963 #define BF_ANADIG_PLL_VIDEO_NUM_RSVD0(v) \
964 (((v) << 30) & BM_ANADIG_PLL_VIDEO_NUM_RSVD0)
965 #define BP_ANADIG_PLL_VIDEO_NUM_A 0
966 #define BM_ANADIG_PLL_VIDEO_NUM_A 0x3FFFFFFF
967 #define BF_ANADIG_PLL_VIDEO_NUM_A(v) \
968 (((v) << 0) & BM_ANADIG_PLL_VIDEO_NUM_A)
970 #define BP_ANADIG_PLL_VIDEO_DENOM_RSVD0 30
971 #define BM_ANADIG_PLL_VIDEO_DENOM_RSVD0 0xC0000000
972 #define BF_ANADIG_PLL_VIDEO_DENOM_RSVD0(v) \
973 (((v) << 30) & BM_ANADIG_PLL_VIDEO_DENOM_RSVD0)
974 #define BP_ANADIG_PLL_VIDEO_DENOM_B 0
975 #define BM_ANADIG_PLL_VIDEO_DENOM_B 0x3FFFFFFF
976 #define BF_ANADIG_PLL_VIDEO_DENOM_B(v) \
977 (((v) << 0) & BM_ANADIG_PLL_VIDEO_DENOM_B)
979 #define BM_ANADIG_PLL_ENET_LOCK 0x80000000
980 #define BP_ANADIG_PLL_ENET_RSVD1 21
981 #define BM_ANADIG_PLL_ENET_RSVD1 0x7FE00000
982 #define BF_ANADIG_PLL_ENET_RSVD1(v) \
983 (((v) << 21) & BM_ANADIG_PLL_ENET_RSVD1)
984 #define BM_ANADIG_PLL_ENET_ENABLE_SATA 0x00100000
985 #define BM_ANADIG_PLL_ENET_ENABLE_PCIE 0x00080000
986 #define BM_ANADIG_PLL_ENET_PFD_OFFSET_EN 0x00040000
987 #define BM_ANADIG_PLL_ENET_DITHER_ENABLE 0x00020000
988 #define BM_ANADIG_PLL_ENET_BYPASS 0x00010000
989 #define BP_ANADIG_PLL_ENET_BYPASS_CLK_SRC 14
990 #define BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC 0x0000C000
991 #define BF_ANADIG_PLL_ENET_BYPASS_CLK_SRC(v) \
992 (((v) << 14) & BM_ANADIG_PLL_ENET_BYPASS_CLK_SRC)
993 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__OSC_24M 0x0
994 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_1 0x1
995 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__ANACLK_2 0x2
996 #define BV_ANADIG_PLL_ENET_BYPASS_CLK_SRC__XOR 0x3
997 #define BM_ANADIG_PLL_ENET_ENABLE 0x00002000
998 #define BM_ANADIG_PLL_ENET_POWERDOWN 0x00001000
999 #define BM_ANADIG_PLL_ENET_HOLD_RING_OFF 0x00000800
1000 #define BM_ANADIG_PLL_ENET_DOUBLE_CP 0x00000400
1001 #define BM_ANADIG_PLL_ENET_HALF_CP 0x00000200
1002 #define BM_ANADIG_PLL_ENET_DOUBLE_LF 0x00000100
1003 #define BM_ANADIG_PLL_ENET_HALF_LF 0x00000080
1004 #define BP_ANADIG_PLL_ENET_RSVD0 2
1005 #define BM_ANADIG_PLL_ENET_RSVD0 0x0000007C
1006 #define BF_ANADIG_PLL_ENET_RSVD0(v) \
1007 (((v) << 2) & BM_ANADIG_PLL_ENET_RSVD0)
1008 #define BP_ANADIG_PLL_ENET_DIV_SELECT 0
1009 #define BM_ANADIG_PLL_ENET_DIV_SELECT 0x00000003
1010 #define BF_ANADIG_PLL_ENET_DIV_SELECT(v) \
1011 (((v) << 0) & BM_ANADIG_PLL_ENET_DIV_SELECT)
1013 #define BM_ANADIG_PFD_480_PFD3_CLKGATE 0x80000000
1014 #define BM_ANADIG_PFD_480_PFD3_STABLE 0x40000000
1015 #define BP_ANADIG_PFD_480_PFD3_FRAC 24
1016 #define BM_ANADIG_PFD_480_PFD3_FRAC 0x3F000000
1017 #define BF_ANADIG_PFD_480_PFD3_FRAC(v) \
1018 (((v) << 24) & BM_ANADIG_PFD_480_PFD3_FRAC)
1019 #define BM_ANADIG_PFD_480_PFD2_CLKGATE 0x00800000
1020 #define BM_ANADIG_PFD_480_PFD2_STABLE 0x00400000
1021 #define BP_ANADIG_PFD_480_PFD2_FRAC 16
1022 #define BM_ANADIG_PFD_480_PFD2_FRAC 0x003F0000
1023 #define BF_ANADIG_PFD_480_PFD2_FRAC(v) \
1024 (((v) << 16) & BM_ANADIG_PFD_480_PFD2_FRAC)
1025 #define BM_ANADIG_PFD_480_PFD1_CLKGATE 0x00008000
1026 #define BM_ANADIG_PFD_480_PFD1_STABLE 0x00004000
1027 #define BP_ANADIG_PFD_480_PFD1_FRAC 8
1028 #define BM_ANADIG_PFD_480_PFD1_FRAC 0x00003F00
1029 #define BF_ANADIG_PFD_480_PFD1_FRAC(v) \
1030 (((v) << 8) & BM_ANADIG_PFD_480_PFD1_FRAC)
1031 #define BM_ANADIG_PFD_480_PFD0_CLKGATE 0x00000080
1032 #define BM_ANADIG_PFD_480_PFD0_STABLE 0x00000040
1033 #define BP_ANADIG_PFD_480_PFD0_FRAC 0
1034 #define BM_ANADIG_PFD_480_PFD0_FRAC 0x0000003F
1035 #define BF_ANADIG_PFD_480_PFD0_FRAC(v) \
1036 (((v) << 0) & BM_ANADIG_PFD_480_PFD0_FRAC)
1038 #define BM_ANADIG_PFD_528_PFD3_CLKGATE 0x80000000
1039 #define BM_ANADIG_PFD_528_PFD3_STABLE 0x40000000
1040 #define BP_ANADIG_PFD_528_PFD3_FRAC 24
1041 #define BM_ANADIG_PFD_528_PFD3_FRAC 0x3F000000
1042 #define BF_ANADIG_PFD_528_PFD3_FRAC(v) \
1043 (((v) << 24) & BM_ANADIG_PFD_528_PFD3_FRAC)
1044 #define BM_ANADIG_PFD_528_PFD2_CLKGATE 0x00800000
1045 #define BM_ANADIG_PFD_528_PFD2_STABLE 0x00400000
1046 #define BP_ANADIG_PFD_528_PFD2_FRAC 16
1047 #define BM_ANADIG_PFD_528_PFD2_FRAC 0x003F0000
1048 #define BF_ANADIG_PFD_528_PFD2_FRAC(v) \
1049 (((v) << 16) & BM_ANADIG_PFD_528_PFD2_FRAC)
1050 #define BM_ANADIG_PFD_528_PFD1_CLKGATE 0x00008000
1051 #define BM_ANADIG_PFD_528_PFD1_STABLE 0x00004000
1052 #define BP_ANADIG_PFD_528_PFD1_FRAC 8
1053 #define BM_ANADIG_PFD_528_PFD1_FRAC 0x00003F00
1054 #define BF_ANADIG_PFD_528_PFD1_FRAC(v) \
1055 (((v) << 8) & BM_ANADIG_PFD_528_PFD1_FRAC)
1056 #define BM_ANADIG_PFD_528_PFD0_CLKGATE 0x00000080
1057 #define BM_ANADIG_PFD_528_PFD0_STABLE 0x00000040
1058 #define BP_ANADIG_PFD_528_PFD0_FRAC 0
1059 #define BM_ANADIG_PFD_528_PFD0_FRAC 0x0000003F
1060 #define BF_ANADIG_PFD_528_PFD0_FRAC(v) \
1061 (((v) << 0) & BM_ANADIG_PFD_528_PFD0_FRAC)
1063 #endif /*__ARCH_ARM_MACH_MX6_CCM_REGS_H__ */
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