2 * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
4 * SPDX-License-Identifier: GPL-2.0+
7 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
8 #define __ASM_ARCH_MX6_IMX_REGS_H__
10 #include <asm/imx-common/regs-common.h>
14 #define CONFIG_SYS_CACHELINE_SIZE 64
16 #define ROMCP_ARB_BASE_ADDR 0x00000000
17 #define ROMCP_ARB_END_ADDR 0x000FFFFF
19 #ifdef CONFIG_SOC_MX6SL
20 #define GPU_2D_ARB_BASE_ADDR 0x02200000
21 #define GPU_2D_ARB_END_ADDR 0x02203FFF
22 #define OPENVG_ARB_BASE_ADDR 0x02204000
23 #define OPENVG_ARB_END_ADDR 0x02207FFF
24 #elif defined(CONFIG_SOC_MX6SX)
25 #define CAAM_ARB_BASE_ADDR 0x00100000
26 #define CAAM_ARB_END_ADDR 0x00107FFF
27 #define GPU_ARB_BASE_ADDR 0x01800000
28 #define GPU_ARB_END_ADDR 0x01803FFF
29 #define APBH_DMA_ARB_BASE_ADDR 0x01804000
30 #define APBH_DMA_ARB_END_ADDR 0x0180BFFF
31 #define M4_BOOTROM_BASE_ADDR 0x007F8000
33 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
34 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
35 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
38 #define CAAM_ARB_BASE_ADDR 0x00100000
39 #define CAAM_ARB_END_ADDR 0x00103FFF
40 #define APBH_DMA_ARB_BASE_ADDR 0x00110000
41 #define APBH_DMA_ARB_END_ADDR 0x00117FFF
42 #define HDMI_ARB_BASE_ADDR 0x00120000
43 #define HDMI_ARB_END_ADDR 0x00128FFF
44 #define GPU_3D_ARB_BASE_ADDR 0x00130000
45 #define GPU_3D_ARB_END_ADDR 0x00133FFF
46 #define GPU_2D_ARB_BASE_ADDR 0x00134000
47 #define GPU_2D_ARB_END_ADDR 0x00137FFF
48 #define DTCP_ARB_BASE_ADDR 0x00138000
49 #define DTCP_ARB_END_ADDR 0x0013BFFF
50 #endif /* CONFIG_SOC_MX6SL */
52 #define MXS_APBH_BASE APBH_DMA_ARB_BASE_ADDR
53 #define MXS_GPMI_BASE (APBH_DMA_ARB_BASE_ADDR + 0x02000)
54 #define MXS_BCH_BASE (APBH_DMA_ARB_BASE_ADDR + 0x04000)
56 /* GPV - PL301 configuration ports */
57 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
58 #define GPV2_BASE_ADDR 0x00D00000
60 #define GPV2_BASE_ADDR 0x00200000
63 #ifdef CONFIG_SOC_MX6SX
64 #define GPV3_BASE_ADDR 0x00E00000
65 #define GPV4_BASE_ADDR 0x00F00000
66 #define GPV5_BASE_ADDR 0x01000000
67 #define GPV6_BASE_ADDR 0x01100000
68 #define PCIE_ARB_BASE_ADDR 0x08000000
69 #define PCIE_ARB_END_ADDR 0x08FFFFFF
72 #define GPV3_BASE_ADDR 0x00300000
73 #define GPV4_BASE_ADDR 0x00800000
74 #define PCIE_ARB_BASE_ADDR 0x01000000
75 #define PCIE_ARB_END_ADDR 0x01FFFFFF
78 #define IRAM_BASE_ADDR 0x00900000
79 #define SCU_BASE_ADDR 0x00A00000
80 #define IC_INTERFACES_BASE_ADDR 0x00A00100
81 #define GLOBAL_TIMER_BASE_ADDR 0x00A00200
82 #define PRIVATE_TIMERS_WD_BASE_ADDR 0x00A00600
83 #define IC_DISTRIBUTOR_BASE_ADDR 0x00A01000
84 #define L2_PL310_BASE 0x00A02000
85 #define GPV0_BASE_ADDR 0x00B00000
86 #define GPV1_BASE_ADDR 0x00C00000
88 #define AIPS1_ARB_BASE_ADDR 0x02000000
89 #define AIPS1_ARB_END_ADDR 0x020FFFFF
90 #define AIPS2_ARB_BASE_ADDR 0x02100000
91 #define AIPS2_ARB_END_ADDR 0x021FFFFF
92 #ifdef CONFIG_SOC_MX6SX
93 #define AIPS3_BASE_ADDR 0x02200000
94 #define AIPS3_END_ADDR 0x022FFFFF
95 #define WEIM_ARB_BASE_ADDR 0x50000000
96 #define WEIM_ARB_END_ADDR 0x57FFFFFF
97 #define QSPI0_AMBA_BASE 0x60000000
98 #define QSPI0_AMBA_END 0x6FFFFFFF
99 #define QSPI1_AMBA_BASE 0x70000000
100 #define QSPI1_AMBA_END 0x7FFFFFFF
102 #define SATA_ARB_BASE_ADDR 0x02200000
103 #define SATA_ARB_END_ADDR 0x02203FFF
104 #define OPENVG_ARB_BASE_ADDR 0x02204000
105 #define OPENVG_ARB_END_ADDR 0x02207FFF
106 #define HSI_ARB_BASE_ADDR 0x02208000
107 #define HSI_ARB_END_ADDR 0x0220BFFF
108 #define IPU1_ARB_BASE_ADDR 0x02400000
109 #define IPU1_ARB_END_ADDR 0x027FFFFF
110 #define IPU2_ARB_BASE_ADDR 0x02800000
111 #define IPU2_ARB_END_ADDR 0x02BFFFFF
112 #define WEIM_ARB_BASE_ADDR 0x08000000
113 #define WEIM_ARB_END_ADDR 0x0FFFFFFF
116 #if (defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6SX))
117 #define MMDC0_ARB_BASE_ADDR 0x80000000
118 #define MMDC0_ARB_END_ADDR 0xFFFFFFFF
119 #define MMDC1_ARB_BASE_ADDR 0xC0000000
120 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
122 #define MMDC0_ARB_BASE_ADDR 0x10000000
123 #define MMDC0_ARB_END_ADDR 0x7FFFFFFF
124 #define MMDC1_ARB_BASE_ADDR 0x80000000
125 #define MMDC1_ARB_END_ADDR 0xFFFFFFFF
128 #ifndef CONFIG_SOC_MX6SX
129 #define IPU_SOC_BASE_ADDR IPU1_ARB_BASE_ADDR
130 #define IPU_SOC_OFFSET 0x00200000
133 /* Defines for Blocks connected via AIPS (SkyBlue) */
134 #define ATZ1_BASE_ADDR AIPS1_ARB_BASE_ADDR
135 #define ATZ2_BASE_ADDR AIPS2_ARB_BASE_ADDR
136 #define AIPS1_BASE_ADDR AIPS1_ON_BASE_ADDR
137 #define AIPS2_BASE_ADDR AIPS2_ON_BASE_ADDR
139 #define SPDIF_BASE_ADDR (ATZ1_BASE_ADDR + 0x04000)
140 #define ECSPI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x08000)
141 #define ECSPI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x0C000)
142 #define ECSPI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x10000)
143 #define ECSPI4_BASE_ADDR (ATZ1_BASE_ADDR + 0x14000)
144 #ifdef CONFIG_SOC_MX6SL
145 #define UART5_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
146 #define UART1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x20000)
147 #define UART2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
148 #define SSI1_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
149 #define SSI2_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
150 #define SSI3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
151 #define UART3_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
152 #define UART4_IPS_BASE_ADDR (ATZ1_BASE_ADDR + 0x38000)
154 #ifndef CONFIG_SOC_MX6SX
155 #define ECSPI5_BASE_ADDR (ATZ1_BASE_ADDR + 0x18000)
157 #define UART1_BASE (ATZ1_BASE_ADDR + 0x20000)
158 #define ESAI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x24000)
159 #define SSI1_BASE_ADDR (ATZ1_BASE_ADDR + 0x28000)
160 #define SSI2_BASE_ADDR (ATZ1_BASE_ADDR + 0x2C000)
161 #define SSI3_BASE_ADDR (ATZ1_BASE_ADDR + 0x30000)
162 #define ASRC_BASE_ADDR (ATZ1_BASE_ADDR + 0x34000)
165 #ifndef CONFIG_SOC_MX6SX
166 #define SPBA_BASE_ADDR (ATZ1_BASE_ADDR + 0x3C000)
167 #define VPU_BASE_ADDR (ATZ1_BASE_ADDR + 0x40000)
169 #define AIPS1_ON_BASE_ADDR (ATZ1_BASE_ADDR + 0x7C000)
171 #define AIPS1_OFF_BASE_ADDR (ATZ1_BASE_ADDR + 0x80000)
172 #define PWM1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x0000)
173 #define PWM2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4000)
174 #define PWM3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x8000)
175 #define PWM4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0xC000)
176 #define CAN1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x10000)
177 #define CAN2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x14000)
178 #define GPT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x18000)
179 #define GPIO1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x1C000)
180 #define GPIO2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x20000)
181 #define GPIO3_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x24000)
182 #define GPIO4_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x28000)
183 #define GPIO5_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x2C000)
184 #define GPIO6_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x30000)
185 #define GPIO7_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x34000)
186 #define KPP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x38000)
187 #define WDOG1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x3C000)
188 #define WDOG2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x40000)
189 #define CCM_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x44000)
190 #define ANATOP_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x48000)
191 #define USB_PHY0_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x49000)
192 #define USB_PHY1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4a000)
193 #define SNVS_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x4C000)
194 #define EPIT1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x50000)
195 #define EPIT2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x54000)
196 #define SRC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x58000)
197 #define GPC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x5C000)
198 #define IOMUXC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x60000)
199 #ifdef CONFIG_SOC_MX6SL
200 #define CSI_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
201 #define SIPIX_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
202 #define SDMA_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
203 #elif defined(CONFIG_SOC_MX6SX)
204 #define CANFD1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
205 #define SDMA_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
206 #define CANFD2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x70000)
207 #define SEMAPHORE1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x74000)
208 #define SEMAPHORE2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x78000)
209 #define RDC_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x7C000)
211 #define DCIC1_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x64000)
212 #define DCIC2_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x68000)
213 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
216 #define AIPS2_ON_BASE_ADDR (ATZ2_BASE_ADDR + 0x7C000)
217 #define AIPS2_OFF_BASE_ADDR (ATZ2_BASE_ADDR + 0x80000)
218 #define CAAM_BASE_ADDR (ATZ2_BASE_ADDR)
219 #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
220 #define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000)
221 #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000)
223 #define ENET_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x8000)
224 #ifdef CONFIG_SOC_MX6SL
225 #define MSHC_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
227 #define MLB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0xC000)
230 #define USDHC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x10000)
231 #define USDHC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x14000)
232 #define USDHC3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x18000)
233 #define USDHC4_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x1C000)
234 #define I2C1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x20000)
235 #define I2C2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x24000)
236 #define I2C3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x28000)
237 #define ROMCP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x2C000)
238 #define MMDC_P0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x30000)
239 #ifdef CONFIG_SOC_MX6SL
240 #define RNGB_IPS_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
241 #elif defined(CONFIG_SOC_MX6SX)
242 #define ENET2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
244 #define MMDC_P1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x34000)
247 #define WEIM_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x38000)
248 #define OCOTP_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x3C000)
249 #define CSU_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x40000)
250 #define IP2APB_PERFMON1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x44000)
251 #define IP2APB_PERFMON2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x48000)
252 #ifdef CONFIG_SOC_MX6SX
253 #define DEBUG_MONITOR_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
255 #define IP2APB_PERFMON3_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4C000)
257 #define IP2APB_TZASC1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x50000)
258 #ifdef CONFIG_SOC_MX6SX
259 #define SAI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
261 #define IP2APB_TZASC2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x54000)
263 #define AUDMUX_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x58000)
264 #ifdef CONFIG_SOC_MX6SX
265 #define SAI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
266 #define QSPI0_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
267 #define QSPI1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
269 #define MIPI_CSI2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x5C000)
270 #define MIPI_DSI_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x60000)
271 #define VDOA_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x64000)
273 #define UART2_BASE (AIPS2_OFF_BASE_ADDR + 0x68000)
274 #define UART3_BASE (AIPS2_OFF_BASE_ADDR + 0x6C000)
275 #define UART4_BASE (AIPS2_OFF_BASE_ADDR + 0x70000)
276 #define UART5_BASE (AIPS2_OFF_BASE_ADDR + 0x74000)
277 #define IP2APB_USBPHY1_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x78000)
278 #define IP2APB_USBPHY2_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x7C000)
280 #ifdef CONFIG_SOC_MX6SX
281 #define GIS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x04000)
282 #define DCIC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x0C000)
283 #define DCIC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x10000)
284 #define CSI1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x14000)
285 #define PXP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x18000)
286 #define CSI2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x1C000)
287 #define LCDIF1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x20000)
288 #define LCDIF2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x24000)
289 #define VADC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x28000)
290 #define VDEC_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x2C000)
291 #define SPBA_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x3C000)
292 #define AIPS3_CONFIG_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x7C000)
293 #define ADC1_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x80000)
294 #define ADC2_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x84000)
295 #define WDOG3_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x88000)
296 #define ECSPI5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x8C000)
297 #define HS_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x90000)
298 #define MU_MCU_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x94000)
299 #define CANFD_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x98000)
300 #define MU_DSP_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0x9C000)
301 #define UART6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA0000)
302 #define PWM5_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA4000)
303 #define PWM6_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xA8000)
304 #define PWM7_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xAC000)
305 #define PWM8_BASE_ADDR (AIPS3_ARB_BASE_ADDR + 0xB0000)
308 #define CHIP_REV_1_0 0x10
309 #define CHIP_REV_1_2 0x12
310 #define CHIP_REV_1_5 0x15
311 #ifndef CONFIG_SOC_MX6SX
312 #define IRAM_SIZE 0x00040000
314 #define IRAM_SIZE 0x00020000
316 #define IMX_IIM_BASE OCOTP_BASE_ADDR
317 #define FEC_QUIRK_ENET_MAC
319 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
320 #include <asm/types.h>
322 #define SRC_SCR_CORE_1_RESET_OFFSET 14
323 #define SRC_SCR_CORE_1_RESET_MASK (1 << SRC_SCR_CORE_1_RESET_OFFSET)
324 #define SRC_SCR_CORE_2_RESET_OFFSET 15
325 #define SRC_SCR_CORE_2_RESET_MASK (1 << SRC_SCR_CORE_2_RESET_OFFSET)
326 #define SRC_SCR_CORE_3_RESET_OFFSET 16
327 #define SRC_SCR_CORE_3_RESET_MASK (1 << SRC_SCR_CORE_3_RESET_OFFSET)
328 #define SRC_SCR_CORE_1_ENABLE_OFFSET 22
329 #define SRC_SCR_CORE_1_ENABLE_MASK (1 << SRC_SCR_CORE_1_ENABLE_OFFSET)
330 #define SRC_SCR_CORE_2_ENABLE_OFFSET 23
331 #define SRC_SCR_CORE_2_ENABLE_MASK (1 << SRC_SCR_CORE_2_ENABLE_OFFSET)
332 #define SRC_SCR_CORE_3_ENABLE_OFFSET 24
333 #define SRC_SCR_CORE_3_ENABLE_MASK (1 << SRC_SCR_CORE_3_ENABLE_OFFSET)
372 /* System Reset Controller (SRC) */
394 #define IOMUXC_GPR1_ENET_CLK_SEL_OFFSET 21
395 #define IOMUXC_GPR1_ENET_CLK_SEL_MASK (1 << IOMUXC_GPR1_ENET_CLK_SEL_OFFSET)
396 #define IOMUXC_GPR1_USB_OTG_ID_OFFSET 13
397 #define IOMUXC_GPR1_USB_OTG_ID_SEL_MASK (1 << IOMUXC_GPR1_USB_OTG_ID_OFFSET)
400 #define IOMUXC_GPR3_GPU_DBG_OFFSET 29
401 #define IOMUXC_GPR3_GPU_DBG_MASK (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
402 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET 28
403 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
404 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET 27
405 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
406 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET 26
407 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
408 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET 25
409 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
410 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET 21
411 #define IOMUXC_GPR3_OCRAM_CTL_MASK (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
412 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET 17
413 #define IOMUXC_GPR3_OCRAM_STATUS_MASK (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
414 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET 16
415 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
416 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET 15
417 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
418 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET 14
419 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
420 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET 13
421 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
422 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET 12
423 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
424 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET 11
425 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
426 #define IOMUXC_GPR3_IPU_DIAG_OFFSET 10
427 #define IOMUXC_GPR3_IPU_DIAG_MASK (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
429 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0 0
430 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1 1
431 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0 2
432 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1 3
434 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET 8
435 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
437 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET 6
438 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
440 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET 4
441 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
443 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET 2
444 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
448 #ifdef CONFIG_SOC_MX6SX
449 u32 reserved[0x1000];
467 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET 20
468 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
469 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET 16
470 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
472 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET 15
473 #define IOMUXC_GPR2_BGREF_RRMODE_MASK (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
474 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
475 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
476 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH 0
477 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW 1
479 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET 10
480 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
481 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
482 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
484 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET 9
485 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
486 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
487 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
489 #define IOMUXC_GPR2_BITMAP_SPWG 0
490 #define IOMUXC_GPR2_BITMAP_JEIDA 1
492 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET 8
493 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
494 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
495 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
497 #define IOMUXC_GPR2_DATA_WIDTH_18 0
498 #define IOMUXC_GPR2_DATA_WIDTH_24 1
500 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET 7
501 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
502 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
503 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
505 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET 6
506 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
507 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
508 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
510 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET 5
511 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
512 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
513 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
515 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET 4
516 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
518 #define IOMUXC_GPR2_MODE_DISABLED 0
519 #define IOMUXC_GPR2_MODE_ENABLED_DI0 1
520 #define IOMUXC_GPR2_MODE_ENABLED_DI1 3
522 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET 2
523 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
524 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
525 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
526 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
528 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET 0
529 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
530 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
531 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0 (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
532 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1 (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
534 /* ECSPI registers */
547 * CSPI register definitions
550 #define MXC_CSPICTRL_EN (1 << 0)
551 #define MXC_CSPICTRL_MODE (1 << 1)
552 #define MXC_CSPICTRL_XCH (1 << 2)
553 #define MXC_CSPICTRL_MODE_MASK (0xf << 4)
554 #define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 12)
555 #define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0xfff) << 20)
556 #define MXC_CSPICTRL_PREDIV(x) (((x) & 0xF) << 12)
557 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
558 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
559 #define MXC_CSPICTRL_MAXBITS 0xfff
560 #define MXC_CSPICTRL_TC (1 << 7)
561 #define MXC_CSPICTRL_RXOVF (1 << 6)
562 #define MXC_CSPIPERIOD_32KHZ (1 << 15)
563 #define MAX_SPI_BYTES 32
564 #define SPI_MAX_NUM 4
566 /* Bit position inside CTRL register to be associated with SS */
567 #define MXC_CSPICTRL_CHAN 18
569 /* Bit position inside CON register to be associated with SS */
570 #define MXC_CSPICON_PHA 0 /* SCLK phase control */
571 #define MXC_CSPICON_POL 4 /* SCLK polarity */
572 #define MXC_CSPICON_SSPOL 12 /* SS polarity */
573 #define MXC_CSPICON_CTL 20 /* inactive state of SCLK */
574 #if defined(CONFIG_SOC_MX6SL) || defined(CONFIG_SOC_MX6DL)
575 #define MXC_SPI_BASE_ADDRESSES \
581 #define MXC_SPI_BASE_ADDRESSES \
603 reg_32(fuse_regs[8]);
607 struct fuse_bank0_regs {
608 reg_32(misc_conf_lock);
624 #ifdef CONFIG_SOC_MX6SX
625 struct fuse_bank4_regs {
640 struct fuse_bank4_regs {
641 reg_32(sjc_resp_low);
642 reg_32(sjc_resp_high);
643 reg_32(mac_addr_low);
644 reg_32(mac_addr_high);
650 struct fuse_bank5_regs {
652 reg_32(pad_settings);
653 reg_32(field_return);
669 mxs_reg_32(pll_arm); /* 0x000 */
670 mxs_reg_32(usb1_pll_480_ctrl); /* 0x010 */
671 mxs_reg_32(usb2_pll_480_ctrl); /* 0x020 */
672 mxs_reg_32(pll_528); /* 0x030 */
673 reg_32(pll_528_ss); /* 0x040 */
674 reg_32(pll_528_num); /* 0x050 */
675 reg_32(pll_528_denom); /* 0x060 */
676 mxs_reg_32(pll_audio); /* 0x070 */
677 reg_32(pll_audio_num); /* 0x080 */
678 reg_32(pll_audio_denom); /* 0x090 */
679 mxs_reg_32(pll_video); /* 0x0a0 */
680 reg_32(pll_video_num); /* 0x0b0 */
681 reg_32(pll_video_denom); /* 0x0c0 */
682 mxs_reg_32(pll_mlb); /* 0x0d0 */
683 mxs_reg_32(pll_enet); /* 0x0e0 */
684 mxs_reg_32(pfd_480); /* 0x0f0 */
685 mxs_reg_32(pfd_528); /* 0x100 */
686 mxs_reg_32(reg_1p1); /* 0x110 */
687 mxs_reg_32(reg_3p0); /* 0x120 */
688 mxs_reg_32(reg_2p5); /* 0x130 */
689 mxs_reg_32(reg_core); /* 0x140 */
690 mxs_reg_32(ana_misc0); /* 0x150 */
691 mxs_reg_32(ana_misc1); /* 0x160 */
692 mxs_reg_32(ana_misc2); /* 0x170 */
693 mxs_reg_32(tempsense0); /* 0x180 */
694 mxs_reg_32(tempsense1); /* 0x190 */
695 mxs_reg_32(usb1_vbus_detect); /* 0x1a0 */
696 mxs_reg_32(usb1_chrg_detect); /* 0x1b0 */
697 mxs_reg_32(usb1_vbus_det_stat); /* 0x1c0 */
698 mxs_reg_32(usb1_chrg_det_stat); /* 0x1d0 */
699 mxs_reg_32(usb1_loopback); /* 0x1e0 */
700 mxs_reg_32(usb1_misc); /* 0x1f0 */
701 mxs_reg_32(usb2_vbus_detect); /* 0x200 */
702 mxs_reg_32(usb2_chrg_detect); /* 0x210 */
703 mxs_reg_32(usb2_vbus_det_stat); /* 0x220 */
704 mxs_reg_32(usb2_chrg_det_stat); /* 0x230 */
705 mxs_reg_32(usb2_loopback); /* 0x240 */
706 mxs_reg_32(usb2_misc); /* 0x250 */
707 reg_32(digprog); /* 0x260 */
708 reg_32(rsrvd); /* 0x270 */
709 reg_32(digprog_sololite); /* 0x280 */
712 #define ANATOP_PFD_FRAC_SHIFT(n) ((n) * 8)
713 #define ANATOP_PFD_FRAC_MASK(n) (0x3f << ANATOP_PFD_FRAC_SHIFT(n))
714 #define ANATOP_PFD_STABLE_SHIFT(n) (6 + ((n) * 8))
715 #define ANATOP_PFD_STABLE_MASK(n) (1 << ANATOP_PFD_STABLE_SHIFT(n))
716 #define ANATOP_PFD_CLKGATE_SHIFT(n) (7 + ((n) * 8))
717 #define ANATOP_PFD_CLKGATE_MASK(n) (1 << ANATOP_PFD_CLKGATE_SHIFT(n))
720 u16 wcr; /* Control */
721 u16 wsr; /* Service */
722 u16 wrsr; /* Reset Status */
723 u16 wicr; /* Interrupt Control */
724 u16 wmcr; /* Miscellaneous Control */
727 #define PWMCR_PRESCALER(x) ((((x) - 1) & 0xFFF) << 4)
728 #define PWMCR_DOZEEN (1 << 24)
729 #define PWMCR_WAITEN (1 << 23)
730 #define PWMCR_DBGEN (1 << 22)
731 #define PWMCR_CLKSRC_IPG_HIGH (2 << 16)
732 #define PWMCR_CLKSRC_IPG (1 << 16)
733 #define PWMCR_EN (1 << 0)
743 #endif /* __ASSEMBLER__*/
744 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */