arch/arm/include/asm/arch-mx6/imx-regs.h

   1 /*
   2  * Copyright (C) 2011 Freescale Semiconductor, Inc. All Rights Reserved.
   3  *
   4  * This program is free software; you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation; either version 2 of the License, or
   7  * (at your option) any later version.
   8
   9  * This program is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13
  14  * You should have received a copy of the GNU General Public License along
  15  * with this program; if not, write to the Free Software Foundation, Inc.,
  16  * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
  17  */
  18
  19 #ifndef __ASM_ARCH_MX6_IMX_REGS_H__
  20 #define __ASM_ARCH_MX6_IMX_REGS_H__
  21
  22 #define ARCH_MXC
  23
  24 #define CONFIG_SYS_CACHELINE_SIZE       32
  25
  26 #define ROMCP_ARB_BASE_ADDR             0x00000000
  27 #define ROMCP_ARB_END_ADDR              0x000FFFFF
  28 #define CAAM_ARB_BASE_ADDR              0x00100000
  29 #define CAAM_ARB_END_ADDR               0x00103FFF
  30 #define APBH_DMA_ARB_BASE_ADDR          0x00110000
  31 #define APBH_DMA_ARB_END_ADDR           0x00117FFF
  32 #define HDMI_ARB_BASE_ADDR              0x00120000
  33 #define HDMI_ARB_END_ADDR               0x00128FFF
  34 #define GPU_3D_ARB_BASE_ADDR            0x00130000
  35 #define GPU_3D_ARB_END_ADDR             0x00133FFF
  36 #define GPU_2D_ARB_BASE_ADDR            0x00134000
  37 #define GPU_2D_ARB_END_ADDR             0x00137FFF
  38 #define DTCP_ARB_BASE_ADDR              0x00138000
  39 #define DTCP_ARB_END_ADDR               0x0013BFFF
  40
  41 /* GPV - PL301 configuration ports */
  42 #define GPV2_BASE_ADDR                  0x00200000
  43 #define GPV3_BASE_ADDR                  0x00300000
  44 #define GPV4_BASE_ADDR                  0x00800000
  45 #define IRAM_BASE_ADDR                  0x00900000
  46 #define SCU_BASE_ADDR                   0x00A00000
  47 #define IC_INTERFACES_BASE_ADDR         0x00A00100
  48 #define GLOBAL_TIMER_BASE_ADDR          0x00A00200
  49 #define PRIVATE_TIMERS_WD_BASE_ADDR     0x00A00600
  50 #define IC_DISTRIBUTOR_BASE_ADDR        0x00A01000
  51 #define GPV0_BASE_ADDR                  0x00B00000
  52 #define GPV1_BASE_ADDR                  0x00C00000
  53 #define PCIE_ARB_BASE_ADDR              0x01000000
  54 #define PCIE_ARB_END_ADDR               0x01FFFFFF
  55
  56 #define AIPS1_ARB_BASE_ADDR             0x02000000
  57 #define AIPS1_ARB_END_ADDR              0x020FFFFF
  58 #define AIPS2_ARB_BASE_ADDR             0x02100000
  59 #define AIPS2_ARB_END_ADDR              0x021FFFFF
  60 #define SATA_ARB_BASE_ADDR              0x02200000
  61 #define SATA_ARB_END_ADDR               0x02203FFF
  62 #define OPENVG_ARB_BASE_ADDR            0x02204000
  63 #define OPENVG_ARB_END_ADDR             0x02207FFF
  64 #define HSI_ARB_BASE_ADDR               0x02208000
  65 #define HSI_ARB_END_ADDR                0x0220BFFF
  66 #define IPU1_ARB_BASE_ADDR              0x02400000
  67 #define IPU1_ARB_END_ADDR               0x027FFFFF
  68 #define IPU2_ARB_BASE_ADDR              0x02800000
  69 #define IPU2_ARB_END_ADDR               0x02BFFFFF
  70 #define WEIM_ARB_BASE_ADDR              0x08000000
  71 #define WEIM_ARB_END_ADDR               0x0FFFFFFF
  72
  73 #define MMDC0_ARB_BASE_ADDR             0x10000000
  74 #define MMDC0_ARB_END_ADDR              0x7FFFFFFF
  75 #define MMDC1_ARB_BASE_ADDR             0x80000000
  76 #define MMDC1_ARB_END_ADDR              0xFFFFFFFF
  77
  78 #define IPU_SOC_BASE_ADDR               IPU1_ARB_BASE_ADDR
  79 #define IPU_SOC_OFFSET                  0x00200000
  80
  81 /* Defines for Blocks connected via AIPS (SkyBlue) */
  82 #define ATZ1_BASE_ADDR              AIPS1_ARB_BASE_ADDR
  83 #define ATZ2_BASE_ADDR              AIPS2_ARB_BASE_ADDR
  84 #define AIPS1_BASE_ADDR             AIPS1_ON_BASE_ADDR
  85 #define AIPS2_BASE_ADDR             AIPS2_ON_BASE_ADDR
  86
  87 #define SPDIF_BASE_ADDR             (ATZ1_BASE_ADDR + 0x04000)
  88 #define ECSPI1_BASE_ADDR            (ATZ1_BASE_ADDR + 0x08000)
  89 #define ECSPI2_BASE_ADDR            (ATZ1_BASE_ADDR + 0x0C000)
  90 #define ECSPI3_BASE_ADDR            (ATZ1_BASE_ADDR + 0x10000)
  91 #define ECSPI4_BASE_ADDR            (ATZ1_BASE_ADDR + 0x14000)
  92 #define ECSPI5_BASE_ADDR            (ATZ1_BASE_ADDR + 0x18000)
  93 #define UART1_BASE                  (ATZ1_BASE_ADDR + 0x20000)
  94 #define ESAI1_BASE_ADDR             (ATZ1_BASE_ADDR + 0x24000)
  95 #define SSI1_BASE_ADDR              (ATZ1_BASE_ADDR + 0x28000)
  96 #define SSI2_BASE_ADDR              (ATZ1_BASE_ADDR + 0x2C000)
  97 #define SSI3_BASE_ADDR              (ATZ1_BASE_ADDR + 0x30000)
  98 #define ASRC_BASE_ADDR              (ATZ1_BASE_ADDR + 0x34000)
  99 #define SPBA_BASE_ADDR              (ATZ1_BASE_ADDR + 0x3C000)
 100 #define VPU_BASE_ADDR               (ATZ1_BASE_ADDR + 0x40000)
 101 #define AIPS1_ON_BASE_ADDR          (ATZ1_BASE_ADDR + 0x7C000)
 102
 103 #define AIPS1_OFF_BASE_ADDR         (ATZ1_BASE_ADDR + 0x80000)
 104 #define PWM1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x0000)
 105 #define PWM2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4000)
 106 #define PWM3_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x8000)
 107 #define PWM4_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0xC000)
 108 #define CAN1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x10000)
 109 #define CAN2_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x14000)
 110 #define GPT1_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x18000)
 111 #define GPIO1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x1C000)
 112 #define GPIO2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x20000)
 113 #define GPIO3_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x24000)
 114 #define GPIO4_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x28000)
 115 #define GPIO5_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x2C000)
 116 #define GPIO6_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x30000)
 117 #define GPIO7_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x34000)
 118 #define KPP_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x38000)
 119 #define WDOG1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x3C000)
 120 #define WDOG2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x40000)
 121 #define ANATOP_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x48000)
 122 #define USB_PHY0_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x49000)
 123 #define USB_PHY1_BASE_ADDR          (AIPS1_OFF_BASE_ADDR + 0x4a000)
 124 #define CCM_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x44000)
 125 #define SNVS_BASE_ADDR              (AIPS1_OFF_BASE_ADDR + 0x4C000)
 126 #define EPIT1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x50000)
 127 #define EPIT2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x54000)
 128 #define SRC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x58000)
 129 #define GPC_BASE_ADDR               (AIPS1_OFF_BASE_ADDR + 0x5C000)
 130 #define IOMUXC_BASE_ADDR            (AIPS1_OFF_BASE_ADDR + 0x60000)
 131 #define DCIC1_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x64000)
 132 #define DCIC2_BASE_ADDR             (AIPS1_OFF_BASE_ADDR + 0x68000)
 133 #define DMA_REQ_PORT_HOST_BASE_ADDR (AIPS1_OFF_BASE_ADDR + 0x6C000)
 134
 135 #define AIPS2_ON_BASE_ADDR          (ATZ2_BASE_ADDR + 0x7C000)
 136 #define AIPS2_OFF_BASE_ADDR         (ATZ2_BASE_ADDR + 0x80000)
 137 #define CAAM_BASE_ADDR              (ATZ2_BASE_ADDR)
 138 #define ARM_BASE_ADDR               (ATZ2_BASE_ADDR + 0x40000)
 139 #define USBOH3_PL301_BASE_ADDR      (AIPS2_OFF_BASE_ADDR + 0x0000)
 140 #define USBOH3_USB_BASE_ADDR        (AIPS2_OFF_BASE_ADDR + 0x4000)
 141 #define ENET_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x8000)
 142 #define MLB_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0xC000)
 143 #define USDHC1_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x10000)
 144 #define USDHC2_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x14000)
 145 #define USDHC3_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x18000)
 146 #define USDHC4_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x1C000)
 147 #define I2C1_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x20000)
 148 #define I2C2_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x24000)
 149 #define I2C3_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x28000)
 150 #define ROMCP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x2C000)
 151 #define MMDC_P0_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x30000)
 152 #define MMDC_P1_BASE_ADDR           (AIPS2_OFF_BASE_ADDR + 0x34000)
 153 #define WEIM_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x38000)
 154 #define OCOTP_BASE_ADDR             (AIPS2_OFF_BASE_ADDR + 0x3C000)
 155 #define CSU_BASE_ADDR               (AIPS2_OFF_BASE_ADDR + 0x40000)
 156 #define IP2APB_PERFMON1_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x44000)
 157 #define IP2APB_PERFMON2_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x48000)
 158 #define IP2APB_PERFMON3_BASE_ADDR   (AIPS2_OFF_BASE_ADDR + 0x4C000)
 159 #define IP2APB_TZASC1_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x50000)
 160 #define IP2APB_TZASC2_BASE_ADDR     (AIPS2_OFF_BASE_ADDR + 0x54000)
 161 #define AUDMUX_BASE_ADDR            (AIPS2_OFF_BASE_ADDR + 0x58000)
 162 #define MIPI_CSI2_BASE_ADDR         (AIPS2_OFF_BASE_ADDR + 0x5C000)
 163 #define MIPI_DSI_BASE_ADDR          (AIPS2_OFF_BASE_ADDR + 0x60000)
 164 #define VDOA_BASE_ADDR              (AIPS2_OFF_BASE_ADDR + 0x64000)
 165 #define UART2_BASE                  (AIPS2_OFF_BASE_ADDR + 0x68000)
 166 #define UART3_BASE                  (AIPS2_OFF_BASE_ADDR + 0x6C000)
 167 #define UART4_BASE                  (AIPS2_OFF_BASE_ADDR + 0x70000)
 168 #define UART5_BASE                  (AIPS2_OFF_BASE_ADDR + 0x74000)
 169 #define IP2APB_USBPHY1_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x78000)
 170 #define IP2APB_USBPHY2_BASE_ADDR    (AIPS2_OFF_BASE_ADDR + 0x7C000)
 171
 172 #define CHIP_REV_1_0                 0x10
 173 #define IRAM_SIZE                    0x00040000
 174 #define IMX_IIM_BASE                 OCOTP_BASE_ADDR
 175 #define FEC_QUIRK_ENET_MAC
 176
 177 #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__))
 178 #include <asm/types.h>
 179
 180 extern void imx_get_mac_from_fuse(int dev_id, unsigned char *mac);
 181
 182 /* System Reset Controller (SRC) */
 183 struct src {
 184         u32     scr;
 185         u32     sbmr1;
 186         u32     srsr;
 187         u32     reserved1[2];
 188         u32     sisr;
 189         u32     simr;
 190         u32     sbmr2;
 191         u32     gpr1;
 192         u32     gpr2;
 193         u32     gpr3;
 194         u32     gpr4;
 195         u32     gpr5;
 196         u32     gpr6;
 197         u32     gpr7;
 198         u32     gpr8;
 199         u32     gpr9;
 200         u32     gpr10;
 201 };
 202
 203 /* OCOTP Registers */
 204 struct ocotp_regs {
 205         u32     reserved[0x198];
 206         u32     gp1;    /* 0x660 */
 207 };
 208
 209 /* GPR3 bitfields */
 210 #define IOMUXC_GPR3_GPU_DBG_OFFSET              29
 211 #define IOMUXC_GPR3_GPU_DBG_MASK                (3<<IOMUXC_GPR3_GPU_DBG_OFFSET)
 212 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET     28
 213 #define IOMUXC_GPR3_BCH_WR_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_WR_CACHE_CTL_OFFSET)
 214 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET     27
 215 #define IOMUXC_GPR3_BCH_RD_CACHE_CTL_MASK       (1<<IOMUXC_GPR3_BCH_RD_CACHE_CTL_OFFSET)
 216 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET  26
 217 #define IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_WR_CACHE_CTL_OFFSET)
 218 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET  25
 219 #define IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_MASK    (1<<IOMUXC_GPR3_uSDHCx_RD_CACHE_CTL_OFFSET)
 220 #define IOMUXC_GPR3_OCRAM_CTL_OFFSET            21
 221 #define IOMUXC_GPR3_OCRAM_CTL_MASK              (0xf<<IOMUXC_GPR3_OCRAM_CTL_OFFSET)
 222 #define IOMUXC_GPR3_OCRAM_STATUS_OFFSET         17
 223 #define IOMUXC_GPR3_OCRAM_STATUS_MASK           (0xf<<IOMUXC_GPR3_OCRAM_STATUS_OFFSET)
 224 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET     16
 225 #define IOMUXC_GPR3_CORE3_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE3_DBG_ACK_EN_OFFSET)
 226 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET     15
 227 #define IOMUXC_GPR3_CORE2_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE2_DBG_ACK_EN_OFFSET)
 228 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET     14
 229 #define IOMUXC_GPR3_CORE1_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE1_DBG_ACK_EN_OFFSET)
 230 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET     13
 231 #define IOMUXC_GPR3_CORE0_DBG_ACK_EN_MASK       (1<<IOMUXC_GPR3_CORE0_DBG_ACK_EN_OFFSET)
 232 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET     12
 233 #define IOMUXC_GPR3_TZASC2_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC2_BOOT_LOCK_OFFSET)
 234 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET     11
 235 #define IOMUXC_GPR3_TZASC1_BOOT_LOCK_MASK       (1<<IOMUXC_GPR3_TZASC1_BOOT_LOCK_OFFSET)
 236 #define IOMUXC_GPR3_IPU_DIAG_OFFSET             10
 237 #define IOMUXC_GPR3_IPU_DIAG_MASK               (1<<IOMUXC_GPR3_IPU_DIAG_OFFSET)
 238
 239 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI0    0
 240 #define IOMUXC_GPR3_MUX_SRC_IPU1_DI1    1
 241 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI0    2
 242 #define IOMUXC_GPR3_MUX_SRC_IPU2_DI1    3
 243
 244 #define IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET        8
 245 #define IOMUXC_GPR3_LVDS1_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET)
 246
 247 #define IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET        6
 248 #define IOMUXC_GPR3_LVDS0_MUX_CTL_MASK          (3<<IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET)
 249
 250 #define IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET         4
 251 #define IOMUXC_GPR3_MIPI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_MIPI_MUX_CTL_OFFSET)
 252
 253 #define IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET         2
 254 #define IOMUXC_GPR3_HDMI_MUX_CTL_MASK           (3<<IOMUXC_GPR3_HDMI_MUX_CTL_OFFSET)
 255
 256
 257 struct iomuxc {
 258         u32 gpr[14];
 259         u32 omux[5];
 260         /* mux and pad registers */
 261 };
 262
 263 #define IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET            20
 264 #define IOMUXC_GPR2_COUNTER_RESET_VAL_MASK              (3<<IOMUXC_GPR2_COUNTER_RESET_VAL_OFFSET)
 265 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET               16
 266 #define IOMUXC_GPR2_LVDS_CLK_SHIFT_MASK                 (7<<IOMUXC_GPR2_LVDS_CLK_SHIFT_OFFSET)
 267
 268 #define IOMUXC_GPR2_BGREF_RRMODE_OFFSET                 15
 269 #define IOMUXC_GPR2_BGREF_RRMODE_MASK                   (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 270 #define IOMUXC_GPR2_BGREF_RRMODE_INTERNAL_RES           (1<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 271 #define IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES           (0<<IOMUXC_GPR2_BGREF_RRMODE_OFFSET)
 272 #define IOMUXC_GPR2_VSYNC_ACTIVE_HIGH   0
 273 #define IOMUXC_GPR2_VSYNC_ACTIVE_LOW    1
 274
 275 #define IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET              10
 276 #define IOMUXC_GPR2_DI1_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 277 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 278 #define IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI1_VS_POLARITY_OFFSET)
 279
 280 #define IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET              9
 281 #define IOMUXC_GPR2_DI0_VS_POLARITY_MASK                (1<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 282 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH         (IOMUXC_GPR2_VSYNC_ACTIVE_HIGH<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 283 #define IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW          (IOMUXC_GPR2_VSYNC_ACTIVE_LOW<<IOMUXC_GPR2_DI0_VS_POLARITY_OFFSET)
 284
 285 #define IOMUXC_GPR2_BITMAP_SPWG 0
 286 #define IOMUXC_GPR2_BITMAP_JEIDA        1
 287
 288 #define IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET              8
 289 #define IOMUXC_GPR2_BIT_MAPPING_CH1_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 290 #define IOMUXC_GPR2_BIT_MAPPING_CH1_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 291 #define IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH1_OFFSET)
 292
 293 #define IOMUXC_GPR2_DATA_WIDTH_18       0
 294 #define IOMUXC_GPR2_DATA_WIDTH_24       1
 295
 296 #define IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET               7
 297 #define IOMUXC_GPR2_DATA_WIDTH_CH1_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 298 #define IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 299 #define IOMUXC_GPR2_DATA_WIDTH_CH1_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH1_OFFSET)
 300
 301 #define IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET              6
 302 #define IOMUXC_GPR2_BIT_MAPPING_CH0_MASK                (1<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 303 #define IOMUXC_GPR2_BIT_MAPPING_CH0_JEIDA               (IOMUXC_GPR2_BITMAP_JEIDA<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 304 #define IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG                (IOMUXC_GPR2_BITMAP_SPWG<<IOMUXC_GPR2_BIT_MAPPING_CH0_OFFSET)
 305
 306 #define IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET               5
 307 #define IOMUXC_GPR2_DATA_WIDTH_CH0_MASK                 (1<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 308 #define IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT                (IOMUXC_GPR2_DATA_WIDTH_18<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 309 #define IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT                (IOMUXC_GPR2_DATA_WIDTH_24<<IOMUXC_GPR2_DATA_WIDTH_CH0_OFFSET)
 310
 311 #define IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET                4
 312 #define IOMUXC_GPR2_SPLIT_MODE_EN_MASK                  (1<<IOMUXC_GPR2_SPLIT_MODE_EN_OFFSET)
 313
 314 #define IOMUXC_GPR2_MODE_DISABLED       0
 315 #define IOMUXC_GPR2_MODE_ENABLED_DI0    1
 316 #define IOMUXC_GPR2_MODE_ENABLED_DI1    2
 317
 318 #define IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET                2
 319 #define IOMUXC_GPR2_LVDS_CH1_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 320 #define IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 321 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 322 #define IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH1_MODE_OFFSET)
 323
 324 #define IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET                0
 325 #define IOMUXC_GPR2_LVDS_CH0_MODE_MASK                  (3<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 326 #define IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED              (IOMUXC_GPR2_MODE_DISABLED<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 327 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0           (IOMUXC_GPR2_MODE_ENABLED_DI0<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 328 #define IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI1           (IOMUXC_GPR2_MODE_ENABLED_DI1<<IOMUXC_GPR2_LVDS_CH0_MODE_OFFSET)
 329
 330 /* ECSPI registers */
 331 struct cspi_regs {
 332         u32 rxdata;
 333         u32 txdata;
 334         u32 ctrl;
 335         u32 cfg;
 336         u32 intr;
 337         u32 dma;
 338         u32 stat;
 339         u32 period;
 340 };
 341
 342 /*
 343  * CSPI register definitions
 344  */
 345 #define MXC_ECSPI
 346 #define MXC_CSPICTRL_EN         (1 << 0)
 347 #define MXC_CSPICTRL_MODE       (1 << 1)
 348 #define MXC_CSPICTRL_XCH        (1 << 2)
 349 #define MXC_CSPICTRL_CHIPSELECT(x)      (((x) & 0x3) << 12)
 350 #define MXC_CSPICTRL_BITCOUNT(x)        (((x) & 0xfff) << 20)
 351 #define MXC_CSPICTRL_PREDIV(x)  (((x) & 0xF) << 12)
 352 #define MXC_CSPICTRL_POSTDIV(x) (((x) & 0xF) << 8)
 353 #define MXC_CSPICTRL_SELCHAN(x) (((x) & 0x3) << 18)
 354 #define MXC_CSPICTRL_MAXBITS    0xfff
 355 #define MXC_CSPICTRL_TC         (1 << 7)
 356 #define MXC_CSPICTRL_RXOVF      (1 << 6)
 357 #define MXC_CSPIPERIOD_32KHZ    (1 << 15)
 358 #define MAX_SPI_BYTES   32
 359
 360 /* Bit position inside CTRL register to be associated with SS */
 361 #define MXC_CSPICTRL_CHAN       18
 362
 363 /* Bit position inside CON register to be associated with SS */
 364 #define MXC_CSPICON_POL         4
 365 #define MXC_CSPICON_PHA         0
 366 #define MXC_CSPICON_SSPOL       12
 367 #define MXC_SPI_BASE_ADDRESSES \
 368         ECSPI1_BASE_ADDR, \
 369         ECSPI2_BASE_ADDR, \
 370         ECSPI3_BASE_ADDR, \
 371         ECSPI4_BASE_ADDR, \
 372         ECSPI5_BASE_ADDR
 373
 374 struct iim_regs {
 375         u32     ctrl;
 376         u32     ctrl_set;
 377         u32     ctrl_clr;
 378         u32     ctrl_tog;
 379         u32     timing;
 380         u32     rsvd0[3];
 381         u32     data;
 382         u32     rsvd1[3];
 383         u32     read_ctrl;
 384         u32     rsvd2[3];
 385         u32     fuse_data;
 386         u32     rsvd3[3];
 387         u32     sticky;
 388         u32     rsvd4[3];
 389         u32     scs;
 390         u32     scs_set;
 391         u32     scs_clr;
 392         u32     scs_tog;
 393         u32     crc_addr;
 394         u32     rsvd5[3];
 395         u32     crc_value;
 396         u32     rsvd6[3];
 397         u32     version;
 398         u32     rsvd7[0xdb];
 399
 400         struct fuse_bank {
 401                 u32     fuse_regs[0x20];
 402         } bank[15];
 403 };
 404
 405 struct fuse_bank4_regs {
 406         u32     sjc_resp_low;
 407         u32     rsvd0[3];
 408         u32     sjc_resp_high;
 409         u32     rsvd1[3];
 410         u32     mac_addr_low;
 411         u32     rsvd2[3];
 412         u32     mac_addr_high;
 413         u32     rsvd3[0x13];
 414 };
 415
 416 struct aipstz_regs {
 417         u32     mprot0;
 418         u32     mprot1;
 419         u32     rsvd[0xe];
 420         u32     opacr0;
 421         u32     opacr1;
 422         u32     opacr2;
 423         u32     opacr3;
 424         u32     opacr4;
 425 };
 426
 427 struct anatop_regs {
 428         u32     pll_sys;                /* 0x000 */
 429         u32     pll_sys_set;            /* 0x004 */
 430         u32     pll_sys_clr;            /* 0x008 */
 431         u32     pll_sys_tog;            /* 0x00c */
 432         u32     usb1_pll_480_ctrl;      /* 0x010 */
 433         u32     usb1_pll_480_ctrl_set;  /* 0x014 */
 434         u32     usb1_pll_480_ctrl_clr;  /* 0x018 */
 435         u32     usb1_pll_480_ctrl_tog;  /* 0x01c */
 436         u32     usb2_pll_480_ctrl;      /* 0x020 */
 437         u32     usb2_pll_480_ctrl_set;  /* 0x024 */
 438         u32     usb2_pll_480_ctrl_clr;  /* 0x028 */
 439         u32     usb2_pll_480_ctrl_tog;  /* 0x02c */
 440         u32     pll_528;                /* 0x030 */
 441         u32     pll_528_set;            /* 0x034 */
 442         u32     pll_528_clr;            /* 0x038 */
 443         u32     pll_528_tog;            /* 0x03c */
 444         u32     pll_528_ss;             /* 0x040 */
 445         u32     rsvd0[3];
 446         u32     pll_528_num;            /* 0x050 */
 447         u32     rsvd1[3];
 448         u32     pll_528_denom;          /* 0x060 */
 449         u32     rsvd2[3];
 450         u32     pll_audio;              /* 0x070 */
 451         u32     pll_audio_set;          /* 0x074 */
 452         u32     pll_audio_clr;          /* 0x078 */
 453         u32     pll_audio_tog;          /* 0x07c */
 454         u32     pll_audio_num;          /* 0x080 */
 455         u32     rsvd3[3];
 456         u32     pll_audio_denom;        /* 0x090 */
 457         u32     rsvd4[3];
 458         u32     pll_video;              /* 0x0a0 */
 459         u32     pll_video_set;          /* 0x0a4 */
 460         u32     pll_video_clr;          /* 0x0a8 */
 461         u32     pll_video_tog;          /* 0x0ac */
 462         u32     pll_video_num;          /* 0x0b0 */
 463         u32     rsvd5[3];
 464         u32     pll_video_denom;        /* 0x0c0 */
 465         u32     rsvd6[3];
 466         u32     pll_mlb;                /* 0x0d0 */
 467         u32     pll_mlb_set;            /* 0x0d4 */
 468         u32     pll_mlb_clr;            /* 0x0d8 */
 469         u32     pll_mlb_tog;            /* 0x0dc */
 470         u32     pll_enet;               /* 0x0e0 */
 471         u32     pll_enet_set;           /* 0x0e4 */
 472         u32     pll_enet_clr;           /* 0x0e8 */
 473         u32     pll_enet_tog;           /* 0x0ec */
 474         u32     pfd_480;                /* 0x0f0 */
 475         u32     pfd_480_set;            /* 0x0f4 */
 476         u32     pfd_480_clr;            /* 0x0f8 */
 477         u32     pfd_480_tog;            /* 0x0fc */
 478         u32     pfd_528;                /* 0x100 */
 479         u32     pfd_528_set;            /* 0x104 */
 480         u32     pfd_528_clr;            /* 0x108 */
 481         u32     pfd_528_tog;            /* 0x10c */
 482         u32     reg_1p1;                /* 0x110 */
 483         u32     reg_1p1_set;            /* 0x114 */
 484         u32     reg_1p1_clr;            /* 0x118 */
 485         u32     reg_1p1_tog;            /* 0x11c */
 486         u32     reg_3p0;                /* 0x120 */
 487         u32     reg_3p0_set;            /* 0x124 */
 488         u32     reg_3p0_clr;            /* 0x128 */
 489         u32     reg_3p0_tog;            /* 0x12c */
 490         u32     reg_2p5;                /* 0x130 */
 491         u32     reg_2p5_set;            /* 0x134 */
 492         u32     reg_2p5_clr;            /* 0x138 */
 493         u32     reg_2p5_tog;            /* 0x13c */
 494         u32     reg_core;               /* 0x140 */
 495         u32     reg_core_set;           /* 0x144 */
 496         u32     reg_core_clr;           /* 0x148 */
 497         u32     reg_core_tog;           /* 0x14c */
 498         u32     ana_misc0;              /* 0x150 */
 499         u32     ana_misc0_set;          /* 0x154 */
 500         u32     ana_misc0_clr;          /* 0x158 */
 501         u32     ana_misc0_tog;          /* 0x15c */
 502         u32     ana_misc1;              /* 0x160 */
 503         u32     ana_misc1_set;          /* 0x164 */
 504         u32     ana_misc1_clr;          /* 0x168 */
 505         u32     ana_misc1_tog;          /* 0x16c */
 506         u32     ana_misc2;              /* 0x170 */
 507         u32     ana_misc2_set;          /* 0x174 */
 508         u32     ana_misc2_clr;          /* 0x178 */
 509         u32     ana_misc2_tog;          /* 0x17c */
 510         u32     tempsense0;             /* 0x180 */
 511         u32     tempsense0_set;         /* 0x184 */
 512         u32     tempsense0_clr;         /* 0x188 */
 513         u32     tempsense0_tog;         /* 0x18c */
 514         u32     tempsense1;             /* 0x190 */
 515         u32     tempsense1_set;         /* 0x194 */
 516         u32     tempsense1_clr;         /* 0x198 */
 517         u32     tempsense1_tog;         /* 0x19c */
 518         u32     usb1_vbus_detect;       /* 0x1a0 */
 519         u32     usb1_vbus_detect_set;   /* 0x1a4 */
 520         u32     usb1_vbus_detect_clr;   /* 0x1a8 */
 521         u32     usb1_vbus_detect_tog;   /* 0x1ac */
 522         u32     usb1_chrg_detect;       /* 0x1b0 */
 523         u32     usb1_chrg_detect_set;   /* 0x1b4 */
 524         u32     usb1_chrg_detect_clr;   /* 0x1b8 */
 525         u32     usb1_chrg_detect_tog;   /* 0x1bc */
 526         u32     usb1_vbus_det_stat;     /* 0x1c0 */
 527         u32     usb1_vbus_det_stat_set; /* 0x1c4 */
 528         u32     usb1_vbus_det_stat_clr; /* 0x1c8 */
 529         u32     usb1_vbus_det_stat_tog; /* 0x1cc */
 530         u32     usb1_chrg_det_stat;     /* 0x1d0 */
 531         u32     usb1_chrg_det_stat_set; /* 0x1d4 */
 532         u32     usb1_chrg_det_stat_clr; /* 0x1d8 */
 533         u32     usb1_chrg_det_stat_tog; /* 0x1dc */
 534         u32     usb1_loopback;          /* 0x1e0 */
 535         u32     usb1_loopback_set;      /* 0x1e4 */
 536         u32     usb1_loopback_clr;      /* 0x1e8 */
 537         u32     usb1_loopback_tog;      /* 0x1ec */
 538         u32     usb1_misc;              /* 0x1f0 */
 539         u32     usb1_misc_set;          /* 0x1f4 */
 540         u32     usb1_misc_clr;          /* 0x1f8 */
 541         u32     usb1_misc_tog;          /* 0x1fc */
 542         u32     usb2_vbus_detect;       /* 0x200 */
 543         u32     usb2_vbus_detect_set;   /* 0x204 */
 544         u32     usb2_vbus_detect_clr;   /* 0x208 */
 545         u32     usb2_vbus_detect_tog;   /* 0x20c */
 546         u32     usb2_chrg_detect;       /* 0x210 */
 547         u32     usb2_chrg_detect_set;   /* 0x214 */
 548         u32     usb2_chrg_detect_clr;   /* 0x218 */
 549         u32     usb2_chrg_detect_tog;   /* 0x21c */
 550         u32     usb2_vbus_det_stat;     /* 0x220 */
 551         u32     usb2_vbus_det_stat_set; /* 0x224 */
 552         u32     usb2_vbus_det_stat_clr; /* 0x228 */
 553         u32     usb2_vbus_det_stat_tog; /* 0x22c */
 554         u32     usb2_chrg_det_stat;     /* 0x230 */
 555         u32     usb2_chrg_det_stat_set; /* 0x234 */
 556         u32     usb2_chrg_det_stat_clr; /* 0x238 */
 557         u32     usb2_chrg_det_stat_tog; /* 0x23c */
 558         u32     usb2_loopback;          /* 0x240 */
 559         u32     usb2_loopback_set;      /* 0x244 */
 560         u32     usb2_loopback_clr;      /* 0x248 */
 561         u32     usb2_loopback_tog;      /* 0x24c */
 562         u32     usb2_misc;              /* 0x250 */
 563         u32     usb2_misc_set;          /* 0x254 */
 564         u32     usb2_misc_clr;          /* 0x258 */
 565         u32     usb2_misc_tog;          /* 0x25c */
 566         u32     digprog;                /* 0x260 */
 567         u32     reserved1[7];
 568         u32     digprog_sololite;       /* 0x280 */
 569 };
 570
 571 #define ANATOP_PFD_480_PFD0_FRAC_SHIFT          0
 572 #define ANATOP_PFD_480_PFD0_FRAC_MASK           (0x3f<<ANATOP_PFD_480_PFD0_FRAC_SHIFT)
 573 #define ANATOP_PFD_480_PFD0_STABLE_SHIFT        6
 574 #define ANATOP_PFD_480_PFD0_STABLE_MASK         (1<<ANATOP_PFD_480_PFD0_STABLE_SHIFT)
 575 #define ANATOP_PFD_480_PFD0_CLKGATE_SHIFT       7
 576 #define ANATOP_PFD_480_PFD0_CLKGATE_MASK        (1<<ANATOP_PFD_480_PFD0_CLKGATE_SHIFT)
 577 #define ANATOP_PFD_480_PFD1_FRAC_SHIFT          8
 578 #define ANATOP_PFD_480_PFD1_FRAC_MASK           (0x3f<<ANATOP_PFD_480_PFD1_FRAC_SHIFT)
 579 #define ANATOP_PFD_480_PFD1_STABLE_SHIFT        14
 580 #define ANATOP_PFD_480_PFD1_STABLE_MASK         (1<<ANATOP_PFD_480_PFD1_STABLE_SHIFT)
 581 #define ANATOP_PFD_480_PFD1_CLKGATE_SHIFT       15
 582 #define ANATOP_PFD_480_PFD1_CLKGATE_MASK        (0x3f<<ANATOP_PFD_480_PFD1_CLKGATE_SHIFT)
 583 #define ANATOP_PFD_480_PFD2_FRAC_SHIFT          16
 584 #define ANATOP_PFD_480_PFD2_FRAC_MASK           (1<<ANATOP_PFD_480_PFD2_FRAC_SHIFT)
 585 #define ANATOP_PFD_480_PFD2_STABLE_SHIFT        22
 586 #define ANATOP_PFD_480_PFD2_STABLE_MASK (1<<ANATOP_PFD_480_PFD2_STABLE_SHIFT)
 587 #define ANATOP_PFD_480_PFD2_CLKGATE_SHIFT       23
 588 #define ANATOP_PFD_480_PFD2_CLKGATE_MASK        (0x3f<<ANATOP_PFD_480_PFD2_CLKGATE_SHIFT)
 589 #define ANATOP_PFD_480_PFD3_FRAC_SHIFT          24
 590 #define ANATOP_PFD_480_PFD3_FRAC_MASK           (1<<ANATOP_PFD_480_PFD3_FRAC_SHIFT)
 591 #define ANATOP_PFD_480_PFD3_STABLE_SHIFT        30
 592 #define ANATOP_PFD_480_PFD3_STABLE_MASK         (1<<ANATOP_PFD_480_PFD3_STABLE_SHIFT)
 593 #define ANATOP_PFD_480_PFD3_CLKGATE_SHIFT       31
 594
 595 struct iomuxc_base_regs {
 596         u32     gpr[14];        /* 0x000 */
 597         u32     obsrv[5];       /* 0x038 */
 598         u32     swmux_ctl[197]; /* 0x04c */
 599         u32     swpad_ctl[250]; /* 0x360 */
 600         u32     swgrp[26];      /* 0x748 */
 601         u32     daisy[104];     /* 0x7b0..94c */
 602 };
 603
 604 struct wdog_regs {
 605         u16     wcr;    /* Control */
 606         u16     wsr;    /* Service */
 607         u16     wrsr;   /* Reset Status */
 608         u16     wicr;   /* Interrupt Control */
 609         u16     wmcr;   /* Miscellaneous Control */
 610 };
 611
 612 #endif /* __ASSEMBLER__*/
 613 #endif /* __ASM_ARCH_MX6_IMX_REGS_H__ */