arch/arm/include/asm/arch-mx6/regs-ocotp.h

   1 /*
   2  * Freescale i.MX6 OCOTP Register Definitions
   3  *
   4  * Copyright (C) 2012 Lothar Waßmann <LW@KARO-electronics.de>
   5  * based on:
   6  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   7  * on behalf of DENX Software Engineering GmbH
   8  *
   9  * Based on code from LTIB:
  10  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
  11  *
  12  * This program is free software; you can redistribute it and/or modify
  13  * it under the terms of the GNU General Public License as published by
  14  * the Free Software Foundation; either version 2 of the License, or
  15  * (at your option) any later version.
  16  *
  17  * This program is distributed in the hope that it will be useful,
  18  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  19  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  20  * GNU General Public License for more details.
  21  *
  22  * You should have received a copy of the GNU General Public License
  23  * along with this program; if not, write to the Free Software
  24  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307 USA
  25  *
  26  */
  27
  28 #ifndef __MX6_REGS_OCOTP_H__
  29 #define __MX6_REGS_OCOTP_H__
  30
  31 #ifndef __ASSEMBLY__
  32 #define mx6_ocotp_reg_32(r)     mxs_reg_32(hw_ocotp_##r)
  33 #define ocotp_reg_32(r)         reg_32(hw_ocotp_##r)
  34
  35 struct mx6_ocotp_regs {
  36         mx6_ocotp_reg_32(ctrl);                 /* 0x000 */
  37         ocotp_reg_32(timing);                   /* 0x010 */
  38         ocotp_reg_32(data);                     /* 0x020 */
  39         ocotp_reg_32(read_ctrl);                /* 0x030 */
  40         ocotp_reg_32(read_fuse_data);           /* 0x040 */
  41         ocotp_reg_32(sw_sticky);                /* 0x050 */
  42         mx6_ocotp_reg_32(scs);                  /* 0x060 */
  43         reg_32(rsrvd1);                         /* 0x070 */
  44         reg_32(rsrvd2);                         /* 0x080 */
  45         ocotp_reg_32(version);                  /* 0x090 */
  46
  47         reg_32(rsrvd3[54]);                     /* 0x0a0 - 0x3ff */
  48
  49         /* bank 0 */
  50         ocotp_reg_32(lock);                     /* 0x400 */
  51         ocotp_reg_32(cfg0);                     /* 0x410 */
  52         ocotp_reg_32(cfg1);                     /* 0x420 */
  53         ocotp_reg_32(cfg2);                     /* 0x430 */
  54         ocotp_reg_32(cfg3);                     /* 0x440 */
  55         ocotp_reg_32(cfg4);                     /* 0x450 */
  56         ocotp_reg_32(cfg5);                     /* 0x460 */
  57         ocotp_reg_32(cfg6);                     /* 0x470 */
  58
  59         /* bank 1 */
  60         ocotp_reg_32(mem0);                     /* 0x480 */
  61         ocotp_reg_32(mem1);                     /* 0x490 */
  62         ocotp_reg_32(mem2);                     /* 0x4a0 */
  63         ocotp_reg_32(mem3);                     /* 0x4b0 */
  64         ocotp_reg_32(mem4);                     /* 0x4c0 */
  65         ocotp_reg_32(ana0);                     /* 0x4d0 */
  66         ocotp_reg_32(ana1);                     /* 0x4e0 */
  67         ocotp_reg_32(ana2);                     /* 0x4f0 */
  68
  69         /* bank 2 */
  70         reg_32(rsrvd4[8]);                      /* 0x500 - 0x57f */
  71
  72         /* bank 3 */
  73         ocotp_reg_32(srk0);                     /* 0x580 */
  74         ocotp_reg_32(srk1);                     /* 0x590 */
  75         ocotp_reg_32(srk2);                     /* 0x5a0 */
  76         ocotp_reg_32(srk3);                     /* 0x5b0 */
  77         ocotp_reg_32(srk4);                     /* 0x5c0 */
  78         ocotp_reg_32(srk5);                     /* 0x5d0 */
  79         ocotp_reg_32(srk6);                     /* 0x5e0 */
  80         ocotp_reg_32(srk7);                     /* 0x5f0 */
  81
  82         /* bank 4 */
  83         ocotp_reg_32(hsjc_resp0);               /* 0x600 */
  84         ocotp_reg_32(hsjc_resp1);               /* 0x610 */
  85         ocotp_reg_32(mac0);                     /* 0x620 */
  86         ocotp_reg_32(mac1);                     /* 0x630 */
  87         reg_32(rsrvd5[2]);                      /* 0x640 - 0x65f */
  88         ocotp_reg_32(gp1);                      /* 0x660 */
  89         ocotp_reg_32(gp2);                      /* 0x670 */
  90
  91         /* bank 5 */
  92         reg_32(rsrvd6[5]);                      /* 0x680 - 0x6cf */
  93         ocotp_reg_32(misc_conf);                /* 0x6d0 */
  94         ocotp_reg_32(field_return);             /* 0x6e0 */
  95         ocotp_reg_32(srk_revoke);               /* 0x6f0 */
  96 };
  97
  98 #endif
  99
 100 #define OCOTP_CTRL_BUSY                         (1 << 8)
 101 #define OCOTP_CTRL_ERROR                        (1 << 9)
 102 #define OCOTP_CTRL_RELOAD_SHADOWS               (1 << 10)
 103
 104 #define OCOTP_RD_CTRL_READ_FUSE                 (1 << 0)
 105
 106 #define OCOTP_VERSION_MAJOR_MASK                (0xff << 24)
 107 #define OCOTP_VERSION_MAJOR_OFFSET              24
 108 #define OCOTP_VERSION_MINOR_MASK                (0xff << 16)
 109 #define OCOTP_VERSION_MINOR_OFFSET              16
 110 #define OCOTP_VERSION_STEP_MASK                 0xffff
 111 #define OCOTP_VERSION_STEP_OFFSET               0
 112
 113 #endif /* __MX6_REGS_OCOTP_H__ */