2 * linux/include/asm-arm/arch-pxa/pxa-regs.h
4 * Author: Nicolas Pitre
5 * Created: Jun 15, 2001
6 * Copyright: MontaVista Software Inc.
8 * This program is free software; you can redistribute it and/or modify
9 * it under the terms of the GNU General Public License version 2 as
10 * published by the Free Software Foundation.
12 * - 2003/01/20: Robert Schwebel <r.schwebel@pengutronix.de
13 * Original file taken from linux-2.4.19-rmk4-pxa1. Added some definitions.
14 * Added include for hardware.h (for __REG definition)
22 /* FIXME hack so that SA-1111.h will work [cb] */
25 typedef unsigned short Word16 ;
26 typedef unsigned int Word32 ;
28 typedef Word Quad [4] ;
29 typedef void *Address ;
30 typedef void (*ExcpHndlr) (void) ;
36 #ifdef CONFIG_CPU_MONAHANS
37 #define PXA_CS0_PHYS 0x00000000 /* for both small and large same start */
38 #define PXA_CS1_PHYS 0x04000000 /* Small partition start address (64MB) */
39 #define PXA_CS1_LPHYS 0x30000000 /* Large partition start address (256MB) */
40 #define PXA_CS2_PHYS 0x10000000 /* (64MB) */
41 #define PXA_CS3_PHYS 0x14000000 /* (64MB) */
42 #define PXA_PCMCIA_PHYS 0x20000000 /* (256MB) */
44 #define PXA_CS0_PHYS 0x00000000
45 #define PXA_CS1_PHYS 0x04000000
46 #define PXA_CS2_PHYS 0x08000000
47 #define PXA_CS3_PHYS 0x0C000000
48 #define PXA_CS4_PHYS 0x10000000
49 #define PXA_CS5_PHYS 0x14000000
50 #endif /* CONFIG_CPU_MONAHANS */
53 * Personal Computer Memory Card International Association (PCMCIA) sockets
55 #define PCMCIAPrtSp 0x04000000 /* PCMCIA Partition Space [byte] */
56 #define PCMCIASp (4*PCMCIAPrtSp) /* PCMCIA Space [byte] */
57 #define PCMCIAIOSp PCMCIAPrtSp /* PCMCIA I/O Space [byte] */
58 #define PCMCIAAttrSp PCMCIAPrtSp /* PCMCIA Attribute Space [byte] */
59 #define PCMCIAMemSp PCMCIAPrtSp /* PCMCIA Memory Space [byte] */
61 #ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
62 #define PCMCIA0Sp PCMCIASp /* PCMCIA 0 Space [byte] */
63 #define PCMCIA0IOSp PCMCIAIOSp /* PCMCIA 0 I/O Space [byte] */
64 #define PCMCIA0AttrSp PCMCIAAttrSp /* PCMCIA 0 Attribute Space [byte] */
65 #define PCMCIA0MemSp PCMCIAMemSp /* PCMCIA 0 Memory Space [byte] */
68 #define PCMCIA1Sp PCMCIASp /* PCMCIA 1 Space [byte] */
69 #define PCMCIA1IOSp PCMCIAIOSp /* PCMCIA 1 I/O Space [byte] */
70 #define PCMCIA1AttrSp PCMCIAAttrSp /* PCMCIA 1 Attribute Space [byte] */
71 #define PCMCIA1MemSp PCMCIAMemSp /* PCMCIA 1 Memory Space [byte] */
73 #define _PCMCIA(Nb) /* PCMCIA [0..1] */ \
74 (0x20000000 + (Nb)*PCMCIASp)
75 #define _PCMCIAIO(Nb) _PCMCIA (Nb) /* PCMCIA I/O [0..1] */
76 #define _PCMCIAAttr(Nb) /* PCMCIA Attribute [0..1] */ \
77 (_PCMCIA (Nb) + 2*PCMCIAPrtSp)
78 #define _PCMCIAMem(Nb) /* PCMCIA Memory [0..1] */ \
79 (_PCMCIA (Nb) + 3*PCMCIAPrtSp)
81 #define _PCMCIA0 _PCMCIA (0) /* PCMCIA 0 */
82 #define _PCMCIA0IO _PCMCIAIO (0) /* PCMCIA 0 I/O */
83 #define _PCMCIA0Attr _PCMCIAAttr (0) /* PCMCIA 0 Attribute */
84 #define _PCMCIA0Mem _PCMCIAMem (0) /* PCMCIA 0 Memory */
86 #ifndef CONFIG_CPU_MONAHANS /* Monahans supports only one slot */
87 #define _PCMCIA1 _PCMCIA (1) /* PCMCIA 1 */
88 #define _PCMCIA1IO _PCMCIAIO (1) /* PCMCIA 1 I/O */
89 #define _PCMCIA1Attr _PCMCIAAttr (1) /* PCMCIA 1 Attribute */
90 #define _PCMCIA1Mem _PCMCIAMem (1) /* PCMCIA 1 Memory */
96 #define DCSR0 __REG(0x40000000) /* DMA Control / Status Register for Channel 0 */
97 #define DCSR1 __REG(0x40000004) /* DMA Control / Status Register for Channel 1 */
98 #define DCSR2 __REG(0x40000008) /* DMA Control / Status Register for Channel 2 */
99 #define DCSR3 __REG(0x4000000c) /* DMA Control / Status Register for Channel 3 */
100 #define DCSR4 __REG(0x40000010) /* DMA Control / Status Register for Channel 4 */
101 #define DCSR5 __REG(0x40000014) /* DMA Control / Status Register for Channel 5 */
102 #define DCSR6 __REG(0x40000018) /* DMA Control / Status Register for Channel 6 */
103 #define DCSR7 __REG(0x4000001c) /* DMA Control / Status Register for Channel 7 */
104 #define DCSR8 __REG(0x40000020) /* DMA Control / Status Register for Channel 8 */
105 #define DCSR9 __REG(0x40000024) /* DMA Control / Status Register for Channel 9 */
106 #define DCSR10 __REG(0x40000028) /* DMA Control / Status Register for Channel 10 */
107 #define DCSR11 __REG(0x4000002c) /* DMA Control / Status Register for Channel 11 */
108 #define DCSR12 __REG(0x40000030) /* DMA Control / Status Register for Channel 12 */
109 #define DCSR13 __REG(0x40000034) /* DMA Control / Status Register for Channel 13 */
110 #define DCSR14 __REG(0x40000038) /* DMA Control / Status Register for Channel 14 */
111 #define DCSR15 __REG(0x4000003c) /* DMA Control / Status Register for Channel 15 */
112 #ifdef CONFIG_CPU_MONAHANS
113 #define DCSR16 __REG(0x40000040) /* DMA Control / Status Register for Channel 16 */
114 #define DCSR17 __REG(0x40000044) /* DMA Control / Status Register for Channel 17 */
115 #define DCSR18 __REG(0x40000048) /* DMA Control / Status Register for Channel 18 */
116 #define DCSR19 __REG(0x4000004c) /* DMA Control / Status Register for Channel 19 */
117 #define DCSR20 __REG(0x40000050) /* DMA Control / Status Register for Channel 20 */
118 #define DCSR21 __REG(0x40000054) /* DMA Control / Status Register for Channel 21 */
119 #define DCSR22 __REG(0x40000058) /* DMA Control / Status Register for Channel 22 */
120 #define DCSR23 __REG(0x4000005c) /* DMA Control / Status Register for Channel 23 */
121 #define DCSR24 __REG(0x40000060) /* DMA Control / Status Register for Channel 24 */
122 #define DCSR25 __REG(0x40000064) /* DMA Control / Status Register for Channel 25 */
123 #define DCSR26 __REG(0x40000068) /* DMA Control / Status Register for Channel 26 */
124 #define DCSR27 __REG(0x4000006c) /* DMA Control / Status Register for Channel 27 */
125 #define DCSR28 __REG(0x40000070) /* DMA Control / Status Register for Channel 28 */
126 #define DCSR29 __REG(0x40000074) /* DMA Control / Status Register for Channel 29 */
127 #define DCSR30 __REG(0x40000078) /* DMA Control / Status Register for Channel 30 */
128 #define DCSR31 __REG(0x4000007c) /* DMA Control / Status Register for Channel 31 */
129 #endif /* CONFIG_CPU_MONAHANS */
131 #define DCSR(x) __REG2(0x40000000, (x) << 2)
133 #define DCSR_RUN (1 << 31) /* Run Bit (read / write) */
134 #define DCSR_NODESC (1 << 30) /* No-Descriptor Fetch (read / write) */
135 #define DCSR_STOPIRQEN (1 << 29) /* Stop Interrupt Enable (read / write) */
137 #if defined(CONFIG_PXA27X) || defined (CONFIG_CPU_MONAHANS)
138 #define DCSR_EORIRQEN (1 << 28) /* End of Receive Interrupt Enable (R/W) */
139 #define DCSR_EORJMPEN (1 << 27) /* Jump to next descriptor on EOR */
140 #define DCSR_EORSTOPEN (1 << 26) /* STOP on an EOR */
141 #define DCSR_SETCMPST (1 << 25) /* Set Descriptor Compare Status */
142 #define DCSR_CLRCMPST (1 << 24) /* Clear Descriptor Compare Status */
143 #define DCSR_CMPST (1 << 10) /* The Descriptor Compare Status */
144 #define DCSR_ENRINTR (1 << 9) /* The end of Receive */
147 #define DCSR_REQPEND (1 << 8) /* Request Pending (read-only) */
148 #define DCSR_STOPSTATE (1 << 3) /* Stop State (read-only) */
149 #define DCSR_ENDINTR (1 << 2) /* End Interrupt (read / write) */
150 #define DCSR_STARTINTR (1 << 1) /* Start Interrupt (read / write) */
151 #define DCSR_BUSERR (1 << 0) /* Bus Error Interrupt (read / write) */
153 #define DINT __REG(0x400000f0) /* DMA Interrupt Register */
155 #define DRCMR0 __REG(0x40000100) /* Request to Channel Map Register for DREQ 0 */
156 #define DRCMR1 __REG(0x40000104) /* Request to Channel Map Register for DREQ 1 */
157 #define DRCMR2 __REG(0x40000108) /* Request to Channel Map Register for I2S receive Request */
158 #define DRCMR3 __REG(0x4000010c) /* Request to Channel Map Register for I2S transmit Request */
159 #define DRCMR4 __REG(0x40000110) /* Request to Channel Map Register for BTUART receive Request */
160 #define DRCMR5 __REG(0x40000114) /* Request to Channel Map Register for BTUART transmit Request. */
161 #define DRCMR6 __REG(0x40000118) /* Request to Channel Map Register for FFUART receive Request */
162 #define DRCMR7 __REG(0x4000011c) /* Request to Channel Map Register for FFUART transmit Request */
163 #define DRCMR8 __REG(0x40000120) /* Request to Channel Map Register for AC97 microphone Request */
164 #define DRCMR9 __REG(0x40000124) /* Request to Channel Map Register for AC97 modem receive Request */
165 #define DRCMR10 __REG(0x40000128) /* Request to Channel Map Register for AC97 modem transmit Request */
166 #define DRCMR11 __REG(0x4000012c) /* Request to Channel Map Register for AC97 audio receive Request */
167 #define DRCMR12 __REG(0x40000130) /* Request to Channel Map Register for AC97 audio transmit Request */
168 #define DRCMR13 __REG(0x40000134) /* Request to Channel Map Register for SSP receive Request */
169 #define DRCMR14 __REG(0x40000138) /* Request to Channel Map Register for SSP transmit Request */
170 #define DRCMR15 __REG(0x4000013c) /* Reserved */
171 #define DRCMR16 __REG(0x40000140) /* Reserved */
172 #define DRCMR17 __REG(0x40000144) /* Request to Channel Map Register for ICP receive Request */
173 #define DRCMR18 __REG(0x40000148) /* Request to Channel Map Register for ICP transmit Request */
174 #define DRCMR19 __REG(0x4000014c) /* Request to Channel Map Register for STUART receive Request */
175 #define DRCMR20 __REG(0x40000150) /* Request to Channel Map Register for STUART transmit Request */
176 #define DRCMR21 __REG(0x40000154) /* Request to Channel Map Register for MMC receive Request */
177 #define DRCMR22 __REG(0x40000158) /* Request to Channel Map Register for MMC transmit Request */
178 #define DRCMR23 __REG(0x4000015c) /* Reserved */
179 #define DRCMR24 __REG(0x40000160) /* Reserved */
180 #define DRCMR25 __REG(0x40000164) /* Request to Channel Map Register for USB endpoint 1 Request */
181 #define DRCMR26 __REG(0x40000168) /* Request to Channel Map Register for USB endpoint 2 Request */
182 #define DRCMR27 __REG(0x4000016C) /* Request to Channel Map Register for USB endpoint 3 Request */
183 #define DRCMR28 __REG(0x40000170) /* Request to Channel Map Register for USB endpoint 4 Request */
184 #define DRCMR29 __REG(0x40000174) /* Reserved */
185 #define DRCMR30 __REG(0x40000178) /* Request to Channel Map Register for USB endpoint 6 Request */
186 #define DRCMR31 __REG(0x4000017C) /* Request to Channel Map Register for USB endpoint 7 Request */
187 #define DRCMR32 __REG(0x40000180) /* Request to Channel Map Register for USB endpoint 8 Request */
188 #define DRCMR33 __REG(0x40000184) /* Request to Channel Map Register for USB endpoint 9 Request */
189 #define DRCMR34 __REG(0x40000188) /* Reserved */
190 #define DRCMR35 __REG(0x4000018C) /* Request to Channel Map Register for USB endpoint 11 Request */
191 #define DRCMR36 __REG(0x40000190) /* Request to Channel Map Register for USB endpoint 12 Request */
192 #define DRCMR37 __REG(0x40000194) /* Request to Channel Map Register for USB endpoint 13 Request */
193 #define DRCMR38 __REG(0x40000198) /* Request to Channel Map Register for USB endpoint 14 Request */
194 #define DRCMR39 __REG(0x4000019C) /* Reserved */
196 #define DRCMR68 __REG(0x40001110) /* Request to Channel Map Register for Camera FIFO 0 Request */
197 #define DRCMR69 __REG(0x40001114) /* Request to Channel Map Register for Camera FIFO 1 Request */
198 #define DRCMR70 __REG(0x40001118) /* Request to Channel Map Register for Camera FIFO 2 Request */
200 #define DRCMRRXSADR DRCMR2
201 #define DRCMRTXSADR DRCMR3
202 #define DRCMRRXBTRBR DRCMR4
203 #define DRCMRTXBTTHR DRCMR5
204 #define DRCMRRXFFRBR DRCMR6
205 #define DRCMRTXFFTHR DRCMR7
206 #define DRCMRRXMCDR DRCMR8
207 #define DRCMRRXMODR DRCMR9
208 #define DRCMRTXMODR DRCMR10
209 #define DRCMRRXPCDR DRCMR11
210 #define DRCMRTXPCDR DRCMR12
211 #define DRCMRRXSSDR DRCMR13
212 #define DRCMRTXSSDR DRCMR14
213 #define DRCMRRXICDR DRCMR17
214 #define DRCMRTXICDR DRCMR18
215 #define DRCMRRXSTRBR DRCMR19
216 #define DRCMRTXSTTHR DRCMR20
217 #define DRCMRRXMMC DRCMR21
218 #define DRCMRTXMMC DRCMR22
220 #define DRCMR_MAPVLD (1 << 7) /* Map Valid (read / write) */
221 #define DRCMR_CHLNUM 0x0f /* mask for Channel Number (read / write) */
223 #define DDADR0 __REG(0x40000200) /* DMA Descriptor Address Register Channel 0 */
224 #define DSADR0 __REG(0x40000204) /* DMA Source Address Register Channel 0 */
225 #define DTADR0 __REG(0x40000208) /* DMA Target Address Register Channel 0 */
226 #define DCMD0 __REG(0x4000020c) /* DMA Command Address Register Channel 0 */
227 #define DDADR1 __REG(0x40000210) /* DMA Descriptor Address Register Channel 1 */
228 #define DSADR1 __REG(0x40000214) /* DMA Source Address Register Channel 1 */
229 #define DTADR1 __REG(0x40000218) /* DMA Target Address Register Channel 1 */
230 #define DCMD1 __REG(0x4000021c) /* DMA Command Address Register Channel 1 */
231 #define DDADR2 __REG(0x40000220) /* DMA Descriptor Address Register Channel 2 */
232 #define DSADR2 __REG(0x40000224) /* DMA Source Address Register Channel 2 */
233 #define DTADR2 __REG(0x40000228) /* DMA Target Address Register Channel 2 */
234 #define DCMD2 __REG(0x4000022c) /* DMA Command Address Register Channel 2 */
235 #define DDADR3 __REG(0x40000230) /* DMA Descriptor Address Register Channel 3 */
236 #define DSADR3 __REG(0x40000234) /* DMA Source Address Register Channel 3 */
237 #define DTADR3 __REG(0x40000238) /* DMA Target Address Register Channel 3 */
238 #define DCMD3 __REG(0x4000023c) /* DMA Command Address Register Channel 3 */
239 #define DDADR4 __REG(0x40000240) /* DMA Descriptor Address Register Channel 4 */
240 #define DSADR4 __REG(0x40000244) /* DMA Source Address Register Channel 4 */
241 #define DTADR4 __REG(0x40000248) /* DMA Target Address Register Channel 4 */
242 #define DCMD4 __REG(0x4000024c) /* DMA Command Address Register Channel 4 */
243 #define DDADR5 __REG(0x40000250) /* DMA Descriptor Address Register Channel 5 */
244 #define DSADR5 __REG(0x40000254) /* DMA Source Address Register Channel 5 */
245 #define DTADR5 __REG(0x40000258) /* DMA Target Address Register Channel 5 */
246 #define DCMD5 __REG(0x4000025c) /* DMA Command Address Register Channel 5 */
247 #define DDADR6 __REG(0x40000260) /* DMA Descriptor Address Register Channel 6 */
248 #define DSADR6 __REG(0x40000264) /* DMA Source Address Register Channel 6 */
249 #define DTADR6 __REG(0x40000268) /* DMA Target Address Register Channel 6 */
250 #define DCMD6 __REG(0x4000026c) /* DMA Command Address Register Channel 6 */
251 #define DDADR7 __REG(0x40000270) /* DMA Descriptor Address Register Channel 7 */
252 #define DSADR7 __REG(0x40000274) /* DMA Source Address Register Channel 7 */
253 #define DTADR7 __REG(0x40000278) /* DMA Target Address Register Channel 7 */
254 #define DCMD7 __REG(0x4000027c) /* DMA Command Address Register Channel 7 */
255 #define DDADR8 __REG(0x40000280) /* DMA Descriptor Address Register Channel 8 */
256 #define DSADR8 __REG(0x40000284) /* DMA Source Address Register Channel 8 */
257 #define DTADR8 __REG(0x40000288) /* DMA Target Address Register Channel 8 */
258 #define DCMD8 __REG(0x4000028c) /* DMA Command Address Register Channel 8 */
259 #define DDADR9 __REG(0x40000290) /* DMA Descriptor Address Register Channel 9 */
260 #define DSADR9 __REG(0x40000294) /* DMA Source Address Register Channel 9 */
261 #define DTADR9 __REG(0x40000298) /* DMA Target Address Register Channel 9 */
262 #define DCMD9 __REG(0x4000029c) /* DMA Command Address Register Channel 9 */
263 #define DDADR10 __REG(0x400002a0) /* DMA Descriptor Address Register Channel 10 */
264 #define DSADR10 __REG(0x400002a4) /* DMA Source Address Register Channel 10 */
265 #define DTADR10 __REG(0x400002a8) /* DMA Target Address Register Channel 10 */
266 #define DCMD10 __REG(0x400002ac) /* DMA Command Address Register Channel 10 */
267 #define DDADR11 __REG(0x400002b0) /* DMA Descriptor Address Register Channel 11 */
268 #define DSADR11 __REG(0x400002b4) /* DMA Source Address Register Channel 11 */
269 #define DTADR11 __REG(0x400002b8) /* DMA Target Address Register Channel 11 */
270 #define DCMD11 __REG(0x400002bc) /* DMA Command Address Register Channel 11 */
271 #define DDADR12 __REG(0x400002c0) /* DMA Descriptor Address Register Channel 12 */
272 #define DSADR12 __REG(0x400002c4) /* DMA Source Address Register Channel 12 */
273 #define DTADR12 __REG(0x400002c8) /* DMA Target Address Register Channel 12 */
274 #define DCMD12 __REG(0x400002cc) /* DMA Command Address Register Channel 12 */
275 #define DDADR13 __REG(0x400002d0) /* DMA Descriptor Address Register Channel 13 */
276 #define DSADR13 __REG(0x400002d4) /* DMA Source Address Register Channel 13 */
277 #define DTADR13 __REG(0x400002d8) /* DMA Target Address Register Channel 13 */
278 #define DCMD13 __REG(0x400002dc) /* DMA Command Address Register Channel 13 */
279 #define DDADR14 __REG(0x400002e0) /* DMA Descriptor Address Register Channel 14 */
280 #define DSADR14 __REG(0x400002e4) /* DMA Source Address Register Channel 14 */
281 #define DTADR14 __REG(0x400002e8) /* DMA Target Address Register Channel 14 */
282 #define DCMD14 __REG(0x400002ec) /* DMA Command Address Register Channel 14 */
283 #define DDADR15 __REG(0x400002f0) /* DMA Descriptor Address Register Channel 15 */
284 #define DSADR15 __REG(0x400002f4) /* DMA Source Address Register Channel 15 */
285 #define DTADR15 __REG(0x400002f8) /* DMA Target Address Register Channel 15 */
286 #define DCMD15 __REG(0x400002fc) /* DMA Command Address Register Channel 15 */
288 #define DDADR(x) __REG2(0x40000200, (x) << 4)
289 #define DSADR(x) __REG2(0x40000204, (x) << 4)
290 #define DTADR(x) __REG2(0x40000208, (x) << 4)
291 #define DCMD(x) __REG2(0x4000020c, (x) << 4)
293 #define DDADR_DESCADDR 0xfffffff0 /* Address of next descriptor (mask) */
294 #define DDADR_STOP (1 << 0) /* Stop (read / write) */
296 #define DCMD_INCSRCADDR (1 << 31) /* Source Address Increment Setting. */
297 #define DCMD_INCTRGADDR (1 << 30) /* Target Address Increment Setting. */
298 #define DCMD_FLOWSRC (1 << 29) /* Flow Control by the source. */
299 #define DCMD_FLOWTRG (1 << 28) /* Flow Control by the target. */
300 #define DCMD_STARTIRQEN (1 << 22) /* Start Interrupt Enable */
301 #define DCMD_ENDIRQEN (1 << 21) /* End Interrupt Enable */
302 #define DCMD_ENDIAN (1 << 18) /* Device Endian-ness. */
303 #define DCMD_BURST8 (1 << 16) /* 8 byte burst */
304 #define DCMD_BURST16 (2 << 16) /* 16 byte burst */
305 #define DCMD_BURST32 (3 << 16) /* 32 byte burst */
306 #define DCMD_WIDTH1 (1 << 14) /* 1 byte width */
307 #define DCMD_WIDTH2 (2 << 14) /* 2 byte width (HalfWord) */
308 #define DCMD_WIDTH4 (3 << 14) /* 4 byte width (Word) */
309 #define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
311 /* default combinations */
312 #define DCMD_RXPCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
313 #define DCMD_RXMCDR (DCMD_INCTRGADDR|DCMD_FLOWSRC|DCMD_BURST32|DCMD_WIDTH4)
314 #define DCMD_TXPCDR (DCMD_INCSRCADDR|DCMD_FLOWTRG|DCMD_BURST32|DCMD_WIDTH4)
319 /* Full Function UART (FFUART) */
321 #define FFRBR __REG(0x40100000) /* Receive Buffer Register (read only) */
322 #define FFTHR __REG(0x40100000) /* Transmit Holding Register (write only) */
323 #define FFIER __REG(0x40100004) /* Interrupt Enable Register (read/write) */
324 #define FFIIR __REG(0x40100008) /* Interrupt ID Register (read only) */
325 #define FFFCR __REG(0x40100008) /* FIFO Control Register (write only) */
326 #define FFLCR __REG(0x4010000C) /* Line Control Register (read/write) */
327 #define FFMCR __REG(0x40100010) /* Modem Control Register (read/write) */
328 #define FFLSR __REG(0x40100014) /* Line Status Register (read only) */
329 #define FFMSR __REG(0x40100018) /* Modem Status Register (read only) */
330 #define FFSPR __REG(0x4010001C) /* Scratch Pad Register (read/write) */
331 #define FFISR __REG(0x40100020) /* Infrared Selection Register (read/write) */
332 #define FFDLL __REG(0x40100000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
333 #define FFDLH __REG(0x40100004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
335 /* Bluetooth UART (BTUART) */
337 #define BTRBR __REG(0x40200000) /* Receive Buffer Register (read only) */
338 #define BTTHR __REG(0x40200000) /* Transmit Holding Register (write only) */
339 #define BTIER __REG(0x40200004) /* Interrupt Enable Register (read/write) */
340 #define BTIIR __REG(0x40200008) /* Interrupt ID Register (read only) */
341 #define BTFCR __REG(0x40200008) /* FIFO Control Register (write only) */
342 #define BTLCR __REG(0x4020000C) /* Line Control Register (read/write) */
343 #define BTMCR __REG(0x40200010) /* Modem Control Register (read/write) */
344 #define BTLSR __REG(0x40200014) /* Line Status Register (read only) */
345 #define BTMSR __REG(0x40200018) /* Modem Status Register (read only) */
346 #define BTSPR __REG(0x4020001C) /* Scratch Pad Register (read/write) */
347 #define BTISR __REG(0x40200020) /* Infrared Selection Register (read/write) */
348 #define BTDLL __REG(0x40200000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
349 #define BTDLH __REG(0x40200004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
351 /* Standard UART (STUART) */
353 #define STRBR __REG(0x40700000) /* Receive Buffer Register (read only) */
354 #define STTHR __REG(0x40700000) /* Transmit Holding Register (write only) */
355 #define STIER __REG(0x40700004) /* Interrupt Enable Register (read/write) */
356 #define STIIR __REG(0x40700008) /* Interrupt ID Register (read only) */
357 #define STFCR __REG(0x40700008) /* FIFO Control Register (write only) */
358 #define STLCR __REG(0x4070000C) /* Line Control Register (read/write) */
359 #define STMCR __REG(0x40700010) /* Modem Control Register (read/write) */
360 #define STLSR __REG(0x40700014) /* Line Status Register (read only) */
361 #define STMSR __REG(0x40700018) /* Reserved */
362 #define STSPR __REG(0x4070001C) /* Scratch Pad Register (read/write) */
363 #define STISR __REG(0x40700020) /* Infrared Selection Register (read/write) */
364 #define STDLL __REG(0x40700000) /* Divisor Latch Low Register (DLAB = 1) (read/write) */
365 #define STDLH __REG(0x40700004) /* Divisor Latch High Register (DLAB = 1) (read/write) */
367 #define IER_DMAE (1 << 7) /* DMA Requests Enable */
368 #define IER_UUE (1 << 6) /* UART Unit Enable */
369 #define IER_NRZE (1 << 5) /* NRZ coding Enable */
370 #define IER_RTIOE (1 << 4) /* Receiver Time Out Interrupt Enable */
371 #define IER_MIE (1 << 3) /* Modem Interrupt Enable */
372 #define IER_RLSE (1 << 2) /* Receiver Line Status Interrupt Enable */
373 #define IER_TIE (1 << 1) /* Transmit Data request Interrupt Enable */
374 #define IER_RAVIE (1 << 0) /* Receiver Data Available Interrupt Enable */
376 #define IIR_FIFOES1 (1 << 7) /* FIFO Mode Enable Status */
377 #define IIR_FIFOES0 (1 << 6) /* FIFO Mode Enable Status */
378 #define IIR_TOD (1 << 3) /* Time Out Detected */
379 #define IIR_IID2 (1 << 2) /* Interrupt Source Encoded */
380 #define IIR_IID1 (1 << 1) /* Interrupt Source Encoded */
381 #define IIR_IP (1 << 0) /* Interrupt Pending (active low) */
383 #define FCR_ITL2 (1 << 7) /* Interrupt Trigger Level */
384 #define FCR_ITL1 (1 << 6) /* Interrupt Trigger Level */
385 #define FCR_RESETTF (1 << 2) /* Reset Transmitter FIFO */
386 #define FCR_RESETRF (1 << 1) /* Reset Receiver FIFO */
387 #define FCR_TRFIFOE (1 << 0) /* Transmit and Receive FIFO Enable */
388 #define FCR_ITL_1 (0)
389 #define FCR_ITL_8 (FCR_ITL1)
390 #define FCR_ITL_16 (FCR_ITL2)
391 #define FCR_ITL_32 (FCR_ITL2|FCR_ITL1)
393 #define LCR_DLAB (1 << 7) /* Divisor Latch Access Bit */
394 #define LCR_SB (1 << 6) /* Set Break */
395 #define LCR_STKYP (1 << 5) /* Sticky Parity */
396 #define LCR_EPS (1 << 4) /* Even Parity Select */
397 #define LCR_PEN (1 << 3) /* Parity Enable */
398 #define LCR_STB (1 << 2) /* Stop Bit */
399 #define LCR_WLS1 (1 << 1) /* Word Length Select */
400 #define LCR_WLS0 (1 << 0) /* Word Length Select */
402 #define LSR_FIFOE (1 << 7) /* FIFO Error Status */
403 #define LSR_TEMT (1 << 6) /* Transmitter Empty */
404 #define LSR_TDRQ (1 << 5) /* Transmit Data Request */
405 #define LSR_BI (1 << 4) /* Break Interrupt */
406 #define LSR_FE (1 << 3) /* Framing Error */
407 #define LSR_PE (1 << 2) /* Parity Error */
408 #define LSR_OE (1 << 1) /* Overrun Error */
409 #define LSR_DR (1 << 0) /* Data Ready */
411 #define MCR_LOOP (1 << 4) */
412 #define MCR_OUT2 (1 << 3) /* force MSR_DCD in loopback mode */
413 #define MCR_OUT1 (1 << 2) /* force MSR_RI in loopback mode */
414 #define MCR_RTS (1 << 1) /* Request to Send */
415 #define MCR_DTR (1 << 0) /* Data Terminal Ready */
417 #define MSR_DCD (1 << 7) /* Data Carrier Detect */
418 #define MSR_RI (1 << 6) /* Ring Indicator */
419 #define MSR_DSR (1 << 5) /* Data Set Ready */
420 #define MSR_CTS (1 << 4) /* Clear To Send */
421 #define MSR_DDCD (1 << 3) /* Delta Data Carrier Detect */
422 #define MSR_TERI (1 << 2) /* Trailing Edge Ring Indicator */
423 #define MSR_DDSR (1 << 1) /* Delta Data Set Ready */
424 #define MSR_DCTS (1 << 0) /* Delta Clear To Send */
427 * IrSR (Infrared Selection Register)
429 #define IrSR_OFFSET 0x20
431 #define IrSR_RXPL_NEG_IS_ZERO (1<<4)
432 #define IrSR_RXPL_POS_IS_ZERO 0x0
433 #define IrSR_TXPL_NEG_IS_ZERO (1<<3)
434 #define IrSR_TXPL_POS_IS_ZERO 0x0
435 #define IrSR_XMODE_PULSE_1_6 (1<<2)
436 #define IrSR_XMODE_PULSE_3_16 0x0
437 #define IrSR_RCVEIR_IR_MODE (1<<1)
438 #define IrSR_RCVEIR_UART_MODE 0x0
439 #define IrSR_XMITIR_IR_MODE (1<<0)
440 #define IrSR_XMITIR_UART_MODE 0x0
442 #define IrSR_IR_RECEIVE_ON (\
443 IrSR_RXPL_NEG_IS_ZERO | \
444 IrSR_TXPL_POS_IS_ZERO | \
445 IrSR_XMODE_PULSE_3_16 | \
446 IrSR_RCVEIR_IR_MODE | \
447 IrSR_XMITIR_UART_MODE)
449 #define IrSR_IR_TRANSMIT_ON (\
450 IrSR_RXPL_NEG_IS_ZERO | \
451 IrSR_TXPL_POS_IS_ZERO | \
452 IrSR_XMODE_PULSE_3_16 | \
453 IrSR_RCVEIR_UART_MODE | \
459 #define IBMR __REG(0x40301680) /* I2C Bus Monitor Register - IBMR */
460 #define IDBR __REG(0x40301688) /* I2C Data Buffer Register - IDBR */
461 #define ICR __REG(0x40301690) /* I2C Control Register - ICR */
462 #define ISR __REG(0x40301698) /* I2C Status Register - ISR */
463 #define ISAR __REG(0x403016A0) /* I2C Slave Address Register - ISAR */
465 #define PWRIBMR __REG(0x40f00180) /* Power I2C Bus Monitor Register-IBMR */
466 #define PWRIDBR __REG(0x40f00188) /* Power I2C Data Buffer Register-IDBR */
467 #define PWRICR __REG(0x40f00190) /* Power I2C Control Register - ICR */
468 #define PWRISR __REG(0x40f00198) /* Power I2C Status Register - ISR */
469 #define PWRISAR __REG(0x40f001A0) /* Power I2C Slave Address Register-ISAR */
471 /* ----- Control register bits ---------------------------------------- */
473 #define ICR_START 0x1 /* start bit */
474 #define ICR_STOP 0x2 /* stop bit */
475 #define ICR_ACKNAK 0x4 /* send ACK(0) or NAK(1) */
476 #define ICR_TB 0x8 /* transfer byte bit */
477 #define ICR_MA 0x10 /* master abort */
478 #define ICR_SCLE 0x20 /* master clock enable, mona SCLEA */
479 #define ICR_IUE 0x40 /* unit enable */
480 #define ICR_GCD 0x80 /* general call disable */
481 #define ICR_ITEIE 0x100 /* enable tx interrupts */
482 #define ICR_IRFIE 0x200 /* enable rx interrupts, mona: DRFIE */
483 #define ICR_BEIE 0x400 /* enable bus error ints */
484 #define ICR_SSDIE 0x800 /* slave STOP detected int enable */
485 #define ICR_ALDIE 0x1000 /* enable arbitration interrupt */
486 #define ICR_SADIE 0x2000 /* slave address detected int enable */
487 #define ICR_UR 0x4000 /* unit reset */
488 #define ICR_FM 0x8000 /* Fast Mode */
490 /* ----- Status register bits ----------------------------------------- */
492 #define ISR_RWM 0x1 /* read/write mode */
493 #define ISR_ACKNAK 0x2 /* ack/nak status */
494 #define ISR_UB 0x4 /* unit busy */
495 #define ISR_IBB 0x8 /* bus busy */
496 #define ISR_SSD 0x10 /* slave stop detected */
497 #define ISR_ALD 0x20 /* arbitration loss detected */
498 #define ISR_ITE 0x40 /* tx buffer empty */
499 #define ISR_IRF 0x80 /* rx buffer full */
500 #define ISR_GCAD 0x100 /* general call address detected */
501 #define ISR_SAD 0x200 /* slave address detected */
502 #define ISR_BED 0x400 /* bus error no ACK/NAK */
505 * Serial Audio Controller
507 /* FIXME the audio defines collide w/ the SA1111 defines. I don't like these
508 * short defines because there is too much chance of namespace collision
510 /*#define SACR0 __REG(0x40400000) / Global Control Register */
511 /*#define SACR1 __REG(0x40400004) / Serial Audio I 2 S/MSB-Justified Control Register */
512 /*#define SASR0 __REG(0x4040000C) / Serial Audio I 2 S/MSB-Justified Interface and FIFO Status Register */
513 /*#define SAIMR __REG(0x40400014) / Serial Audio Interrupt Mask Register */
514 /*#define SAICR __REG(0x40400018) / Serial Audio Interrupt Clear Register */
515 /*#define SADIV __REG(0x40400060) / Audio Clock Divider Register. */
516 /*#define SADR __REG(0x40400080) / Serial Audio Data Register (TX and RX FIFO access Register). */
520 * AC97 Controller registers
522 #define POCR __REG(0x40500000) /* PCM Out Control Register */
523 #define POCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
525 #define PICR __REG(0x40500004) /* PCM In Control Register */
526 #define PICR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
528 #define MCCR __REG(0x40500008) /* Mic In Control Register */
529 #define MCCR_FEIE (1 << 3) /* FIFO Error Interrupt Enable */
531 #define GCR __REG(0x4050000C) /* Global Control Register */
532 #define GCR_CDONE_IE (1 << 19) /* Command Done Interrupt Enable */
533 #define GCR_SDONE_IE (1 << 18) /* Status Done Interrupt Enable */
534 #define GCR_SECRDY_IEN (1 << 9) /* Secondary Ready Interrupt Enable */
535 #define GCR_PRIRDY_IEN (1 << 8) /* Primary Ready Interrupt Enable */
536 #define GCR_SECRES_IEN (1 << 5) /* Secondary Resume Interrupt Enable */
537 #define GCR_PRIRES_IEN (1 << 4) /* Primary Resume Interrupt Enable */
538 #define GCR_ACLINK_OFF (1 << 3) /* AC-link Shut Off */
539 #define GCR_WARM_RST (1 << 2) /* AC97 Warm Reset */
540 #define GCR_COLD_RST (1 << 1) /* AC'97 Cold Reset (0 = active) */
541 #define GCR_GIE (1 << 0) /* Codec GPI Interrupt Enable */
543 #define POSR __REG(0x40500010) /* PCM Out Status Register */
544 #define POSR_FIFOE (1 << 4) /* FIFO error */
546 #define PISR __REG(0x40500014) /* PCM In Status Register */
547 #define PISR_FIFOE (1 << 4) /* FIFO error */
549 #define MCSR __REG(0x40500018) /* Mic In Status Register */
550 #define MCSR_FIFOE (1 << 4) /* FIFO error */
552 #define GSR __REG(0x4050001C) /* Global Status Register */
553 #define GSR_CDONE (1 << 19) /* Command Done */
554 #define GSR_SDONE (1 << 18) /* Status Done */
555 #define GSR_RDCS (1 << 15) /* Read Completion Status */
556 #define GSR_BIT3SLT12 (1 << 14) /* Bit 3 of slot 12 */
557 #define GSR_BIT2SLT12 (1 << 13) /* Bit 2 of slot 12 */
558 #define GSR_BIT1SLT12 (1 << 12) /* Bit 1 of slot 12 */
559 #define GSR_SECRES (1 << 11) /* Secondary Resume Interrupt */
560 #define GSR_PRIRES (1 << 10) /* Primary Resume Interrupt */
561 #define GSR_SCR (1 << 9) /* Secondary Codec Ready */
562 #define GSR_PCR (1 << 8) /* Primary Codec Ready */
563 #define GSR_MINT (1 << 7) /* Mic In Interrupt */
564 #define GSR_POINT (1 << 6) /* PCM Out Interrupt */
565 #define GSR_PIINT (1 << 5) /* PCM In Interrupt */
566 #define GSR_MOINT (1 << 2) /* Modem Out Interrupt */
567 #define GSR_MIINT (1 << 1) /* Modem In Interrupt */
568 #define GSR_GSCI (1 << 0) /* Codec GPI Status Change Interrupt */
570 #define CAR __REG(0x40500020) /* CODEC Access Register */
571 #define CAR_CAIP (1 << 0) /* Codec Access In Progress */
573 #define PCDR __REG(0x40500040) /* PCM FIFO Data Register */
574 #define MCDR __REG(0x40500060) /* Mic-in FIFO Data Register */
576 #define MOCR __REG(0x40500100) /* Modem Out Control Register */
577 #define MOCR_FEIE (1 << 3) /* FIFO Error */
579 #define MICR __REG(0x40500108) /* Modem In Control Register */
580 #define MICR_FEIE (1 << 3) /* FIFO Error */
582 #define MOSR __REG(0x40500110) /* Modem Out Status Register */
583 #define MOSR_FIFOE (1 << 4) /* FIFO error */
585 #define MISR __REG(0x40500118) /* Modem In Status Register */
586 #define MISR_FIFOE (1 << 4) /* FIFO error */
588 #define MODR __REG(0x40500140) /* Modem FIFO Data Register */
590 #define PAC_REG_BASE __REG(0x40500200) /* Primary Audio Codec */
591 #define SAC_REG_BASE __REG(0x40500300) /* Secondary Audio Codec */
592 #define PMC_REG_BASE __REG(0x40500400) /* Primary Modem Codec */
593 #define SMC_REG_BASE __REG(0x40500500) /* Secondary Modem Codec */
597 * USB Device Controller
601 #define UDCCR __REG(0x40600000) /* UDC Control Register */
602 #define UDCCR_UDE (1 << 0) /* UDC enable */
603 #define UDCCR_UDA (1 << 1) /* UDC active */
604 #define UDCCR_RSM (1 << 2) /* Device resume */
605 #define UDCCR_EMCE (1 << 3) /* Endpoint Memory Configuration Error */
606 #define UDCCR_SMAC (1 << 4) /* Switch Endpoint Memory to Active Configuration */
607 #define UDCCR_RESIR (1 << 29) /* Resume interrupt request */
608 #define UDCCR_SUSIR (1 << 28) /* Suspend interrupt request */
609 #define UDCCR_SM (1 << 28) /* Suspend interrupt mask */
610 #define UDCCR_RSTIR (1 << 27) /* Reset interrupt request */
611 #define UDCCR_REM (1 << 27) /* Reset interrupt mask */
612 #define UDCCR_RM (1 << 29) /* resume interrupt mask */
613 #define UDCCR_SRM (UDCCR_SM|UDCCR_RM)
614 #define UDCCR_OEN (1 << 31) /* On-the-Go Enable */
615 #define UDCCR_AALTHNP (1 << 30) /* A-device Alternate Host Negotiation Protocol Port Support */
616 #define UDCCR_AHNP (1 << 29) /* A-device Host Negotiation Protocol Support */
617 #define UDCCR_BHNP (1 << 28) /* B-device Host Negotiation Protocol Enable */
618 #define UDCCR_DWRE (1 << 16) /* Device Remote Wake-up Enable */
619 #define UDCCR_ACN (0x03 << 11) /* Active UDC configuration Number */
620 #define UDCCR_ACN_S 11
621 #define UDCCR_AIN (0x07 << 8) /* Active UDC interface Number */
622 #define UDCCR_AIN_S 8
623 #define UDCCR_AAISN (0x07 << 5) /* Active UDC Alternate Interface Setting Number */
624 #define UDCCR_AAISN_S 5
626 #define UDCCS0 __REG(0x40600100) /* UDC Endpoint 0 Control/Status Register */
627 #define UDCCS0_OPR (1 << 0) /* OUT packet ready */
628 #define UDCCS0_IPR (1 << 1) /* IN packet ready */
629 #define UDCCS0_FTF (1 << 2) /* Flush Tx FIFO */
630 #define UDCCS0_DRWF (1 << 16) /* Device remote wakeup feature */
631 #define UDCCS0_SST (1 << 4) /* Sent stall */
632 #define UDCCS0_FST (1 << 5) /* Force stall */
633 #define UDCCS0_RNE (1 << 6) /* Receive FIFO no empty */
634 #define UDCCS0_SA (1 << 7) /* Setup active */
636 /* Bulk IN - Endpoint 1,6,11 */
637 #define UDCCS1 __REG(0x40600104) /* UDC Endpoint 1 (IN) Control/Status Register */
638 #define UDCCS6 __REG(0x40600028) /* UDC Endpoint 6 (IN) Control/Status Register */
639 #define UDCCS11 __REG(0x4060003C) /* UDC Endpoint 11 (IN) Control/Status Register */
641 #define UDCCS_BI_TFS (1 << 0) /* Transmit FIFO service */
642 #define UDCCS_BI_TPC (1 << 1) /* Transmit packet complete */
643 #define UDCCS_BI_FTF (1 << 8) /* Flush Tx FIFO */
644 #define UDCCS_BI_TUR (1 << 3) /* Transmit FIFO underrun */
645 #define UDCCS_BI_SST (1 << 4) /* Sent stall */
646 #define UDCCS_BI_FST (1 << 5) /* Force stall */
647 #define UDCCS_BI_TSP (1 << 7) /* Transmit short packet */
649 /* Bulk OUT - Endpoint 2,7,12 */
650 #define UDCCS2 __REG(0x40600108) /* UDC Endpoint 2 (OUT) Control/Status Register */
651 #define UDCCS7 __REG(0x4060002C) /* UDC Endpoint 7 (OUT) Control/Status Register */
652 #define UDCCS12 __REG(0x40600040) /* UDC Endpoint 12 (OUT) Control/Status Register */
654 #define UDCCS_BO_RFS (1 << 0) /* Receive FIFO service */
655 #define UDCCS_BO_RPC (1 << 1) /* Receive packet complete */
656 #define UDCCS_BO_DME (1 << 3) /* DMA enable */
657 #define UDCCS_BO_SST (1 << 4) /* Sent stall */
658 #define UDCCS_BO_FST (1 << 5) /* Force stall */
659 #define UDCCS_BO_RNE (1 << 6) /* Receive FIFO not empty */
660 #define UDCCS_BO_RSP (1 << 7) /* Receive short packet */
662 /* Isochronous IN - Endpoint 3,8,13 */
663 #define UDCCS3 __REG(0x4060001C) /* UDC Endpoint 3 (IN) Control/Status Register */
664 #define UDCCS8 __REG(0x40600030) /* UDC Endpoint 8 (IN) Control/Status Register */
665 #define UDCCS13 __REG(0x40600044) /* UDC Endpoint 13 (IN) Control/Status Register */
667 #define UDCCS_II_TFS (1 << 0) /* Transmit FIFO service */
668 #define UDCCS_II_TPC (1 << 1) /* Transmit packet complete */
669 #define UDCCS_II_FTF (1 << 2) /* Flush Tx FIFO */
670 #define UDCCS_II_TUR (1 << 3) /* Transmit FIFO underrun */
671 #define UDCCS_II_TSP (1 << 7) /* Transmit short packet */
673 /* Isochronous OUT - Endpoint 4,9,14 */
674 #define UDCCS4 __REG(0x40600020) /* UDC Endpoint 4 (OUT) Control/Status Register */
675 #define UDCCS9 __REG(0x40600034) /* UDC Endpoint 9 (OUT) Control/Status Register */
676 #define UDCCS14 __REG(0x40600048) /* UDC Endpoint 14 (OUT) Control/Status Register */
678 #define UDCCS_IO_RFS (1 << 0) /* Receive FIFO service */
679 #define UDCCS_IO_RPC (1 << 1) /* Receive packet complete */
680 #define UDCCS_IO_ROF (1 << 3) /* Receive overflow */
681 #define UDCCS_IO_DME (1 << 3) /* DMA enable */
682 #define UDCCS_IO_RNE (1 << 6) /* Receive FIFO not empty */
683 #define UDCCS_IO_RSP (1 << 7) /* Receive short packet */
685 /* Interrupt IN - Endpoint 5,10,15 */
686 #define UDCCS5 __REG(0x40600024) /* UDC Endpoint 5 (Interrupt) Control/Status Register */
687 #define UDCCS10 __REG(0x40600038) /* UDC Endpoint 10 (Interrupt) Control/Status Register */
688 #define UDCCS15 __REG(0x4060004C) /* UDC Endpoint 15 (Interrupt) Control/Status Register */
690 #define UDCCS_INT_TFS (1 << 0) /* Transmit FIFO service */
691 #define UDCCS_INT_TPC (1 << 1) /* Transmit packet complete */
692 #define UDCCS_INT_FTF (1 << 2) /* Flush Tx FIFO */
693 #define UDCCS_INT_TUR (1 << 3) /* Transmit FIFO underrun */
694 #define UDCCS_INT_SST (1 << 4) /* Sent stall */
695 #define UDCCS_INT_FST (1 << 5) /* Force stall */
696 #define UDCCS_INT_TSP (1 << 7) /* Transmit short packet */
698 #define UFNRH __REG(0x40600060) /* UDC Frame Number Register High */
699 #define UFNRL __REG(0x40600014) /* UDC Frame Number Register Low */
700 #define UBCR2 __REG(0x40600208) /* UDC Byte Count Reg 2 */
701 #define UBCR4 __REG(0x4060006c) /* UDC Byte Count Reg 4 */
702 #define UBCR7 __REG(0x40600070) /* UDC Byte Count Reg 7 */
703 #define UBCR9 __REG(0x40600074) /* UDC Byte Count Reg 9 */
704 #define UBCR12 __REG(0x40600078) /* UDC Byte Count Reg 12 */
705 #define UBCR14 __REG(0x4060007c) /* UDC Byte Count Reg 14 */
706 #define UDDR0 __REG(0x40600300) /* UDC Endpoint 0 Data Register */
707 #define UDDR1 __REG(0x40600304) /* UDC Endpoint 1 Data Register */
708 #define UDDR2 __REG(0x40600308) /* UDC Endpoint 2 Data Register */
709 #define UDDR3 __REG(0x40600200) /* UDC Endpoint 3 Data Register */
710 #define UDDR4 __REG(0x40600400) /* UDC Endpoint 4 Data Register */
711 #define UDDR5 __REG(0x406000A0) /* UDC Endpoint 5 Data Register */
712 #define UDDR6 __REG(0x40600600) /* UDC Endpoint 6 Data Register */
713 #define UDDR7 __REG(0x40600680) /* UDC Endpoint 7 Data Register */
714 #define UDDR8 __REG(0x40600700) /* UDC Endpoint 8 Data Register */
715 #define UDDR9 __REG(0x40600900) /* UDC Endpoint 9 Data Register */
716 #define UDDR10 __REG(0x406000C0) /* UDC Endpoint 10 Data Register */
717 #define UDDR11 __REG(0x40600B00) /* UDC Endpoint 11 Data Register */
718 #define UDDR12 __REG(0x40600B80) /* UDC Endpoint 12 Data Register */
719 #define UDDR13 __REG(0x40600C00) /* UDC Endpoint 13 Data Register */
720 #define UDDR14 __REG(0x40600E00) /* UDC Endpoint 14 Data Register */
721 #define UDDR15 __REG(0x406000E0) /* UDC Endpoint 15 Data Register */
723 #define UICR0 __REG(0x40600004) /* UDC Interrupt Control Register 0 */
725 #define UICR0_IM0 (1 << 0) /* Interrupt mask ep 0 */
726 #define UICR0_IM1 (1 << 1) /* Interrupt mask ep 1 */
727 #define UICR0_IM2 (1 << 2) /* Interrupt mask ep 2 */
728 #define UICR0_IM3 (1 << 3) /* Interrupt mask ep 3 */
729 #define UICR0_IM4 (1 << 4) /* Interrupt mask ep 4 */
730 #define UICR0_IM5 (1 << 5) /* Interrupt mask ep 5 */
731 #define UICR0_IM6 (1 << 6) /* Interrupt mask ep 6 */
732 #define UICR0_IM7 (1 << 7) /* Interrupt mask ep 7 */
734 #define UICR1 __REG(0x40600008) /* UDC Interrupt Control Register 1 */
736 #define UICR1_IM8 (1 << 0) /* Interrupt mask ep 8 */
737 #define UICR1_IM9 (1 << 1) /* Interrupt mask ep 9 */
738 #define UICR1_IM10 (1 << 2) /* Interrupt mask ep 10 */
739 #define UICR1_IM11 (1 << 3) /* Interrupt mask ep 11 */
740 #define UICR1_IM12 (1 << 4) /* Interrupt mask ep 12 */
741 #define UICR1_IM13 (1 << 5) /* Interrupt mask ep 13 */
742 #define UICR1_IM14 (1 << 6) /* Interrupt mask ep 14 */
743 #define UICR1_IM15 (1 << 7) /* Interrupt mask ep 15 */
745 #define USIR0 __REG(0x4060000C) /* UDC Status Interrupt Register 0 */
747 #define USIR0_IR0 (1 << 0) /* Interrup request ep 0 */
748 #define USIR0_IR1 (1 << 2) /* Interrup request ep 1 */
749 #define USIR0_IR2 (1 << 4) /* Interrup request ep 2 */
750 #define USIR0_IR3 (1 << 3) /* Interrup request ep 3 */
751 #define USIR0_IR4 (1 << 4) /* Interrup request ep 4 */
752 #define USIR0_IR5 (1 << 5) /* Interrup request ep 5 */
753 #define USIR0_IR6 (1 << 6) /* Interrup request ep 6 */
754 #define USIR0_IR7 (1 << 7) /* Interrup request ep 7 */
756 #define USIR1 __REG(0x40600010) /* UDC Status Interrupt Register 1 */
758 #define USIR1_IR8 (1 << 0) /* Interrup request ep 8 */
759 #define USIR1_IR9 (1 << 1) /* Interrup request ep 9 */
760 #define USIR1_IR10 (1 << 2) /* Interrup request ep 10 */
761 #define USIR1_IR11 (1 << 3) /* Interrup request ep 11 */
762 #define USIR1_IR12 (1 << 4) /* Interrup request ep 12 */
763 #define USIR1_IR13 (1 << 5) /* Interrup request ep 13 */
764 #define USIR1_IR14 (1 << 6) /* Interrup request ep 14 */
765 #define USIR1_IR15 (1 << 7) /* Interrup request ep 15 */
768 #define UDCICR0 __REG(0x40600004) /* UDC Interrupt Control Register0 */
769 #define UDCICR1 __REG(0x40600008) /* UDC Interrupt Control Register1 */
770 #define UDCICR_FIFOERR (1 << 1) /* FIFO Error interrupt for EP */
771 #define UDCICR_PKTCOMPL (1 << 0) /* Packet Complete interrupt for EP */
773 #define UDCICR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
774 #define UDCICR1_IECC (1 << 31) /* IntEn - Configuration Change */
775 #define UDCICR1_IESOF (1 << 30) /* IntEn - Start of Frame */
776 #define UDCICR1_IERU (1 << 29) /* IntEn - Resume */
777 #define UDCICR1_IESU (1 << 28) /* IntEn - Suspend */
778 #define UDCICR1_IERS (1 << 27) /* IntEn - Reset */
780 #define UDCISR0 __REG(0x4060000C) /* UDC Interrupt Status Register 0 */
781 #define UDCISR1 __REG(0x40600010) /* UDC Interrupt Status Register 1 */
782 #define UDCISR_INT(n, intr) (((intr) & 0x03) << (((n) & 0x0F) * 2))
783 #define UDCISR1_IRCC (1 << 31) /* IntEn - Configuration Change */
784 #define UDCISR1_IRSOF (1 << 30) /* IntEn - Start of Frame */
785 #define UDCISR1_IRRU (1 << 29) /* IntEn - Resume */
786 #define UDCISR1_IRSU (1 << 28) /* IntEn - Suspend */
787 #define UDCISR1_IRRS (1 << 27) /* IntEn - Reset */
790 #define UDCFNR __REG(0x40600014) /* UDC Frame Number Register */
791 #define UDCOTGICR __REG(0x40600018) /* UDC On-The-Go interrupt control */
792 #define UDCOTGICR_IESF (1 << 24) /* OTG SET_FEATURE command recvd */
793 #define UDCOTGICR_IEXR (1 << 17) /* Extra Transciever Interrupt Rising Edge Interrupt Enable */
794 #define UDCOTGICR_IEXF (1 << 16) /* Extra Transciever Interrupt Falling Edge Interrupt Enable */
795 #define UDCOTGICR_IEVV40R (1 << 9) /* OTG Vbus Valid 4.0V Rising Edge Interrupt Enable */
796 #define UDCOTGICR_IEVV40F (1 << 8) /* OTG Vbus Valid 4.0V Falling Edge Interrupt Enable */
797 #define UDCOTGICR_IEVV44R (1 << 7) /* OTG Vbus Valid 4.4V Rising Edge Interrupt Enable */
798 #define UDCOTGICR_IEVV44F (1 << 6) /* OTG Vbus Valid 4.4V Falling Edge Interrupt Enable */
799 #define UDCOTGICR_IESVR (1 << 5) /* OTG Session Valid Rising Edge Interrupt Enable */
800 #define UDCOTGICR_IESVF (1 << 4) /* OTG Session Valid Falling Edge Interrupt Enable */
801 #define UDCOTGICR_IESDR (1 << 3) /* OTG A-Device SRP Detect Rising Edge Interrupt Enable */
802 #define UDCOTGICR_IESDF (1 << 2) /* OTG A-Device SRP Detect Falling Edge Interrupt Enable */
803 #define UDCOTGICR_IEIDR (1 << 1) /* OTG ID Change Rising Edge Interrupt Enable */
804 #define UDCOTGICR_IEIDF (1 << 0) /* OTG ID Change Falling Edge Interrupt Enable */
806 #define UDCCSN(x) __REG2(0x40600100, (x) << 2)
807 #define UDCCSR0 __REG(0x40600100) /* UDC Control/Status register - Endpoint 0 */
809 #define UDCCSR0_SA (1 << 7) /* Setup Active */
810 #define UDCCSR0_RNE (1 << 6) /* Receive FIFO Not Empty */
811 #define UDCCSR0_FST (1 << 5) /* Force Stall */
812 #define UDCCSR0_SST (1 << 4) /* Sent Stall */
813 #define UDCCSR0_DME (1 << 3) /* DMA Enable */
814 #define UDCCSR0_FTF (1 << 2) /* Flush Transmit FIFO */
815 #define UDCCSR0_IPR (1 << 1) /* IN Packet Ready */
816 #define UDCCSR0_OPC (1 << 0) /* OUT Packet Complete */
818 #define UDCCSRA __REG(0x40600104) /* UDC Control/Status register - Endpoint A */
819 #define UDCCSRB __REG(0x40600108) /* UDC Control/Status register - Endpoint B */
820 #define UDCCSRC __REG(0x4060010C) /* UDC Control/Status register - Endpoint C */
821 #define UDCCSRD __REG(0x40600110) /* UDC Control/Status register - Endpoint D */
822 #define UDCCSRE __REG(0x40600114) /* UDC Control/Status register - Endpoint E */
823 #define UDCCSRF __REG(0x40600118) /* UDC Control/Status register - Endpoint F */
824 #define UDCCSRG __REG(0x4060011C) /* UDC Control/Status register - Endpoint G */
825 #define UDCCSRH __REG(0x40600120) /* UDC Control/Status register - Endpoint H */
826 #define UDCCSRI __REG(0x40600124) /* UDC Control/Status register - Endpoint I */
827 #define UDCCSRJ __REG(0x40600128) /* UDC Control/Status register - Endpoint J */
828 #define UDCCSRK __REG(0x4060012C) /* UDC Control/Status register - Endpoint K */
829 #define UDCCSRL __REG(0x40600130) /* UDC Control/Status register - Endpoint L */
830 #define UDCCSRM __REG(0x40600134) /* UDC Control/Status register - Endpoint M */
831 #define UDCCSRN __REG(0x40600138) /* UDC Control/Status register - Endpoint N */
832 #define UDCCSRP __REG(0x4060013C) /* UDC Control/Status register - Endpoint P */
833 #define UDCCSRQ __REG(0x40600140) /* UDC Control/Status register - Endpoint Q */
834 #define UDCCSRR __REG(0x40600144) /* UDC Control/Status register - Endpoint R */
835 #define UDCCSRS __REG(0x40600148) /* UDC Control/Status register - Endpoint S */
836 #define UDCCSRT __REG(0x4060014C) /* UDC Control/Status register - Endpoint T */
837 #define UDCCSRU __REG(0x40600150) /* UDC Control/Status register - Endpoint U */
838 #define UDCCSRV __REG(0x40600154) /* UDC Control/Status register - Endpoint V */
839 #define UDCCSRW __REG(0x40600158) /* UDC Control/Status register - Endpoint W */
840 #define UDCCSRX __REG(0x4060015C) /* UDC Control/Status register - Endpoint X */
842 #define UDCCSR_DPE (1 << 9) /* Data Packet Error */
843 #define UDCCSR_FEF (1 << 8) /* Flush Endpoint FIFO */
844 #define UDCCSR_SP (1 << 7) /* Short Packet Control/Status */
845 #define UDCCSR_BNE (1 << 6) /* Buffer Not Empty (IN endpoints) */
846 #define UDCCSR_BNF (1 << 6) /* Buffer Not Full (OUT endpoints) */
847 #define UDCCSR_FST (1 << 5) /* Force STALL */
848 #define UDCCSR_SST (1 << 4) /* Sent STALL */
849 #define UDCCSR_DME (1 << 3) /* DMA Enable */
850 #define UDCCSR_TRN (1 << 2) /* Tx/Rx NAK */
851 #define UDCCSR_PC (1 << 1) /* Packet Complete */
852 #define UDCCSR_FS (1 << 0) /* FIFO needs service */
854 #define UDCBCN(x) __REG2(0x40600200, (x)<<2)
855 #define UDCBCR0 __REG(0x40600200) /* Byte Count Register - EP0 */
856 #define UDCBCRA __REG(0x40600204) /* Byte Count Register - EPA */
857 #define UDCBCRB __REG(0x40600208) /* Byte Count Register - EPB */
858 #define UDCBCRC __REG(0x4060020C) /* Byte Count Register - EPC */
859 #define UDCBCRD __REG(0x40600210) /* Byte Count Register - EPD */
860 #define UDCBCRE __REG(0x40600214) /* Byte Count Register - EPE */
861 #define UDCBCRF __REG(0x40600218) /* Byte Count Register - EPF */
862 #define UDCBCRG __REG(0x4060021C) /* Byte Count Register - EPG */
863 #define UDCBCRH __REG(0x40600220) /* Byte Count Register - EPH */
864 #define UDCBCRI __REG(0x40600224) /* Byte Count Register - EPI */
865 #define UDCBCRJ __REG(0x40600228) /* Byte Count Register - EPJ */
866 #define UDCBCRK __REG(0x4060022C) /* Byte Count Register - EPK */
867 #define UDCBCRL __REG(0x40600230) /* Byte Count Register - EPL */
868 #define UDCBCRM __REG(0x40600234) /* Byte Count Register - EPM */
869 #define UDCBCRN __REG(0x40600238) /* Byte Count Register - EPN */
870 #define UDCBCRP __REG(0x4060023C) /* Byte Count Register - EPP */
871 #define UDCBCRQ __REG(0x40600240) /* Byte Count Register - EPQ */
872 #define UDCBCRR __REG(0x40600244) /* Byte Count Register - EPR */
873 #define UDCBCRS __REG(0x40600248) /* Byte Count Register - EPS */
874 #define UDCBCRT __REG(0x4060024C) /* Byte Count Register - EPT */
875 #define UDCBCRU __REG(0x40600250) /* Byte Count Register - EPU */
876 #define UDCBCRV __REG(0x40600254) /* Byte Count Register - EPV */
877 #define UDCBCRW __REG(0x40600258) /* Byte Count Register - EPW */
878 #define UDCBCRX __REG(0x4060025C) /* Byte Count Register - EPX */
880 #define UDCDN(x) __REG2(0x40600300, (x)<<2)
881 #define UDCDR0 __REG(0x40600300) /* Data Register - EP0 */
882 #define UDCDRA __REG(0x40600304) /* Data Register - EPA */
883 #define UDCDRB __REG(0x40600308) /* Data Register - EPB */
884 #define UDCDRC __REG(0x4060030C) /* Data Register - EPC */
885 #define UDCDRD __REG(0x40600310) /* Data Register - EPD */
886 #define UDCDRE __REG(0x40600314) /* Data Register - EPE */
887 #define UDCDRF __REG(0x40600318) /* Data Register - EPF */
888 #define UDCDRG __REG(0x4060031C) /* Data Register - EPG */
889 #define UDCDRH __REG(0x40600320) /* Data Register - EPH */
890 #define UDCDRI __REG(0x40600324) /* Data Register - EPI */
891 #define UDCDRJ __REG(0x40600328) /* Data Register - EPJ */
892 #define UDCDRK __REG(0x4060032C) /* Data Register - EPK */
893 #define UDCDRL __REG(0x40600330) /* Data Register - EPL */
894 #define UDCDRM __REG(0x40600334) /* Data Register - EPM */
895 #define UDCDRN __REG(0x40600338) /* Data Register - EPN */
896 #define UDCDRP __REG(0x4060033C) /* Data Register - EPP */
897 #define UDCDRQ __REG(0x40600340) /* Data Register - EPQ */
898 #define UDCDRR __REG(0x40600344) /* Data Register - EPR */
899 #define UDCDRS __REG(0x40600348) /* Data Register - EPS */
900 #define UDCDRT __REG(0x4060034C) /* Data Register - EPT */
901 #define UDCDRU __REG(0x40600350) /* Data Register - EPU */
902 #define UDCDRV __REG(0x40600354) /* Data Register - EPV */
903 #define UDCDRW __REG(0x40600358) /* Data Register - EPW */
904 #define UDCDRX __REG(0x4060035C) /* Data Register - EPX */
906 #define UDCCN(x) __REG2(0x40600400, (x)<<2)
907 #define UDCCRA __REG(0x40600404) /* Configuration register EPA */
908 #define UDCCRB __REG(0x40600408) /* Configuration register EPB */
909 #define UDCCRC __REG(0x4060040C) /* Configuration register EPC */
910 #define UDCCRD __REG(0x40600410) /* Configuration register EPD */
911 #define UDCCRE __REG(0x40600414) /* Configuration register EPE */
912 #define UDCCRF __REG(0x40600418) /* Configuration register EPF */
913 #define UDCCRG __REG(0x4060041C) /* Configuration register EPG */
914 #define UDCCRH __REG(0x40600420) /* Configuration register EPH */
915 #define UDCCRI __REG(0x40600424) /* Configuration register EPI */
916 #define UDCCRJ __REG(0x40600428) /* Configuration register EPJ */
917 #define UDCCRK __REG(0x4060042C) /* Configuration register EPK */
918 #define UDCCRL __REG(0x40600430) /* Configuration register EPL */
919 #define UDCCRM __REG(0x40600434) /* Configuration register EPM */
920 #define UDCCRN __REG(0x40600438) /* Configuration register EPN */
921 #define UDCCRP __REG(0x4060043C) /* Configuration register EPP */
922 #define UDCCRQ __REG(0x40600440) /* Configuration register EPQ */
923 #define UDCCRR __REG(0x40600444) /* Configuration register EPR */
924 #define UDCCRS __REG(0x40600448) /* Configuration register EPS */
925 #define UDCCRT __REG(0x4060044C) /* Configuration register EPT */
926 #define UDCCRU __REG(0x40600450) /* Configuration register EPU */
927 #define UDCCRV __REG(0x40600454) /* Configuration register EPV */
928 #define UDCCRW __REG(0x40600458) /* Configuration register EPW */
929 #define UDCCRX __REG(0x4060045C) /* Configuration register EPX */
931 #define UDCCONR_CN (0x03 << 25) /* Configuration Number */
932 #define UDCCONR_CN_S (25)
933 #define UDCCONR_IN (0x07 << 22) /* Interface Number */
934 #define UDCCONR_IN_S (22)
935 #define UDCCONR_AISN (0x07 << 19) /* Alternate Interface Number */
936 #define UDCCONR_AISN_S (19)
937 #define UDCCONR_EN (0x0f << 15) /* Endpoint Number */
938 #define UDCCONR_EN_S (15)
939 #define UDCCONR_ET (0x03 << 13) /* Endpoint Type: */
940 #define UDCCONR_ET_S (13)
941 #define UDCCONR_ET_INT (0x03 << 13) /* Interrupt */
942 #define UDCCONR_ET_BULK (0x02 << 13) /* Bulk */
943 #define UDCCONR_ET_ISO (0x01 << 13) /* Isochronous */
944 #define UDCCONR_ET_NU (0x00 << 13) /* Not used */
945 #define UDCCONR_ED (1 << 12) /* Endpoint Direction */
946 #define UDCCONR_MPS (0x3ff << 2) /* Maximum Packet Size */
947 #define UDCCONR_MPS_S (2)
948 #define UDCCONR_DE (1 << 1) /* Double Buffering Enable */
949 #define UDCCONR_EE (1 << 0) /* Endpoint Enable */
952 #define UDC_INT_FIFOERROR (0x2)
953 #define UDC_INT_PACKETCMP (0x1)
954 #define UDC_FNR_MASK (0x7ff)
955 #define UDCCSR_WR_MASK (UDCCSR_DME|UDCCSR_FST)
956 #define UDC_BCR_MASK (0x3ff)
958 #endif /* CONFIG_PXA27X */
960 #if defined(CONFIG_PXA27X) || defined(CONFIG_CPU_MONAHANS)
963 * USB Host Controller
965 #define OHCI_REGS_BASE 0x4C000000 /* required for ohci driver */
966 #define UHCREV __REG(0x4C000000)
967 #define UHCHCON __REG(0x4C000004)
968 #define UHCCOMS __REG(0x4C000008)
969 #define UHCINTS __REG(0x4C00000C)
970 #define UHCINTE __REG(0x4C000010)
971 #define UHCINTD __REG(0x4C000014)
972 #define UHCHCCA __REG(0x4C000018)
973 #define UHCPCED __REG(0x4C00001C)
974 #define UHCCHED __REG(0x4C000020)
975 #define UHCCCED __REG(0x4C000024)
976 #define UHCBHED __REG(0x4C000028)
977 #define UHCBCED __REG(0x4C00002C)
978 #define UHCDHEAD __REG(0x4C000030)
979 #define UHCFMI __REG(0x4C000034)
980 #define UHCFMR __REG(0x4C000038)
981 #define UHCFMN __REG(0x4C00003C)
982 #define UHCPERS __REG(0x4C000040)
983 #define UHCLST __REG(0x4C000044)
984 #define UHCRHDA __REG(0x4C000048)
985 #define UHCRHDB __REG(0x4C00004C)
986 #define UHCRHS __REG(0x4C000050)
987 #define UHCRHPS1 __REG(0x4C000054)
988 #define UHCRHPS2 __REG(0x4C000058)
989 #define UHCRHPS3 __REG(0x4C00005C)
990 #define UHCSTAT __REG(0x4C000060)
991 #define UHCHR __REG(0x4C000064)
992 #define UHCHIE __REG(0x4C000068)
993 #define UHCHIT __REG(0x4C00006C)
995 #if defined(CONFIG_CPU_MONAHANS)
996 #define UP2OCR __REG(0x40600020)
999 #define UHCHR_FSBIR (1<<0)
1000 #define UHCHR_FHR (1<<1)
1001 #define UHCHR_CGR (1<<2)
1002 #define UHCHR_SSDC (1<<3)
1003 #define UHCHR_UIT (1<<4)
1004 #define UHCHR_SSE (1<<5)
1005 #define UHCHR_PSPL (1<<6)
1006 #define UHCHR_PCPL (1<<7)
1007 #define UHCHR_SSEP0 (1<<9)
1008 #define UHCHR_SSEP1 (1<<10)
1009 #define UHCHR_SSEP2 (1<<11)
1011 #define UHCHIE_UPRIE (1<<13)
1012 #define UHCHIE_UPS2IE (1<<12)
1013 #define UHCHIE_UPS1IE (1<<11)
1014 #define UHCHIE_TAIE (1<<10)
1015 #define UHCHIE_HBAIE (1<<8)
1016 #define UHCHIE_RWIE (1<<7)
1021 * Fast Infrared Communication Port
1023 #define ICCR0 __REG(0x40800000) /* ICP Control Register 0 */
1024 #define ICCR1 __REG(0x40800004) /* ICP Control Register 1 */
1025 #define ICCR2 __REG(0x40800008) /* ICP Control Register 2 */
1026 #define ICDR __REG(0x4080000c) /* ICP Data Register */
1027 #define ICSR0 __REG(0x40800014) /* ICP Status Register 0 */
1028 #define ICSR1 __REG(0x40800018) /* ICP Status Register 1 */
1033 #define RCNR __REG(0x40900000) /* RTC Count Register */
1034 #define RTAR __REG(0x40900004) /* RTC Alarm Register */
1035 #define RTSR __REG(0x40900008) /* RTC Status Register */
1036 #define RTTR __REG(0x4090000C) /* RTC Timer Trim Register */
1037 #define RDAR1 __REG(0x40900018) /* Wristwatch Day Alarm Reg 1 */
1038 #define RDAR2 __REG(0x40900020) /* Wristwatch Day Alarm Reg 2 */
1039 #define RYAR1 __REG(0x4090001C) /* Wristwatch Year Alarm Reg 1 */
1040 #define RYAR2 __REG(0x40900024) /* Wristwatch Year Alarm Reg 2 */
1041 #define SWAR1 __REG(0x4090002C) /* Stopwatch Alarm Register 1 */
1042 #define SWAR2 __REG(0x40900030) /* Stopwatch Alarm Register 2 */
1043 #define PIAR __REG(0x40900038) /* Periodic Interrupt Alarm Register */
1044 #define RDCR __REG(0x40900010) /* RTC Day Count Register. */
1045 #define RYCR __REG(0x40900014) /* RTC Year Count Register. */
1046 #define SWCR __REG(0x40900028) /* Stopwatch Count Register */
1047 #define RTCPICR __REG(0x40900034) /* Periodic Interrupt Counter Register */
1049 #define RTSR_PICE (1 << 15) /* Peridoc interrupt count enable */
1050 #define RTSR_PIALE (1 << 14) /* Peridoc interrupt Alarm enable */
1051 #define RTSR_PIAL (1 << 13) /* Peridoc interrupt Alarm status */
1052 #define RTSR_HZE (1 << 3) /* HZ interrupt enable */
1053 #define RTSR_ALE (1 << 2) /* RTC alarm interrupt enable */
1054 #define RTSR_HZ (1 << 1) /* HZ rising-edge detected */
1055 #define RTSR_AL (1 << 0) /* RTC alarm detected */
1058 * OS Timer & Match Registers
1060 #define OSMR0 __REG(0x40A00000) /* OS Timer Match Register 0 */
1061 #define OSMR1 __REG(0x40A00004) /* OS Timer Match Register 1 */
1062 #define OSMR2 __REG(0x40A00008) /* OS Timer Match Register 2 */
1063 #define OSMR3 __REG(0x40A0000C) /* OS Timer Match Register 3 */
1064 #define OSCR __REG(0x40A00010) /* OS Timer Counter Register */
1065 #define OSSR __REG(0x40A00014) /* OS Timer Status Register */
1066 #define OWER __REG(0x40A00018) /* OS Timer Watchdog Enable Register */
1067 #define OIER __REG(0x40A0001C) /* OS Timer Interrupt Enable Register */
1069 #ifdef CONFIG_CPU_MONAHANS
1070 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register 4 */
1071 #define OSCR5 __REG(0x40A00044) /* OS Timer Counter Register 5 */
1072 #define OSCR6 __REG(0x40A00048) /* OS Timer Counter Register 6 */
1073 #define OSCR7 __REG(0x40A0004C) /* OS Timer Counter Register 7 */
1074 #define OSCR8 __REG(0x40A00050) /* OS Timer Counter Register 8 */
1075 #define OSCR9 __REG(0x40A00054) /* OS Timer Counter Register 9 */
1076 #define OSCR10 __REG(0x40A00058) /* OS Timer Counter Register 10 */
1077 #define OSCR11 __REG(0x40A0005C) /* OS Timer Counter Register 11 */
1079 #define OSMR4 __REG(0x40A00080) /* OS Timer Match Register 4 */
1080 #define OSMR5 __REG(0x40A00084) /* OS Timer Match Register 5 */
1081 #define OSMR6 __REG(0x40A00088) /* OS Timer Match Register 6 */
1082 #define OSMR7 __REG(0x40A0008C) /* OS Timer Match Register 7 */
1083 #define OSMR8 __REG(0x40A00090) /* OS Timer Match Register 8 */
1084 #define OSMR9 __REG(0x40A00094) /* OS Timer Match Register 9 */
1085 #define OSMR10 __REG(0x40A00098) /* OS Timer Match Register 10 */
1086 #define OSMR11 __REG(0x40A0009C) /* OS Timer Match Register 11 */
1088 #define OMCR4 __REG(0x40A000C0) /* OS Match Control Register 4 */
1089 #define OMCR5 __REG(0x40A000C4) /* OS Match Control Register 5 */
1090 #define OMCR6 __REG(0x40A000C8) /* OS Match Control Register 6 */
1091 #define OMCR7 __REG(0x40A000CC) /* OS Match Control Register 7 */
1092 #define OMCR8 __REG(0x40A000D0) /* OS Match Control Register 8 */
1093 #define OMCR9 __REG(0x40A000D4) /* OS Match Control Register 9 */
1094 #define OMCR10 __REG(0x40A000D8) /* OS Match Control Register 10 */
1095 #define OMCR11 __REG(0x40A000DC) /* OS Match Control Register 11 */
1097 #define OSCR_CLK_FREQ 3250 /* kHz = 3.25 MHz */
1098 #endif /* CONFIG_CPU_MONAHANS */
1100 #define OSSR_M4 (1 << 4) /* Match status channel 4 */
1101 #define OSSR_M3 (1 << 3) /* Match status channel 3 */
1102 #define OSSR_M2 (1 << 2) /* Match status channel 2 */
1103 #define OSSR_M1 (1 << 1) /* Match status channel 1 */
1104 #define OSSR_M0 (1 << 0) /* Match status channel 0 */
1106 #define OWER_WME (1 << 0) /* Watchdog Match Enable */
1108 #define OIER_E4 (1 << 4) /* Interrupt enable channel 4 */
1109 #define OIER_E3 (1 << 3) /* Interrupt enable channel 3 */
1110 #define OIER_E2 (1 << 2) /* Interrupt enable channel 2 */
1111 #define OIER_E1 (1 << 1) /* Interrupt enable channel 1 */
1112 #define OIER_E0 (1 << 0) /* Interrupt enable channel 0 */
1115 * Pulse Width Modulator
1117 #define PWM_CTRL0 __REG(0x40B00000) /* PWM 0 Control Register */
1118 #define PWM_PWDUTY0 __REG(0x40B00004) /* PWM 0 Duty Cycle Register */
1119 #define PWM_PERVAL0 __REG(0x40B00008) /* PWM 0 Period Control Register */
1121 #define PWM_CTRL1 __REG(0x40C00000) /* PWM 1Control Register */
1122 #define PWM_PWDUTY1 __REG(0x40C00004) /* PWM 1 Duty Cycle Register */
1123 #define PWM_PERVAL1 __REG(0x40C00008) /* PWM 1 Period Control Register */
1126 * Interrupt Controller
1128 #define ICIP __REG(0x40D00000) /* Interrupt Controller IRQ Pending Register */
1129 #define ICMR __REG(0x40D00004) /* Interrupt Controller Mask Register */
1130 #define ICLR __REG(0x40D00008) /* Interrupt Controller Level Register */
1131 #define ICFP __REG(0x40D0000C) /* Interrupt Controller FIQ Pending Register */
1132 #define ICPR __REG(0x40D00010) /* Interrupt Controller Pending Register */
1133 #define ICCR __REG(0x40D00014) /* Interrupt Controller Control Register */
1135 #ifdef CONFIG_CPU_MONAHANS
1136 #define ICHP __REG(0x40D00018) /* Interrupt Controller Highest Priority Register */
1137 /* Missing: 32 Interrupt priority registers
1138 * These are the same as beneath for PXA27x: maybe can be merged if
1139 * GPIO Stuff is same too.
1141 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1142 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1143 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1144 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1145 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1146 /* Missing: 2 Interrupt priority registers */
1147 #endif /* CONFIG_CPU_MONAHANS */
1150 * General Purpose I/O
1152 #define GPLR0 __REG(0x40E00000) /* GPIO Pin-Level Register GPIO<31:0> */
1153 #define GPLR1 __REG(0x40E00004) /* GPIO Pin-Level Register GPIO<63:32> */
1154 #define GPLR2 __REG(0x40E00008) /* GPIO Pin-Level Register GPIO<80:64> */
1156 #define GPDR0 __REG(0x40E0000C) /* GPIO Pin Direction Register GPIO<31:0> */
1157 #define GPDR1 __REG(0x40E00010) /* GPIO Pin Direction Register GPIO<63:32> */
1158 #define GPDR2 __REG(0x40E00014) /* GPIO Pin Direction Register GPIO<80:64> */
1160 #define GPSR0 __REG(0x40E00018) /* GPIO Pin Output Set Register GPIO<31:0> */
1161 #define GPSR1 __REG(0x40E0001C) /* GPIO Pin Output Set Register GPIO<63:32> */
1162 #define GPSR2 __REG(0x40E00020) /* GPIO Pin Output Set Register GPIO<80:64> */
1164 #define GPCR0 __REG(0x40E00024) /* GPIO Pin Output Clear Register GPIO<31:0> */
1165 #define GPCR1 __REG(0x40E00028) /* GPIO Pin Output Clear Register GPIO <63:32> */
1166 #define GPCR2 __REG(0x40E0002C) /* GPIO Pin Output Clear Register GPIO <80:64> */
1168 #define GRER0 __REG(0x40E00030) /* GPIO Rising-Edge Detect Register GPIO<31:0> */
1169 #define GRER1 __REG(0x40E00034) /* GPIO Rising-Edge Detect Register GPIO<63:32> */
1170 #define GRER2 __REG(0x40E00038) /* GPIO Rising-Edge Detect Register GPIO<80:64> */
1172 #define GFER0 __REG(0x40E0003C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
1173 #define GFER1 __REG(0x40E00040) /* GPIO Falling-Edge Detect Register GPIO<63:32> */
1174 #define GFER2 __REG(0x40E00044) /* GPIO Falling-Edge Detect Register GPIO<80:64> */
1176 #define GEDR0 __REG(0x40E00048) /* GPIO Edge Detect Status Register GPIO<31:0> */
1177 #define GEDR1 __REG(0x40E0004C) /* GPIO Edge Detect Status Register GPIO<63:32> */
1178 #define GEDR2 __REG(0x40E00050) /* GPIO Edge Detect Status Register GPIO<80:64> */
1180 #ifdef CONFIG_CPU_MONAHANS
1181 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
1182 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
1183 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
1184 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO<127:96> */
1185 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
1186 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<127:96> */
1187 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
1189 #define GSDR0 __REG(0x40E00400) /* Bit-wise Set of GPDR[31:0] */
1190 #define GSDR1 __REG(0x40E00404) /* Bit-wise Set of GPDR[63:32] */
1191 #define GSDR2 __REG(0x40E00408) /* Bit-wise Set of GPDR[95:64] */
1192 #define GSDR3 __REG(0x40E0040C) /* Bit-wise Set of GPDR[127:96] */
1194 #define GCDR0 __REG(0x40E00420) /* Bit-wise Clear of GPDR[31:0] */
1195 #define GCDR1 __REG(0x40E00424) /* Bit-wise Clear of GPDR[63:32] */
1196 #define GCDR2 __REG(0x40E00428) /* Bit-wise Clear of GPDR[95:64] */
1197 #define GCDR3 __REG(0x40E0042C) /* Bit-wise Clear of GPDR[127:96] */
1199 #define GSRER0 __REG(0x40E00440) /* Set Rising Edge Det. Enable [31:0] */
1200 #define GSRER1 __REG(0x40E00444) /* Set Rising Edge Det. Enable [63:32] */
1201 #define GSRER2 __REG(0x40E00448) /* Set Rising Edge Det. Enable [95:64] */
1202 #define GSRER3 __REG(0x40E0044C) /* Set Rising Edge Det. Enable [127:96] */
1204 #define GCRER0 __REG(0x40E00460) /* Clear Rising Edge Det. Enable [31:0] */
1205 #define GCRER1 __REG(0x40E00464) /* Clear Rising Edge Det. Enable [63:32] */
1206 #define GCRER2 __REG(0x40E00468) /* Clear Rising Edge Det. Enable [95:64] */
1207 #define GCRER3 __REG(0x40E0046C) /* Clear Rising Edge Det. Enable[127:96] */
1209 #define GSFER0 __REG(0x40E00480) /* Set Falling Edge Det. Enable [31:0] */
1210 #define GSFER1 __REG(0x40E00484) /* Set Falling Edge Det. Enable [63:32] */
1211 #define GSFER2 __REG(0x40E00488) /* Set Falling Edge Det. Enable [95:64] */
1212 #define GSFER3 __REG(0x40E0048C) /* Set Falling Edge Det. Enable[127:96] */
1214 #define GCFER0 __REG(0x40E004A0) /* Clr Falling Edge Det. Enable [31:0] */
1215 #define GCFER1 __REG(0x40E004A4) /* Clr Falling Edge Det. Enable [63:32] */
1216 #define GCFER2 __REG(0x40E004A8) /* Clr Falling Edge Det. Enable [95:64] */
1217 #define GCFER3 __REG(0x40E004AC) /* Clr Falling Edge Det. Enable[127:96] */
1219 #define GSDR(x) __REG2(0x40E00400, ((x) & 0x60) >> 3)
1220 #define GCDR(x) __REG2(0x40E00420, ((x) & 0x60) >> 3)
1222 /* Multi-funktion Pin Registers, uncomplete, only:
1224 * - Data Flash DF_* pins defined.
1226 #define GPIO0 __REG(0x40e10124)
1227 #define GPIO1 __REG(0x40e10128)
1228 #define GPIO2 __REG(0x40e1012c)
1229 #define GPIO3 __REG(0x40e10130)
1230 #define GPIO4 __REG(0x40e10134)
1231 #define nXCVREN __REG(0x40e10138)
1233 #define DF_CLE_NOE __REG(0x40e10204)
1234 #define DF_ALE_WE1 __REG(0x40e10208)
1236 #define DF_SCLK_E __REG(0x40e10210)
1237 #define nBE0 __REG(0x40e10214)
1238 #define nBE1 __REG(0x40e10218)
1239 #define DF_ALE_WE2 __REG(0x40e1021c)
1240 #define DF_INT_RnB __REG(0x40e10220)
1241 #define DF_nCS0 __REG(0x40e10224)
1242 #define DF_nCS1 __REG(0x40e10228)
1243 #define DF_nWE __REG(0x40e1022c)
1244 #define DF_nRE __REG(0x40e10230)
1245 #define nLUA __REG(0x40e10234)
1246 #define nLLA __REG(0x40e10238)
1247 #define DF_ADDR0 __REG(0x40e1023c)
1248 #define DF_ADDR1 __REG(0x40e10240)
1249 #define DF_ADDR2 __REG(0x40e10244)
1250 #define DF_ADDR3 __REG(0x40e10248)
1251 #define DF_IO0 __REG(0x40e1024c)
1252 #define DF_IO8 __REG(0x40e10250)
1253 #define DF_IO1 __REG(0x40e10254)
1254 #define DF_IO9 __REG(0x40e10258)
1255 #define DF_IO2 __REG(0x40e1025c)
1256 #define DF_IO10 __REG(0x40e10260)
1257 #define DF_IO3 __REG(0x40e10264)
1258 #define DF_IO11 __REG(0x40e10268)
1259 #define DF_IO4 __REG(0x40e1026c)
1260 #define DF_IO12 __REG(0x40e10270)
1261 #define DF_IO5 __REG(0x40e10274)
1262 #define DF_IO13 __REG(0x40e10278)
1263 #define DF_IO6 __REG(0x40e1027c)
1264 #define DF_IO14 __REG(0x40e10280)
1265 #define DF_IO7 __REG(0x40e10284)
1266 #define DF_IO15 __REG(0x40e10288)
1268 #define GPIO5 __REG(0x40e1028c)
1269 #define GPIO6 __REG(0x40e10290)
1270 #define GPIO7 __REG(0x40e10294)
1271 #define GPIO8 __REG(0x40e10298)
1272 #define GPIO9 __REG(0x40e1029c)
1274 #define GPIO11 __REG(0x40e102a0)
1275 #define GPIO12 __REG(0x40e102a4)
1276 #define GPIO13 __REG(0x40e102a8)
1277 #define GPIO14 __REG(0x40e102ac)
1278 #define GPIO15 __REG(0x40e102b0)
1279 #define GPIO16 __REG(0x40e102b4)
1280 #define GPIO17 __REG(0x40e102b8)
1281 #define GPIO18 __REG(0x40e102bc)
1282 #define GPIO19 __REG(0x40e102c0)
1283 #define GPIO20 __REG(0x40e102c4)
1284 #define GPIO21 __REG(0x40e102c8)
1285 #define GPIO22 __REG(0x40e102cc)
1286 #define GPIO23 __REG(0x40e102d0)
1287 #define GPIO24 __REG(0x40e102d4)
1288 #define GPIO25 __REG(0x40e102d8)
1289 #define GPIO26 __REG(0x40e102dc)
1291 #define GPIO27 __REG(0x40e10400)
1292 #define GPIO28 __REG(0x40e10404)
1293 #define GPIO29 __REG(0x40e10408)
1294 #define GPIO30 __REG(0x40e1040c)
1295 #define GPIO31 __REG(0x40e10410)
1296 #define GPIO32 __REG(0x40e10414)
1297 #define GPIO33 __REG(0x40e10418)
1298 #define GPIO34 __REG(0x40e1041c)
1299 #define GPIO35 __REG(0x40e10420)
1300 #define GPIO36 __REG(0x40e10424)
1301 #define GPIO37 __REG(0x40e10428)
1302 #define GPIO38 __REG(0x40e1042c)
1303 #define GPIO39 __REG(0x40e10430)
1304 #define GPIO40 __REG(0x40e10434)
1305 #define GPIO41 __REG(0x40e10438)
1306 #define GPIO42 __REG(0x40e1043c)
1307 #define GPIO43 __REG(0x40e10440)
1308 #define GPIO44 __REG(0x40e10444)
1309 #define GPIO45 __REG(0x40e10448)
1310 #define GPIO46 __REG(0x40e1044c)
1311 #define GPIO47 __REG(0x40e10450)
1312 #define GPIO48 __REG(0x40e10454)
1314 #define GPIO10 __REG(0x40e10458)
1316 #define GPIO49 __REG(0x40e1045c)
1317 #define GPIO50 __REG(0x40e10460)
1318 #define GPIO51 __REG(0x40e10464)
1319 #define GPIO52 __REG(0x40e10468)
1320 #define GPIO53 __REG(0x40e1046c)
1321 #define GPIO54 __REG(0x40e10470)
1322 #define GPIO55 __REG(0x40e10474)
1323 #define GPIO56 __REG(0x40e10478)
1324 #define GPIO57 __REG(0x40e1047c)
1325 #define GPIO58 __REG(0x40e10480)
1326 #define GPIO59 __REG(0x40e10484)
1327 #define GPIO60 __REG(0x40e10488)
1328 #define GPIO61 __REG(0x40e1048c)
1329 #define GPIO62 __REG(0x40e10490)
1331 #define GPIO6_2 __REG(0x40e10494)
1332 #define GPIO7_2 __REG(0x40e10498)
1333 #define GPIO8_2 __REG(0x40e1049c)
1334 #define GPIO9_2 __REG(0x40e104a0)
1335 #define GPIO10_2 __REG(0x40e104a4)
1336 #define GPIO11_2 __REG(0x40e104a8)
1337 #define GPIO12_2 __REG(0x40e104ac)
1338 #define GPIO13_2 __REG(0x40e104b0)
1340 #define GPIO63 __REG(0x40e104b4)
1341 #define GPIO64 __REG(0x40e104b8)
1342 #define GPIO65 __REG(0x40e104bc)
1343 #define GPIO66 __REG(0x40e104c0)
1344 #define GPIO67 __REG(0x40e104c4)
1345 #define GPIO68 __REG(0x40e104c8)
1346 #define GPIO69 __REG(0x40e104cc)
1347 #define GPIO70 __REG(0x40e104d0)
1348 #define GPIO71 __REG(0x40e104d4)
1349 #define GPIO72 __REG(0x40e104d8)
1350 #define GPIO73 __REG(0x40e104dc)
1352 #define GPIO14_2 __REG(0x40e104e0)
1353 #define GPIO15_2 __REG(0x40e104e4)
1354 #define GPIO16_2 __REG(0x40e104e8)
1355 #define GPIO17_2 __REG(0x40e104ec)
1357 #define GPIO74 __REG(0x40e104f0)
1358 #define GPIO75 __REG(0x40e104f4)
1359 #define GPIO76 __REG(0x40e104f8)
1360 #define GPIO77 __REG(0x40e104fc)
1361 #define GPIO78 __REG(0x40e10500)
1362 #define GPIO79 __REG(0x40e10504)
1363 #define GPIO80 __REG(0x40e10508)
1364 #define GPIO81 __REG(0x40e1050c)
1365 #define GPIO82 __REG(0x40e10510)
1366 #define GPIO83 __REG(0x40e10514)
1367 #define GPIO84 __REG(0x40e10518)
1368 #define GPIO85 __REG(0x40e1051c)
1369 #define GPIO86 __REG(0x40e10520)
1370 #define GPIO87 __REG(0x40e10524)
1371 #define GPIO88 __REG(0x40e10528)
1372 #define GPIO89 __REG(0x40e1052c)
1373 #define GPIO90 __REG(0x40e10530)
1374 #define GPIO91 __REG(0x40e10534)
1375 #define GPIO92 __REG(0x40e10538)
1376 #define GPIO93 __REG(0x40e1053c)
1377 #define GPIO94 __REG(0x40e10540)
1378 #define GPIO95 __REG(0x40e10544)
1379 #define GPIO96 __REG(0x40e10548)
1380 #define GPIO97 __REG(0x40e1054c)
1381 #define GPIO98 __REG(0x40e10550)
1383 #define GPIO99 __REG(0x40e10600)
1384 #define GPIO100 __REG(0x40e10604)
1385 #define GPIO101 __REG(0x40e10608)
1386 #define GPIO102 __REG(0x40e1060c)
1387 #define GPIO103 __REG(0x40e10610)
1388 #define GPIO104 __REG(0x40e10614)
1389 #define GPIO105 __REG(0x40e10618)
1390 #define GPIO106 __REG(0x40e1061c)
1391 #define GPIO107 __REG(0x40e10620)
1392 #define GPIO108 __REG(0x40e10624)
1393 #define GPIO109 __REG(0x40e10628)
1394 #define GPIO110 __REG(0x40e1062c)
1395 #define GPIO111 __REG(0x40e10630)
1396 #define GPIO112 __REG(0x40e10634)
1398 #define GPIO113 __REG(0x40e10638)
1399 #define GPIO114 __REG(0x40e1063c)
1400 #define GPIO115 __REG(0x40e10640)
1401 #define GPIO116 __REG(0x40e10644)
1402 #define GPIO117 __REG(0x40e10648)
1403 #define GPIO118 __REG(0x40e1064c)
1404 #define GPIO119 __REG(0x40e10650)
1405 #define GPIO120 __REG(0x40e10654)
1406 #define GPIO121 __REG(0x40e10658)
1407 #define GPIO122 __REG(0x40e1065c)
1408 #define GPIO123 __REG(0x40e10660)
1409 #define GPIO124 __REG(0x40e10664)
1410 #define GPIO125 __REG(0x40e10668)
1411 #define GPIO126 __REG(0x40e1066c)
1412 #define GPIO127 __REG(0x40e10670)
1414 #define GPIO0_2 __REG(0x40e10674)
1415 #define GPIO1_2 __REG(0x40e10678)
1416 #define GPIO2_2 __REG(0x40e1067c)
1417 #define GPIO3_2 __REG(0x40e10680)
1418 #define GPIO4_2 __REG(0x40e10684)
1419 #define GPIO5_2 __REG(0x40e10688)
1421 /* MFPR Bit Definitions, see 4-10, Vol. 1 */
1422 #define PULL_SEL 0x8000
1423 #define PULLUP_EN 0x4000
1424 #define PULLDOWN_EN 0x2000
1426 #define DRIVE_FAST_1mA 0x0
1427 #define DRIVE_FAST_2mA 0x400
1428 #define DRIVE_FAST_3mA 0x800
1429 #define DRIVE_FAST_4mA 0xC00
1430 #define DRIVE_SLOW_6mA 0x1000
1431 #define DRIVE_FAST_6mA 0x1400
1432 #define DRIVE_SLOW_10mA 0x1800
1433 #define DRIVE_FAST_10mA 0x1C00
1435 #define SLEEP_SEL 0x200
1436 #define SLEEP_DATA 0x100
1437 #define SLEEP_OE_N 0x80
1438 #define EDGE_CLEAR 0x40
1439 #define EDGE_FALL_EN 0x20
1440 #define EDGE_RISE_EN 0x10
1442 #define AF_SEL_0 0x0 /* Alternate function 0 (reset state) */
1443 #define AF_SEL_1 0x1 /* Alternate function 1 */
1444 #define AF_SEL_2 0x2 /* Alternate function 2 */
1445 #define AF_SEL_3 0x3 /* Alternate function 3 */
1446 #define AF_SEL_4 0x4 /* Alternate function 4 */
1447 #define AF_SEL_5 0x5 /* Alternate function 5 */
1448 #define AF_SEL_6 0x6 /* Alternate function 6 */
1449 #define AF_SEL_7 0x7 /* Alternate function 7 */
1452 #else /* CONFIG_CPU_MONAHANS */
1454 #define GAFR0_L __REG(0x40E00054) /* GPIO Alternate Function Select Register GPIO<15:0> */
1455 #define GAFR0_U __REG(0x40E00058) /* GPIO Alternate Function Select Register GPIO<31:16> */
1456 #define GAFR1_L __REG(0x40E0005C) /* GPIO Alternate Function Select Register GPIO<47:32> */
1457 #define GAFR1_U __REG(0x40E00060) /* GPIO Alternate Function Select Register GPIO<63:48> */
1458 #define GAFR2_L __REG(0x40E00064) /* GPIO Alternate Function Select Register GPIO<79:64> */
1459 #define GAFR2_U __REG(0x40E00068) /* GPIO Alternate Function Select Register GPIO 80 */
1460 #endif /* CONFIG_CPU_MONAHANS */
1462 /* More handy macros. The argument is a literal GPIO number. */
1464 #define GPIO_bit(x) (1 << ((x) & 0x1f))
1466 #ifdef CONFIG_PXA27X
1468 /* Interrupt Controller */
1470 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
1471 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
1472 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
1473 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
1474 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
1476 #define _GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1477 #define _GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1478 #define _GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1479 #define _GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1480 #define _GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1481 #define _GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1482 #define _GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1483 #define _GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1485 #define GPLR(x) (*((((x) & 0x7f) < 96) ? &_GPLR(x) : &GPLR3))
1486 #define GPDR(x) (*((((x) & 0x7f) < 96) ? &_GPDR(x) : &GPDR3))
1487 #define GPSR(x) (*((((x) & 0x7f) < 96) ? &_GPSR(x) : &GPSR3))
1488 #define GPCR(x) (*((((x) & 0x7f) < 96) ? &_GPCR(x) : &GPCR3))
1489 #define GRER(x) (*((((x) & 0x7f) < 96) ? &_GRER(x) : &GRER3))
1490 #define GFER(x) (*((((x) & 0x7f) < 96) ? &_GFER(x) : &GFER3))
1491 #define GEDR(x) (*((((x) & 0x7f) < 96) ? &_GEDR(x) : &GEDR3))
1492 #define GAFR(x) (*((((x) & 0x7f) < 96) ? &_GAFR(x) : \
1493 ((((x) & 0x7f) < 112) ? &GAFR3_L : &GAFR3_U)))
1496 #define GPLR(x) __REG2(0x40E00000, ((x) & 0x60) >> 3)
1497 #define GPDR(x) __REG2(0x40E0000C, ((x) & 0x60) >> 3)
1498 #define GPSR(x) __REG2(0x40E00018, ((x) & 0x60) >> 3)
1499 #define GPCR(x) __REG2(0x40E00024, ((x) & 0x60) >> 3)
1500 #define GRER(x) __REG2(0x40E00030, ((x) & 0x60) >> 3)
1501 #define GFER(x) __REG2(0x40E0003C, ((x) & 0x60) >> 3)
1502 #define GEDR(x) __REG2(0x40E00048, ((x) & 0x60) >> 3)
1503 #define GAFR(x) __REG2(0x40E00054, ((x) & 0x70) >> 2)
1507 /* GPIO alternate function assignments */
1509 #define GPIO1_RST 1 /* reset */
1510 #define GPIO6_MMCCLK 6 /* MMC Clock */
1511 #define GPIO8_48MHz 7 /* 48 MHz clock output */
1512 #define GPIO8_MMCCS0 8 /* MMC Chip Select 0 */
1513 #define GPIO9_MMCCS1 9 /* MMC Chip Select 1 */
1514 #define GPIO10_RTCCLK 10 /* real time clock (1 Hz) */
1515 #define GPIO11_3_6MHz 11 /* 3.6 MHz oscillator out */
1516 #define GPIO12_32KHz 12 /* 32 kHz out */
1517 #define GPIO13_MBGNT 13 /* memory controller grant */
1518 #define GPIO14_MBREQ 14 /* alternate bus master request */
1519 #define GPIO15_nCS_1 15 /* chip select 1 */
1520 #define GPIO16_PWM0 16 /* PWM0 output */
1521 #define GPIO17_PWM1 17 /* PWM1 output */
1522 #define GPIO18_RDY 18 /* Ext. Bus Ready */
1523 #define GPIO19_DREQ1 19 /* External DMA Request */
1524 #define GPIO20_DREQ0 20 /* External DMA Request */
1525 #define GPIO23_SCLK 23 /* SSP clock */
1526 #define GPIO24_SFRM 24 /* SSP Frame */
1527 #define GPIO25_STXD 25 /* SSP transmit */
1528 #define GPIO26_SRXD 26 /* SSP receive */
1529 #define GPIO27_SEXTCLK 27 /* SSP ext_clk */
1530 #define GPIO28_BITCLK 28 /* AC97/I2S bit_clk */
1531 #define GPIO29_SDATA_IN 29 /* AC97 Sdata_in0 / I2S Sdata_in */
1532 #define GPIO30_SDATA_OUT 30 /* AC97/I2S Sdata_out */
1533 #define GPIO31_SYNC 31 /* AC97/I2S sync */
1534 #define GPIO32_SDATA_IN1 32 /* AC97 Sdata_in1 */
1535 #define GPIO33_nCS_5 33 /* chip select 5 */
1536 #define GPIO34_FFRXD 34 /* FFUART receive */
1537 #define GPIO34_MMCCS0 34 /* MMC Chip Select 0 */
1538 #define GPIO35_FFCTS 35 /* FFUART Clear to send */
1539 #define GPIO36_FFDCD 36 /* FFUART Data carrier detect */
1540 #define GPIO37_FFDSR 37 /* FFUART data set ready */
1541 #define GPIO38_FFRI 38 /* FFUART Ring Indicator */
1542 #define GPIO39_MMCCS1 39 /* MMC Chip Select 1 */
1543 #define GPIO39_FFTXD 39 /* FFUART transmit data */
1544 #define GPIO40_FFDTR 40 /* FFUART data terminal Ready */
1545 #define GPIO41_FFRTS 41 /* FFUART request to send */
1546 #define GPIO42_BTRXD 42 /* BTUART receive data */
1547 #define GPIO43_BTTXD 43 /* BTUART transmit data */
1548 #define GPIO44_BTCTS 44 /* BTUART clear to send */
1549 #define GPIO45_BTRTS 45 /* BTUART request to send */
1550 #define GPIO46_ICPRXD 46 /* ICP receive data */
1551 #define GPIO46_STRXD 46 /* STD_UART receive data */
1552 #define GPIO47_ICPTXD 47 /* ICP transmit data */
1553 #define GPIO47_STTXD 47 /* STD_UART transmit data */
1554 #define GPIO48_nPOE 48 /* Output Enable for Card Space */
1555 #define GPIO49_nPWE 49 /* Write Enable for Card Space */
1556 #define GPIO50_nPIOR 50 /* I/O Read for Card Space */
1557 #define GPIO51_nPIOW 51 /* I/O Write for Card Space */
1558 #define GPIO52_nPCE_1 52 /* Card Enable for Card Space */
1559 #define GPIO53_nPCE_2 53 /* Card Enable for Card Space */
1560 #define GPIO53_MMCCLK 53 /* MMC Clock */
1561 #define GPIO54_MMCCLK 54 /* MMC Clock */
1562 #define GPIO54_pSKTSEL 54 /* Socket Select for Card Space */
1563 #define GPIO55_nPREG 55 /* Card Address bit 26 */
1564 #define GPIO56_nPWAIT 56 /* Wait signal for Card Space */
1565 #define GPIO57_nIOIS16 57 /* Bus Width select for I/O Card Space */
1566 #define GPIO58_LDD_0 58 /* LCD data pin 0 */
1567 #define GPIO59_LDD_1 59 /* LCD data pin 1 */
1568 #define GPIO60_LDD_2 60 /* LCD data pin 2 */
1569 #define GPIO61_LDD_3 61 /* LCD data pin 3 */
1570 #define GPIO62_LDD_4 62 /* LCD data pin 4 */
1571 #define GPIO63_LDD_5 63 /* LCD data pin 5 */
1572 #define GPIO64_LDD_6 64 /* LCD data pin 6 */
1573 #define GPIO65_LDD_7 65 /* LCD data pin 7 */
1574 #define GPIO66_LDD_8 66 /* LCD data pin 8 */
1575 #define GPIO66_MBREQ 66 /* alternate bus master req */
1576 #define GPIO67_LDD_9 67 /* LCD data pin 9 */
1577 #define GPIO67_MMCCS0 67 /* MMC Chip Select 0 */
1578 #define GPIO68_LDD_10 68 /* LCD data pin 10 */
1579 #define GPIO68_MMCCS1 68 /* MMC Chip Select 1 */
1580 #define GPIO69_LDD_11 69 /* LCD data pin 11 */
1581 #define GPIO69_MMCCLK 69 /* MMC_CLK */
1582 #define GPIO70_LDD_12 70 /* LCD data pin 12 */
1583 #define GPIO70_RTCCLK 70 /* Real Time clock (1 Hz) */
1584 #define GPIO71_LDD_13 71 /* LCD data pin 13 */
1585 #define GPIO71_3_6MHz 71 /* 3.6 MHz Oscillator clock */
1586 #define GPIO72_LDD_14 72 /* LCD data pin 14 */
1587 #define GPIO72_32kHz 72 /* 32 kHz clock */
1588 #define GPIO73_LDD_15 73 /* LCD data pin 15 */
1589 #define GPIO73_MBGNT 73 /* Memory controller grant */
1590 #define GPIO74_LCD_FCLK 74 /* LCD Frame clock */
1591 #define GPIO75_LCD_LCLK 75 /* LCD line clock */
1592 #define GPIO76_LCD_PCLK 76 /* LCD Pixel clock */
1593 #define GPIO77_LCD_ACBIAS 77 /* LCD AC Bias */
1594 #define GPIO78_nCS_2 78 /* chip select 2 */
1595 #define GPIO79_nCS_3 79 /* chip select 3 */
1596 #define GPIO80_nCS_4 80 /* chip select 4 */
1598 /* GPIO alternate function mode & direction */
1600 #define GPIO_IN 0x000
1601 #define GPIO_OUT 0x080
1602 #define GPIO_ALT_FN_1_IN 0x100
1603 #define GPIO_ALT_FN_1_OUT 0x180
1604 #define GPIO_ALT_FN_2_IN 0x200
1605 #define GPIO_ALT_FN_2_OUT 0x280
1606 #define GPIO_ALT_FN_3_IN 0x300
1607 #define GPIO_ALT_FN_3_OUT 0x380
1608 #define GPIO_MD_MASK_NR 0x07f
1609 #define GPIO_MD_MASK_DIR 0x080
1610 #define GPIO_MD_MASK_FN 0x300
1612 #define GPIO1_RTS_MD ( 1 | GPIO_ALT_FN_1_IN)
1613 #define GPIO6_MMCCLK_MD ( 6 | GPIO_ALT_FN_1_OUT)
1614 #define GPIO8_48MHz_MD ( 8 | GPIO_ALT_FN_1_OUT)
1615 #define GPIO8_MMCCS0_MD ( 8 | GPIO_ALT_FN_1_OUT)
1616 #define GPIO9_MMCCS1_MD ( 9 | GPIO_ALT_FN_1_OUT)
1617 #define GPIO10_RTCCLK_MD (10 | GPIO_ALT_FN_1_OUT)
1618 #define GPIO11_3_6MHz_MD (11 | GPIO_ALT_FN_1_OUT)
1619 #define GPIO12_32KHz_MD (12 | GPIO_ALT_FN_1_OUT)
1620 #define GPIO13_MBGNT_MD (13 | GPIO_ALT_FN_2_OUT)
1621 #define GPIO14_MBREQ_MD (14 | GPIO_ALT_FN_1_IN)
1622 #define GPIO15_nCS_1_MD (15 | GPIO_ALT_FN_2_OUT)
1623 #define GPIO16_PWM0_MD (16 | GPIO_ALT_FN_2_OUT)
1624 #define GPIO17_PWM1_MD (17 | GPIO_ALT_FN_2_OUT)
1625 #define GPIO18_RDY_MD (18 | GPIO_ALT_FN_1_IN)
1626 #define GPIO19_DREQ1_MD (19 | GPIO_ALT_FN_1_IN)
1627 #define GPIO20_DREQ0_MD (20 | GPIO_ALT_FN_1_IN)
1628 #define GPIO23_SCLK_md (23 | GPIO_ALT_FN_2_OUT)
1629 #define GPIO24_SFRM_MD (24 | GPIO_ALT_FN_2_OUT)
1630 #define GPIO25_STXD_MD (25 | GPIO_ALT_FN_2_OUT)
1631 #define GPIO26_SRXD_MD (26 | GPIO_ALT_FN_1_IN)
1632 #define GPIO27_SEXTCLK_MD (27 | GPIO_ALT_FN_1_IN)
1633 #define GPIO28_BITCLK_AC97_MD (28 | GPIO_ALT_FN_1_IN)
1634 #define GPIO28_BITCLK_I2S_MD (28 | GPIO_ALT_FN_2_IN)
1635 #define GPIO29_SDATA_IN_AC97_MD (29 | GPIO_ALT_FN_1_IN)
1636 #define GPIO29_SDATA_IN_I2S_MD (29 | GPIO_ALT_FN_2_IN)
1637 #define GPIO30_SDATA_OUT_AC97_MD (30 | GPIO_ALT_FN_2_OUT)
1638 #define GPIO30_SDATA_OUT_I2S_MD (30 | GPIO_ALT_FN_1_OUT)
1639 #define GPIO31_SYNC_AC97_MD (31 | GPIO_ALT_FN_2_OUT)
1640 #define GPIO31_SYNC_I2S_MD (31 | GPIO_ALT_FN_1_OUT)
1641 #define GPIO32_SDATA_IN1_AC97_MD (32 | GPIO_ALT_FN_1_IN)
1642 #define GPIO33_nCS_5_MD (33 | GPIO_ALT_FN_2_OUT)
1643 #define GPIO34_FFRXD_MD (34 | GPIO_ALT_FN_1_IN)
1644 #define GPIO34_MMCCS0_MD (34 | GPIO_ALT_FN_2_OUT)
1645 #define GPIO35_FFCTS_MD (35 | GPIO_ALT_FN_1_IN)
1646 #define GPIO36_FFDCD_MD (36 | GPIO_ALT_FN_1_IN)
1647 #define GPIO37_FFDSR_MD (37 | GPIO_ALT_FN_1_IN)
1648 #define GPIO38_FFRI_MD (38 | GPIO_ALT_FN_1_IN)
1649 #define GPIO39_MMCCS1_MD (39 | GPIO_ALT_FN_1_OUT)
1650 #define GPIO39_FFTXD_MD (39 | GPIO_ALT_FN_2_OUT)
1651 #define GPIO40_FFDTR_MD (40 | GPIO_ALT_FN_2_OUT)
1652 #define GPIO41_FFRTS_MD (41 | GPIO_ALT_FN_2_OUT)
1653 #define GPIO42_BTRXD_MD (42 | GPIO_ALT_FN_1_IN)
1654 #define GPIO43_BTTXD_MD (43 | GPIO_ALT_FN_2_OUT)
1655 #define GPIO44_BTCTS_MD (44 | GPIO_ALT_FN_1_IN)
1656 #define GPIO45_BTRTS_MD (45 | GPIO_ALT_FN_2_OUT)
1657 #define GPIO46_ICPRXD_MD (46 | GPIO_ALT_FN_1_IN)
1658 #define GPIO46_STRXD_MD (46 | GPIO_ALT_FN_2_IN)
1659 #define GPIO47_ICPTXD_MD (47 | GPIO_ALT_FN_2_OUT)
1660 #define GPIO47_STTXD_MD (47 | GPIO_ALT_FN_1_OUT)
1661 #define GPIO48_nPOE_MD (48 | GPIO_ALT_FN_2_OUT)
1662 #define GPIO49_nPWE_MD (49 | GPIO_ALT_FN_2_OUT)
1663 #define GPIO50_nPIOR_MD (50 | GPIO_ALT_FN_2_OUT)
1664 #define GPIO51_nPIOW_MD (51 | GPIO_ALT_FN_2_OUT)
1665 #define GPIO52_nPCE_1_MD (52 | GPIO_ALT_FN_2_OUT)
1666 #define GPIO53_nPCE_2_MD (53 | GPIO_ALT_FN_2_OUT)
1667 #define GPIO53_MMCCLK_MD (53 | GPIO_ALT_FN_1_OUT)
1668 #define GPIO54_MMCCLK_MD (54 | GPIO_ALT_FN_1_OUT)
1669 #define GPIO54_pSKTSEL_MD (54 | GPIO_ALT_FN_2_OUT)
1670 #define GPIO55_nPREG_MD (55 | GPIO_ALT_FN_2_OUT)
1671 #define GPIO56_nPWAIT_MD (56 | GPIO_ALT_FN_1_IN)
1672 #define GPIO57_nIOIS16_MD (57 | GPIO_ALT_FN_1_IN)
1673 #define GPIO58_LDD_0_MD (58 | GPIO_ALT_FN_2_OUT)
1674 #define GPIO59_LDD_1_MD (59 | GPIO_ALT_FN_2_OUT)
1675 #define GPIO60_LDD_2_MD (60 | GPIO_ALT_FN_2_OUT)
1676 #define GPIO61_LDD_3_MD (61 | GPIO_ALT_FN_2_OUT)
1677 #define GPIO62_LDD_4_MD (62 | GPIO_ALT_FN_2_OUT)
1678 #define GPIO63_LDD_5_MD (63 | GPIO_ALT_FN_2_OUT)
1679 #define GPIO64_LDD_6_MD (64 | GPIO_ALT_FN_2_OUT)
1680 #define GPIO65_LDD_7_MD (65 | GPIO_ALT_FN_2_OUT)
1681 #define GPIO66_LDD_8_MD (66 | GPIO_ALT_FN_2_OUT)
1682 #define GPIO66_MBREQ_MD (66 | GPIO_ALT_FN_1_IN)
1683 #define GPIO67_LDD_9_MD (67 | GPIO_ALT_FN_2_OUT)
1684 #define GPIO67_MMCCS0_MD (67 | GPIO_ALT_FN_1_OUT)
1685 #define GPIO68_LDD_10_MD (68 | GPIO_ALT_FN_2_OUT)
1686 #define GPIO68_MMCCS1_MD (68 | GPIO_ALT_FN_1_OUT)
1687 #define GPIO69_LDD_11_MD (69 | GPIO_ALT_FN_2_OUT)
1688 #define GPIO69_MMCCLK_MD (69 | GPIO_ALT_FN_1_OUT)
1689 #define GPIO70_LDD_12_MD (70 | GPIO_ALT_FN_2_OUT)
1690 #define GPIO70_RTCCLK_MD (70 | GPIO_ALT_FN_1_OUT)
1691 #define GPIO71_LDD_13_MD (71 | GPIO_ALT_FN_2_OUT)
1692 #define GPIO71_3_6MHz_MD (71 | GPIO_ALT_FN_1_OUT)
1693 #define GPIO72_LDD_14_MD (72 | GPIO_ALT_FN_2_OUT)
1694 #define GPIO72_32kHz_MD (72 | GPIO_ALT_FN_1_OUT)
1695 #define GPIO73_LDD_15_MD (73 | GPIO_ALT_FN_2_OUT)
1696 #define GPIO73_MBGNT_MD (73 | GPIO_ALT_FN_1_OUT)
1697 #define GPIO74_LCD_FCLK_MD (74 | GPIO_ALT_FN_2_OUT)
1698 #define GPIO75_LCD_LCLK_MD (75 | GPIO_ALT_FN_2_OUT)
1699 #define GPIO76_LCD_PCLK_MD (76 | GPIO_ALT_FN_2_OUT)
1700 #define GPIO77_LCD_ACBIAS_MD (77 | GPIO_ALT_FN_2_OUT)
1701 #define GPIO78_nCS_2_MD (78 | GPIO_ALT_FN_2_OUT)
1702 #define GPIO79_nCS_3_MD (79 | GPIO_ALT_FN_2_OUT)
1703 #define GPIO80_nCS_4_MD (80 | GPIO_ALT_FN_2_OUT)
1705 #define GPIO117_SCL (117 | GPIO_ALT_FN_1_OUT)
1706 #define GPIO118_SDA (118 | GPIO_ALT_FN_1_OUT)
1711 #ifdef CONFIG_CPU_MONAHANS
1713 #define ASCR __REG(0x40F40000) /* Application Subsystem Power Status/Control Register */
1714 #define ARSR __REG(0x40F40004) /* Application Subsystem Reset Status Register */
1715 #define AD3ER __REG(0x40F40008) /* Application Subsystem D3 state Wakeup Enable Register */
1716 #define AD3SR __REG(0x40F4000C) /* Application Subsystem D3 state Wakeup Status Register */
1717 #define AD2D0ER __REG(0x40F40010) /* Application Subsystem D2 to D0 state Wakeup Enable Register */
1718 #define AD2D0SR __REG(0x40F40014) /* Application Subsystem D2 to D0 state Wakeup Status Register */
1719 #define AD2D1ER __REG(0x40F40018) /* Application Subsystem D2 to D1 state Wakeup Enable Register */
1720 #define AD2D1SR __REG(0x40F4001C) /* Application Subsystem D2 to D1 state Wakeup Status Register */
1721 #define AD1D0ER __REG(0x40F40020) /* Application Subsystem D1 to D0 state Wakeup Enable Register */
1722 #define AD1D0SR __REG(0x40F40024) /* Application Subsystem D1 to D0 state Wakeup Status Register */
1723 #define ASDCNT __REG(0x40F40028) /* Application Subsystem SRAM Drowsy Count Register */
1724 #define AD3R __REG(0x40F40030) /* Application Subsystem D3 State Configuration Register */
1725 #define AD2R __REG(0x40F40034) /* Application Subsystem D2 State Configuration Register */
1726 #define AD1R __REG(0x40F40038) /* Application Subsystem D1 State Configuration Register */
1728 #define PMCR __REG(0x40F50000) /* Power Manager Control Register */
1729 #define PSR __REG(0x40F50004) /* Power Manager S2 Status Register */
1730 #define PSPR __REG(0x40F50008) /* Power Manager Scratch Pad Register */
1731 #define PCFR __REG(0x40F5000C) /* Power Manager General Configuration Register */
1732 #define PWER __REG(0x40F50010) /* Power Manager Wake-up Enable Register */
1733 #define PWSR __REG(0x40F50014) /* Power Manager Wake-up Status Register */
1734 #define PECR __REG(0x40F50018) /* Power Manager EXT_WAKEUP[1:0] Control Register */
1735 #define DCDCSR __REG(0x40F50080) /* DC-DC Controller Status Register */
1736 #define PVCR __REG(0x40F50100) /* Power Manager Voltage Change Control Register */
1737 #define PCMD(x) __REG(0x40F50110 + x*4)
1738 #define PCMD0 __REG(0x40F50110 + 0 * 4)
1739 #define PCMD1 __REG(0x40F50110 + 1 * 4)
1740 #define PCMD2 __REG(0x40F50110 + 2 * 4)
1741 #define PCMD3 __REG(0x40F50110 + 3 * 4)
1742 #define PCMD4 __REG(0x40F50110 + 4 * 4)
1743 #define PCMD5 __REG(0x40F50110 + 5 * 4)
1744 #define PCMD6 __REG(0x40F50110 + 6 * 4)
1745 #define PCMD7 __REG(0x40F50110 + 7 * 4)
1746 #define PCMD8 __REG(0x40F50110 + 8 * 4)
1747 #define PCMD9 __REG(0x40F50110 + 9 * 4)
1748 #define PCMD10 __REG(0x40F50110 + 10 * 4)
1749 #define PCMD11 __REG(0x40F50110 + 11 * 4)
1750 #define PCMD12 __REG(0x40F50110 + 12 * 4)
1751 #define PCMD13 __REG(0x40F50110 + 13 * 4)
1752 #define PCMD14 __REG(0x40F50110 + 14 * 4)
1753 #define PCMD15 __REG(0x40F50110 + 15 * 4)
1754 #define PCMD16 __REG(0x40F50110 + 16 * 4)
1755 #define PCMD17 __REG(0x40F50110 + 17 * 4)
1756 #define PCMD18 __REG(0x40F50110 + 18 * 4)
1757 #define PCMD19 __REG(0x40F50110 + 19 * 4)
1758 #define PCMD20 __REG(0x40F50110 + 20 * 4)
1759 #define PCMD21 __REG(0x40F50110 + 21 * 4)
1760 #define PCMD22 __REG(0x40F50110 + 22 * 4)
1761 #define PCMD23 __REG(0x40F50110 + 23 * 4)
1762 #define PCMD24 __REG(0x40F50110 + 24 * 4)
1763 #define PCMD25 __REG(0x40F50110 + 25 * 4)
1764 #define PCMD26 __REG(0x40F50110 + 26 * 4)
1765 #define PCMD27 __REG(0x40F50110 + 27 * 4)
1766 #define PCMD28 __REG(0x40F50110 + 28 * 4)
1767 #define PCMD29 __REG(0x40F50110 + 29 * 4)
1768 #define PCMD30 __REG(0x40F50110 + 30 * 4)
1769 #define PCMD31 __REG(0x40F50110 + 31 * 4)
1771 #define PCMD_MBC (1<<12)
1772 #define PCMD_DCE (1<<11)
1773 #define PCMD_LC (1<<10)
1774 #define PCMD_SQC (3<<8) /* only 00 and 01 are valid */
1776 #define PVCR_FVC (0x1 << 28)
1777 #define PVCR_VCSA (0x1<<14)
1778 #define PVCR_CommandDelay (0xf80)
1779 #define PVCR_ReadPointer (0x01f00000)
1780 #define PVCR_SlaveAddress (0x7f)
1782 #else /* ifdef CONFIG_CPU_MONAHANS */
1784 #define PMCR __REG(0x40F00000) /* Power Manager Control Register */
1785 #define PSSR __REG(0x40F00004) /* Power Manager Sleep Status Register */
1786 #define PSPR __REG(0x40F00008) /* Power Manager Scratch Pad Register */
1787 #define PWER __REG(0x40F0000C) /* Power Manager Wake-up Enable Register */
1788 #define PRER __REG(0x40F00010) /* Power Manager GPIO Rising-Edge Detect Enable Register */
1789 #define PFER __REG(0x40F00014) /* Power Manager GPIO Falling-Edge Detect Enable Register */
1790 #define PEDR __REG(0x40F00018) /* Power Manager GPIO Edge Detect Status Register */
1791 #define PCFR __REG(0x40F0001C) /* Power Manager General Configuration Register */
1792 #define PGSR0 __REG(0x40F00020) /* Power Manager GPIO Sleep State Register for GP[31-0] */
1793 #define PGSR1 __REG(0x40F00024) /* Power Manager GPIO Sleep State Register for GP[63-32] */
1794 #define PGSR2 __REG(0x40F00028) /* Power Manager GPIO Sleep State Register for GP[84-64] */
1795 #define PGSR3 __REG(0x40F0002C) /* Power Manager GPIO Sleep State Register for GP[118-96] */
1796 #define RCSR __REG(0x40F00030) /* Reset Controller Status Register */
1798 #define PSLR __REG(0x40F00034) /* Power Manager Sleep Config Register */
1799 #define PSTR __REG(0x40F00038) /* Power Manager Standby Config Register */
1800 #define PSNR __REG(0x40F0003C) /* Power Manager Sense Config Register */
1801 #define PVCR __REG(0x40F00040) /* Power Manager VoltageControl Register */
1802 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-up Enable Reg */
1803 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Register */
1804 #define PCMD(x) __REG(0x40F00080 + x*4)
1805 #define PCMD0 __REG(0x40F00080 + 0 * 4)
1806 #define PCMD1 __REG(0x40F00080 + 1 * 4)
1807 #define PCMD2 __REG(0x40F00080 + 2 * 4)
1808 #define PCMD3 __REG(0x40F00080 + 3 * 4)
1809 #define PCMD4 __REG(0x40F00080 + 4 * 4)
1810 #define PCMD5 __REG(0x40F00080 + 5 * 4)
1811 #define PCMD6 __REG(0x40F00080 + 6 * 4)
1812 #define PCMD7 __REG(0x40F00080 + 7 * 4)
1813 #define PCMD8 __REG(0x40F00080 + 8 * 4)
1814 #define PCMD9 __REG(0x40F00080 + 9 * 4)
1815 #define PCMD10 __REG(0x40F00080 + 10 * 4)
1816 #define PCMD11 __REG(0x40F00080 + 11 * 4)
1817 #define PCMD12 __REG(0x40F00080 + 12 * 4)
1818 #define PCMD13 __REG(0x40F00080 + 13 * 4)
1819 #define PCMD14 __REG(0x40F00080 + 14 * 4)
1820 #define PCMD15 __REG(0x40F00080 + 15 * 4)
1821 #define PCMD16 __REG(0x40F00080 + 16 * 4)
1822 #define PCMD17 __REG(0x40F00080 + 17 * 4)
1823 #define PCMD18 __REG(0x40F00080 + 18 * 4)
1824 #define PCMD19 __REG(0x40F00080 + 19 * 4)
1825 #define PCMD20 __REG(0x40F00080 + 20 * 4)
1826 #define PCMD21 __REG(0x40F00080 + 21 * 4)
1827 #define PCMD22 __REG(0x40F00080 + 22 * 4)
1828 #define PCMD23 __REG(0x40F00080 + 23 * 4)
1829 #define PCMD24 __REG(0x40F00080 + 24 * 4)
1830 #define PCMD25 __REG(0x40F00080 + 25 * 4)
1831 #define PCMD26 __REG(0x40F00080 + 26 * 4)
1832 #define PCMD27 __REG(0x40F00080 + 27 * 4)
1833 #define PCMD28 __REG(0x40F00080 + 28 * 4)
1834 #define PCMD29 __REG(0x40F00080 + 29 * 4)
1835 #define PCMD30 __REG(0x40F00080 + 30 * 4)
1836 #define PCMD31 __REG(0x40F00080 + 31 * 4)
1838 #define PCMD_MBC (1<<12)
1839 #define PCMD_DCE (1<<11)
1840 #define PCMD_LC (1<<10)
1841 /* FIXME: PCMD_SQC need be checked. */
1842 #define PCMD_SQC (3<<8) /* currently only bit 8 is changerable, */
1843 /* bit 9 should be 0 all day. */
1844 #define PVCR_VCSA (0x1<<14)
1845 #define PVCR_CommandDelay (0xf80)
1846 /* define MACRO for Power Manager General Configuration Register (PCFR) */
1847 #define PCFR_FVC (0x1 << 10)
1848 #define PCFR_PI2C_EN (0x1 << 6)
1850 #define PSSR_OTGPH (1 << 6) /* OTG Peripheral control Hold */
1851 #define PSSR_RDH (1 << 5) /* Read Disable Hold */
1852 #define PSSR_PH (1 << 4) /* Peripheral Control Hold */
1853 #define PSSR_VFS (1 << 2) /* VDD Fault Status */
1854 #define PSSR_BFS (1 << 1) /* Battery Fault Status */
1855 #define PSSR_SSS (1 << 0) /* Software Sleep Status */
1857 #define PCFR_DS (1 << 3) /* Deep Sleep Mode */
1858 #define PCFR_FS (1 << 2) /* Float Static Chip Selects */
1859 #define PCFR_FP (1 << 1) /* Float PCMCIA controls */
1860 #define PCFR_OPDE (1 << 0) /* 3.6864 MHz oscillator power-down enable */
1862 #define RCSR_GPR (1 << 3) /* GPIO Reset */
1863 #define RCSR_SMR (1 << 2) /* Sleep Mode */
1864 #define RCSR_WDR (1 << 1) /* Watchdog Reset */
1865 #define RCSR_HWR (1 << 0) /* Hardware Reset */
1867 #endif /* CONFIG_CPU_MONAHANS */
1870 * SSP Serial Port Registers
1872 #define SSCR0 __REG(0x41000000) /* SSP Control Register 0 */
1873 #define SSCR1 __REG(0x41000004) /* SSP Control Register 1 */
1874 #define SSSR __REG(0x41000008) /* SSP Status Register */
1875 #define SSITR __REG(0x4100000C) /* SSP Interrupt Test Register */
1876 #define SSDR __REG(0x41000010) /* (Write / Read) SSP Data Write Register/SSP Data Read Register */
1879 * MultiMediaCard (MMC) controller
1881 #define MMC_STRPCL __REG(0x41100000) /* Control to start and stop MMC clock */
1882 #define MMC_STAT __REG(0x41100004) /* MMC Status Register (read only) */
1883 #define MMC_CLKRT __REG(0x41100008) /* MMC clock rate */
1884 #define MMC_SPI __REG(0x4110000c) /* SPI mode control bits */
1885 #define MMC_CMDAT __REG(0x41100010) /* Command/response/data sequence control */
1886 #define MMC_RESTO __REG(0x41100014) /* Expected response time out */
1887 #define MMC_RDTO __REG(0x41100018) /* Expected data read time out */
1888 #define MMC_BLKLEN __REG(0x4110001c) /* Block length of data transaction */
1889 #define MMC_NOB __REG(0x41100020) /* Number of blocks, for block mode */
1890 #define MMC_PRTBUF __REG(0x41100024) /* Partial MMC_TXFIFO FIFO written */
1891 #define MMC_I_MASK __REG(0x41100028) /* Interrupt Mask */
1892 #define MMC_I_REG __REG(0x4110002c) /* Interrupt Register (read only) */
1893 #define MMC_CMD __REG(0x41100030) /* Index of current command */
1894 #define MMC_ARGH __REG(0x41100034) /* MSW part of the current command argument */
1895 #define MMC_ARGL __REG(0x41100038) /* LSW part of the current command argument */
1896 #define MMC_RES __REG(0x4110003c) /* Response FIFO (read only) */
1897 #define MMC_RXFIFO __REG(0x41100040) /* Receive FIFO (read only) */
1898 #define MMC_TXFIFO __REG(0x41100044) /* Transmit FIFO (write only) */
1904 #if defined(CONFIG_CPU_MONAHANS)
1905 #define ACCR __REG(0x41340000) /* Application Subsystem Clock Configuration Register */
1906 #define ACSR __REG(0x41340004) /* Application Subsystem Clock Status Register */
1907 #define AICSR __REG(0x41340008) /* Application Subsystem Interrupt Control/Status Register */
1908 #define CKENA __REG(0x4134000C) /* A Clock Enable Register */
1909 #define CKENB __REG(0x41340010) /* B Clock Enable Register */
1910 #define AC97_DIV __REG(0x41340014) /* AC97 clock divisor value register */
1912 #define ACCR_SMC_MASK 0x03800000 /* Static Memory Controller Frequency Select */
1913 #define ACCR_SRAM_MASK 0x000c0000 /* SRAM Controller Frequency Select */
1914 #define ACCR_FC_MASK 0x00030000 /* Frequency Change Frequency Select */
1915 #define ACCR_HSIO_MASK 0x0000c000 /* High Speed IO Frequency Select */
1916 #define ACCR_DDR_MASK 0x00003000 /* DDR Memory Controller Frequency Select */
1917 #define ACCR_XN_MASK 0x00000700 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1918 #define ACCR_XL_MASK 0x0000001f /* Crystal Frequency to Memory Frequency Multiplier */
1919 #define ACCR_XPDIS (1 << 31)
1920 #define ACCR_SPDIS (1 << 30)
1921 #define ACCR_13MEND1 (1 << 27)
1922 #define ACCR_D0CS (1 << 26)
1923 #define ACCR_13MEND2 (1 << 21)
1924 #define ACCR_PCCE (1 << 11)
1926 #define CKENA_30_MSL0 (1 << 30) /* MSL0 Interface Unit Clock Enable */
1927 #define CKENA_29_SSP4 (1 << 29) /* SSP3 Unit Clock Enable */
1928 #define CKENA_28_SSP3 (1 << 28) /* SSP2 Unit Clock Enable */
1929 #define CKENA_27_SSP2 (1 << 27) /* SSP1 Unit Clock Enable */
1930 #define CKENA_26_SSP1 (1 << 26) /* SSP0 Unit Clock Enable */
1931 #define CKENA_25_TSI (1 << 25) /* TSI Clock Enable */
1932 #define CKENA_24_AC97 (1 << 24) /* AC97 Unit Clock Enable */
1933 #define CKENA_23_STUART (1 << 23) /* STUART Unit Clock Enable */
1934 #define CKENA_22_FFUART (1 << 22) /* FFUART Unit Clock Enable */
1935 #define CKENA_21_BTUART (1 << 21) /* BTUART Unit Clock Enable */
1936 #define CKENA_20_UDC (1 << 20) /* UDC Clock Enable */
1937 #define CKENA_19_TPM (1 << 19) /* TPM Unit Clock Enable */
1938 #define CKENA_18_USIM1 (1 << 18) /* USIM1 Unit Clock Enable */
1939 #define CKENA_17_USIM0 (1 << 17) /* USIM0 Unit Clock Enable */
1940 #define CKENA_15_CIR (1 << 15) /* Consumer IR Clock Enable */
1941 #define CKENA_14_KEY (1 << 14) /* Keypad Controller Clock Enable */
1942 #define CKENA_13_MMC1 (1 << 13) /* MMC1 Clock Enable */
1943 #define CKENA_12_MMC0 (1 << 12) /* MMC0 Clock Enable */
1944 #define CKENA_11_FLASH (1 << 11) /* Boot ROM Clock Enable */
1945 #define CKENA_10_SRAM (1 << 10) /* SRAM Controller Clock Enable */
1946 #define CKENA_9_SMC (1 << 9) /* Static Memory Controller */
1947 #define CKENA_8_DMC (1 << 8) /* Dynamic Memory Controller */
1948 #define CKENA_7_GRAPHICS (1 << 7) /* 2D Graphics Clock Enable */
1949 #define CKENA_6_USBCLI (1 << 6) /* USB Client Unit Clock Enable */
1950 #define CKENA_4_NAND (1 << 4) /* NAND Flash Controller Clock Enable */
1951 #define CKENA_3_CAMERA (1 << 3) /* Camera Interface Clock Enable */
1952 #define CKENA_2_USBHOST (1 << 2) /* USB Host Unit Clock Enable */
1953 #define CKENA_1_LCD (1 << 1) /* LCD Unit Clock Enable */
1955 #define CKENB_9_SYSBUS2 (1 << 9) /* System bus 2 */
1956 #define CKENB_8_1WIRE (1 << 8) /* One Wire Interface Unit Clock Enable */
1957 #define CKENB_7_GPIO (1 << 7) /* GPIO Clock Enable */
1958 #define CKENB_6_IRQ (1 << 6) /* Interrupt Controller Clock Enable */
1959 #define CKENB_4_I2C (1 << 4) /* I2C Unit Clock Enable */
1960 #define CKENB_1_PWM1 (1 << 1) /* PWM2 & PWM3 Clock Enable */
1961 #define CKENB_0_PWM0 (1 << 0) /* PWM0 & PWM1 Clock Enable */
1963 #else /* if defined CONFIG_CPU_MONAHANS */
1965 #define CCCR __REG(0x41300000) /* Core Clock Configuration Register */
1966 #define CKEN __REG(0x41300004) /* Clock Enable Register */
1967 #define OSCC __REG(0x41300008) /* Oscillator Configuration Register */
1969 #define CCCR_N_MASK 0x0380 /* Run Mode Frequency to Turbo Mode Frequency Multiplier */
1970 #if !defined(CONFIG_PXA27X)
1971 #define CCCR_M_MASK 0x0060 /* Memory Frequency to Run Mode Frequency Multiplier */
1973 #define CCCR_L_MASK 0x001f /* Crystal Frequency to Memory Frequency Multiplier */
1975 #define CKEN24_CAMERA (1 << 24) /* Camera Interface Clock Enable */
1976 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
1977 #define CKEN22_MEMC (1 << 22) /* Memory Controller Clock Enable */
1978 #define CKEN21_MEMSTK (1 << 21) /* Memory Stick Host Controller */
1979 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
1980 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
1981 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
1982 #define CKEN17_MSL (1 << 17) /* MSL Unit Clock Enable */
1983 #define CKEN16_LCD (1 << 16) /* LCD Unit Clock Enable */
1984 #define CKEN15_PWRI2C (1 << 15) /* PWR I2C Unit Clock Enable */
1985 #define CKEN14_I2C (1 << 14) /* I2C Unit Clock Enable */
1986 #define CKEN13_FICP (1 << 13) /* FICP Unit Clock Enable */
1987 #define CKEN12_MMC (1 << 12) /* MMC Unit Clock Enable */
1988 #define CKEN11_USB (1 << 11) /* USB Unit Clock Enable */
1989 #if defined(CONFIG_PXA27X)
1990 #define CKEN10_USBHOST (1 << 10) /* USB Host Unit Clock Enable */
1991 #define CKEN24_CAMERA (1 << 24) /* Camera Unit Clock Enable */
1993 #define CKEN8_I2S (1 << 8) /* I2S Unit Clock Enable */
1994 #define CKEN7_BTUART (1 << 7) /* BTUART Unit Clock Enable */
1995 #define CKEN6_FFUART (1 << 6) /* FFUART Unit Clock Enable */
1996 #define CKEN5_STUART (1 << 5) /* STUART Unit Clock Enable */
1997 #define CKEN3_SSP (1 << 3) /* SSP Unit Clock Enable */
1998 #define CKEN2_AC97 (1 << 2) /* AC97 Unit Clock Enable */
1999 #define CKEN1_PWM1 (1 << 1) /* PWM1 Clock Enable */
2000 #define CKEN0_PWM0 (1 << 0) /* PWM0 Clock Enable */
2002 #define OSCC_OON (1 << 1) /* 32.768kHz OON (write-once only bit) */
2003 #define OSCC_OOK (1 << 0) /* 32.768kHz OOK (read-only bit) */
2005 #if !defined(CONFIG_PXA27X)
2006 #define CCCR_L09 (0x1F)
2007 #define CCCR_L27 (0x1)
2008 #define CCCR_L32 (0x2)
2009 #define CCCR_L36 (0x3)
2010 #define CCCR_L40 (0x4)
2011 #define CCCR_L45 (0x5)
2013 #define CCCR_M1 (0x1 << 5)
2014 #define CCCR_M2 (0x2 << 5)
2015 #define CCCR_M4 (0x3 << 5)
2017 #define CCCR_N10 (0x2 << 7)
2018 #define CCCR_N15 (0x3 << 7)
2019 #define CCCR_N20 (0x4 << 7)
2020 #define CCCR_N25 (0x5 << 7)
2021 #define CCCR_N30 (0x6 << 7)
2024 #endif /* CONFIG_CPU_MONAHANS */
2029 #define LCCR0 __REG(0x44000000) /* LCD Controller Control Register 0 */
2030 #define LCCR1 __REG(0x44000004) /* LCD Controller Control Register 1 */
2031 #define LCCR2 __REG(0x44000008) /* LCD Controller Control Register 2 */
2032 #define LCCR3 __REG(0x4400000C) /* LCD Controller Control Register 3 */
2033 #define DFBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
2034 #define DFBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
2035 #define LCSR0 __REG(0x44000038) /* LCD Controller Status Register */
2036 #define LCSR1 __REG(0x44000034) /* LCD Controller Status Register */
2037 #define LIIDR __REG(0x4400003C) /* LCD Controller Interrupt ID Register */
2038 #define TMEDRGBR __REG(0x44000040) /* TMED RGB Seed Register */
2039 #define TMEDCR __REG(0x44000044) /* TMED Control Register */
2041 #define FDADR0 __REG(0x44000200) /* DMA Channel 0 Frame Descriptor Address Register */
2042 #define FSADR0 __REG(0x44000204) /* DMA Channel 0 Frame Source Address Register */
2043 #define FIDR0 __REG(0x44000208) /* DMA Channel 0 Frame ID Register */
2044 #define LDCMD0 __REG(0x4400020C) /* DMA Channel 0 Command Register */
2045 #define FDADR1 __REG(0x44000210) /* DMA Channel 1 Frame Descriptor Address Register */
2046 #define FSADR1 __REG(0x44000214) /* DMA Channel 1 Frame Source Address Register */
2047 #define FIDR1 __REG(0x44000218) /* DMA Channel 1 Frame ID Register */
2048 #define LDCMD1 __REG(0x4400021C) /* DMA Channel 1 Command Register */
2050 #define LCCR0_ENB (1 << 0) /* LCD Controller enable */
2051 #define LCCR0_CMS (1 << 1) /* Color = 0, Monochrome = 1 */
2052 #define LCCR0_SDS (1 << 2) /* Single Panel = 0, Dual Panel = 1 */
2053 #define LCCR0_LDM (1 << 3) /* LCD Disable Done Mask */
2054 #define LCCR0_SFM (1 << 4) /* Start of frame mask */
2055 #define LCCR0_IUM (1 << 5) /* Input FIFO underrun mask */
2056 #define LCCR0_EFM (1 << 6) /* End of Frame mask */
2057 #define LCCR0_PAS (1 << 7) /* Passive = 0, Active = 1 */
2058 #define LCCR0_BLE (1 << 8) /* Little Endian = 0, Big Endian = 1 */
2059 #define LCCR0_DPD (1 << 9) /* Double Pixel mode, 4 pixel value = 0, 8 pixle values = 1 */
2060 #define LCCR0_DIS (1 << 10) /* LCD Disable */
2061 #define LCCR0_QDM (1 << 11) /* LCD Quick Disable mask */
2062 #define LCCR0_PDD (0xff << 12) /* Palette DMA request delay */
2063 #define LCCR0_PDD_S 12
2064 #define LCCR0_BM (1 << 20) /* Branch mask */
2065 #define LCCR0_OUM (1 << 21) /* Output FIFO underrun mask */
2066 #if defined(CONFIG_PXA27X)
2067 #define LCCR0_LCDT (1 << 22) /* LCD Panel Type */
2068 #define LCCR0_RDSTM (1 << 23) /* Read Status Interrupt Mask */
2069 #define LCCR0_CMDIM (1 << 24) /* Command Interrupt Mask */
2072 #define LCCR1_PPL Fld (10, 0) /* Pixels Per Line - 1 */
2073 #define LCCR1_DisWdth(Pixel) /* Display Width [1..800 pix.] */ \
2074 (((Pixel) - 1) << FShft (LCCR1_PPL))
2076 #define LCCR1_HSW Fld (6, 10) /* Horizontal Synchronization */
2077 #define LCCR1_HorSnchWdth(Tpix) /* Horizontal Synchronization */ \
2078 /* pulse Width [1..64 Tpix] */ \
2079 (((Tpix) - 1) << FShft (LCCR1_HSW))
2081 #define LCCR1_ELW Fld (8, 16) /* End-of-Line pixel clock Wait */
2082 /* count - 1 [Tpix] */
2083 #define LCCR1_EndLnDel(Tpix) /* End-of-Line Delay */ \
2084 /* [1..256 Tpix] */ \
2085 (((Tpix) - 1) << FShft (LCCR1_ELW))
2087 #define LCCR1_BLW Fld (8, 24) /* Beginning-of-Line pixel clock */
2088 /* Wait count - 1 [Tpix] */
2089 #define LCCR1_BegLnDel(Tpix) /* Beginning-of-Line Delay */ \
2090 /* [1..256 Tpix] */ \
2091 (((Tpix) - 1) << FShft (LCCR1_BLW))
2094 #define LCCR2_LPP Fld (10, 0) /* Line Per Panel - 1 */
2095 #define LCCR2_DisHght(Line) /* Display Height [1..1024 lines] */ \
2096 (((Line) - 1) << FShft (LCCR2_LPP))
2098 #define LCCR2_VSW Fld (6, 10) /* Vertical Synchronization pulse */
2099 /* Width - 1 [Tln] (L_FCLK) */
2100 #define LCCR2_VrtSnchWdth(Tln) /* Vertical Synchronization pulse */ \
2101 /* Width [1..64 Tln] */ \
2102 (((Tln) - 1) << FShft (LCCR2_VSW))
2104 #define LCCR2_EFW Fld (8, 16) /* End-of-Frame line clock Wait */
2106 #define LCCR2_EndFrmDel(Tln) /* End-of-Frame Delay */ \
2107 /* [0..255 Tln] */ \
2108 ((Tln) << FShft (LCCR2_EFW))
2110 #define LCCR2_BFW Fld (8, 24) /* Beginning-of-Frame line clock */
2111 /* Wait count [Tln] */
2112 #define LCCR2_BegFrmDel(Tln) /* Beginning-of-Frame Delay */ \
2113 /* [0..255 Tln] */ \
2114 ((Tln) << FShft (LCCR2_BFW))
2117 #define LCCR3_PCD (0xff) /* Pixel clock divisor */
2118 #define LCCR3_ACB (0xff << 8) /* AC Bias pin frequency */
2119 #define LCCR3_ACB_S 8
2122 #define LCCR3_API (0xf << 16) /* AC Bias pin trasitions per interrupt */
2123 #define LCCR3_API_S 16
2124 #define LCCR3_VSP (1 << 20) /* vertical sync polarity */
2125 #define LCCR3_HSP (1 << 21) /* horizontal sync polarity */
2126 #define LCCR3_PCP (1 << 22) /* pixel clock polarity */
2127 #define LCCR3_OEP (1 << 23) /* output enable polarity */
2129 #define LCCR3_BPP (7 << 24) /* bits per pixel */
2130 #define LCCR3_BPP_S 24
2132 #define LCCR3_DPC (1 << 27) /* double pixel clock mode */
2134 #define LCCR3_PDFOR_0 (0 << 30)
2135 #define LCCR3_PDFOR_1 (1 << 30)
2136 #define LCCR3_PDFOR_2 (2 << 30)
2137 #define LCCR3_PDFOR_3 (3 << 30)
2140 #define LCCR3_PCD Fld (8, 0) /* Pixel Clock Divisor */
2141 #define LCCR3_PixClkDiv(Div) /* Pixel Clock Divisor */ \
2142 (((Div) << FShft (LCCR3_PCD)))
2145 #define LCCR3_BPP Fld (3, 24) /* Bit Per Pixel */
2146 #define LCCR3_Bpp(Bpp) /* Bit Per Pixel */ \
2147 ((((Bpp&0x7) << FShft (LCCR3_BPP)))|(((Bpp&0x8)<<26)))
2149 #define LCCR3_ACB Fld (8, 8) /* AC Bias */
2150 #define LCCR3_Acb(Acb) /* BAC Bias */ \
2151 (((Acb) << FShft (LCCR3_ACB)))
2153 #define LCCR3_HorSnchH (LCCR3_HSP*0) /* Horizontal Synchronization */
2154 /* pulse active High */
2155 #define LCCR3_HorSnchL (LCCR3_HSP*1) /* Horizontal Synchronization */
2157 #define LCCR3_VrtSnchH (LCCR3_VSP*0) /* Vertical Synchronization pulse */
2159 #define LCCR3_VrtSnchL (LCCR3_VSP*1) /* Vertical Synchronization pulse */
2162 #define LCSR0_LDD (1 << 0) /* LCD Disable Done */
2163 #define LCSR0_SOF (1 << 1) /* Start of frame */
2164 #define LCSR0_BER (1 << 2) /* Bus error */
2165 #define LCSR0_ABC (1 << 3) /* AC Bias count */
2166 #define LCSR0_IUL (1 << 4) /* input FIFO underrun Lower panel */
2167 #define LCSR0_IUU (1 << 5) /* input FIFO underrun Upper panel */
2168 #define LCSR0_OU (1 << 6) /* output FIFO underrun */
2169 #define LCSR0_QD (1 << 7) /* quick disable */
2170 #define LCSR0_EOF0 (1 << 8) /* end of frame */
2171 #define LCSR0_BS (1 << 9) /* branch status */
2172 #define LCSR0_SINT (1 << 10) /* subsequent interrupt */
2174 #define LCSR1_SOF1 (1 << 0)
2175 #define LCSR1_SOF2 (1 << 1)
2176 #define LCSR1_SOF3 (1 << 2)
2177 #define LCSR1_SOF4 (1 << 3)
2178 #define LCSR1_SOF5 (1 << 4)
2179 #define LCSR1_SOF6 (1 << 5)
2181 #define LCSR1_EOF1 (1 << 8)
2182 #define LCSR1_EOF2 (1 << 9)
2183 #define LCSR1_EOF3 (1 << 10)
2184 #define LCSR1_EOF4 (1 << 11)
2185 #define LCSR1_EOF5 (1 << 12)
2186 #define LCSR1_EOF6 (1 << 13)
2188 #define LCSR1_BS1 (1 << 16)
2189 #define LCSR1_BS2 (1 << 17)
2190 #define LCSR1_BS3 (1 << 18)
2191 #define LCSR1_BS4 (1 << 19)
2192 #define LCSR1_BS5 (1 << 20)
2193 #define LCSR1_BS6 (1 << 21)
2195 #define LCSR1_IU2 (1 << 25)
2196 #define LCSR1_IU3 (1 << 26)
2197 #define LCSR1_IU4 (1 << 27)
2198 #define LCSR1_IU5 (1 << 28)
2199 #define LCSR1_IU6 (1 << 29)
2201 #define LDCMD_PAL (1 << 26) /* instructs DMA to load palette buffer */
2202 #if defined(CONFIG_PXA27X)
2203 #define LDCMD_SOFINT (1 << 22)
2204 #define LDCMD_EOFINT (1 << 21)
2211 #ifdef CONFIG_CPU_MONAHANS
2212 /* Static Memory Controller Registers */
2213 #define MSC0 __REG_2(0x4A000008) /* Static Memory Control Register 0 */
2214 #define MSC1 __REG_2(0x4A00000C) /* Static Memory Control Register 1 */
2215 #define MECR __REG_2(0x4A000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2216 #define SXCNFG __REG_2(0x4A00001C) /* Synchronous Static Memory Control Register */
2217 #define MCMEM0 __REG_2(0x4A000028) /* Card interface Common Memory Space Socket 0 Timing */
2218 #define MCATT0 __REG_2(0x4A000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2219 #define MCIO0 __REG_2(0x4A000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2220 #define MEMCLKCFG __REG_2(0x4A000068) /* SCLK speed configuration */
2221 #define CSADRCFG0 __REG_2(0x4A000080) /* Address Configuration for chip select 0 */
2222 #define CSADRCFG1 __REG_2(0x4A000084) /* Address Configuration for chip select 1 */
2223 #define CSADRCFG2 __REG_2(0x4A000088) /* Address Configuration for chip select 2 */
2224 #define CSADRCFG3 __REG_2(0x4A00008C) /* Address Configuration for chip select 3 */
2225 #define CSADRCFG_P __REG_2(0x4A000090) /* Address Configuration for pcmcia card interface */
2226 #define CSMSADRCFG __REG_2(0x4A0000A0) /* Master Address Configuration Register */
2227 #define CLK_RET_DEL __REG_2(0x4A0000B0) /* Delay line and mux selects for return data latching for sync. flash */
2228 #define ADV_RET_DEL __REG_2(0x4A0000B4) /* Delay line and mux selects for return data latching for sync. flash */
2230 /* Dynamic Memory Controller Registers */
2231 #define MDCNFG __REG_2(0x48100000) /* SDRAM Configuration Register 0 */
2232 #define MDREFR __REG_2(0x48100004) /* SDRAM Refresh Control Register */
2233 #define FLYCNFG __REG_2(0x48100020) /* Fly-by DMA DVAL[1:0] polarities */
2234 #define MDMRS __REG_2(0x48100040) /* MRS value to be written to SDRAM */
2235 #define DDR_SCAL __REG_2(0x48100050) /* Software Delay Line Calibration/Configuration for external DDR memory. */
2236 #define DDR_HCAL __REG_2(0x48100060) /* Hardware Delay Line Calibration/Configuration for external DDR memory. */
2237 #define DDR_WCAL __REG_2(0x48100068) /* DDR Write Strobe Calibration Register */
2238 #define DMCIER __REG_2(0x48100070) /* Dynamic MC Interrupt Enable Register. */
2239 #define DMCISR __REG_2(0x48100078) /* Dynamic MC Interrupt Status Register. */
2240 #define DDR_DLS __REG_2(0x48100080) /* DDR Delay Line Value Status register for external DDR memory. */
2241 #define EMPI __REG_2(0x48100090) /* EMPI Control Register */
2242 #define RCOMP __REG_2(0x48100100)
2243 #define PAD_MA __REG_2(0x48100110)
2244 #define PAD_MDMSB __REG_2(0x48100114)
2245 #define PAD_MDLSB __REG_2(0x48100118)
2246 #define PAD_DMEM __REG_2(0x4810011c)
2247 #define PAD_SDCLK __REG_2(0x48100120)
2248 #define PAD_SDCS __REG_2(0x48100124)
2249 #define PAD_SMEM __REG_2(0x48100128)
2250 #define PAD_SCLK __REG_2(0x4810012C)
2251 #define TAI __REG_2(0x48100F00) /* TAI Tavor Address Isolation Register */
2253 /* Some frequently used bits */
2254 #define MDCNFG_DMAP 0x80000000 /* SDRAM 1GB Memory Map Enable */
2255 #define MDCNFG_DMCEN 0x40000000 /* Enable Dynamic Memory Controller */
2256 #define MDCNFG_HWFREQ 0x20000000 /* Hardware Frequency Change Calibration */
2257 #define MDCNFG_DTYPE 0x400 /* SDRAM Type: 1=DDR SDRAM */
2259 #define MDCNFG_DTC_0 0x0 /* Timing Category of SDRAM */
2260 #define MDCNFG_DTC_1 0x100
2261 #define MDCNFG_DTC_2 0x200
2262 #define MDCNFG_DTC_3 0x300
2264 #define MDCNFG_DRAC_12 0x0 /* Number of Row Access Bits */
2265 #define MDCNFG_DRAC_13 0x20
2266 #define MDCNFG_DRAC_14 0x40
2268 #define MDCNFG_DCAC_9 0x0 /* Number of Column Acess Bits */
2269 #define MDCNFG_DCAC_10 0x08
2270 #define MDCNFG_DCAC_11 0x10
2272 #define MDCNFG_DBW_16 0x4 /* SDRAM Data Bus width 16bit */
2273 #define MDCNFG_DCSE1 0x2 /* SDRAM CS 1 Enable */
2274 #define MDCNFG_DCSE0 0x1 /* SDRAM CS 0 Enable */
2277 /* Data Flash Controller Registers */
2279 #define NDCR __REG(0x43100000) /* Data Flash Control register */
2280 #define NDTR0CS0 __REG(0x43100004) /* Data Controller Timing Parameter 0 Register for ND_nCS0 */
2281 /* #define NDTR0CS1 __REG(0x43100008) /\* Data Controller Timing Parameter 0 Register for ND_nCS1 *\/ */
2282 #define NDTR1CS0 __REG(0x4310000C) /* Data Controller Timing Parameter 1 Register for ND_nCS0 */
2283 /* #define NDTR1CS1 __REG(0x43100010) /\* Data Controller Timing Parameter 1 Register for ND_nCS1 *\/ */
2284 #define NDSR __REG(0x43100014) /* Data Controller Status Register */
2285 #define NDPCR __REG(0x43100018) /* Data Controller Page Count Register */
2286 #define NDBDR0 __REG(0x4310001C) /* Data Controller Bad Block Register 0 */
2287 #define NDBDR1 __REG(0x43100020) /* Data Controller Bad Block Register 1 */
2288 #define NDDB __REG(0x43100040) /* Data Controller Data Buffer */
2289 #define NDCB0 __REG(0x43100048) /* Data Controller Command Buffer0 */
2290 #define NDCB1 __REG(0x4310004C) /* Data Controller Command Buffer1 */
2291 #define NDCB2 __REG(0x43100050) /* Data Controller Command Buffer2 */
2293 #define NDCR_SPARE_EN (0x1<<31)
2294 #define NDCR_ECC_EN (0x1<<30)
2295 #define NDCR_DMA_EN (0x1<<29)
2296 #define NDCR_ND_RUN (0x1<<28)
2297 #define NDCR_DWIDTH_C (0x1<<27)
2298 #define NDCR_DWIDTH_M (0x1<<26)
2299 #define NDCR_PAGE_SZ (0x3<<24)
2300 #define NDCR_NCSX (0x1<<23)
2301 #define NDCR_ND_STOP (0x1<<22)
2303 * #define NDCR_ND_MODE (0x3<<21)
2304 * #define NDCR_NAND_MODE 0x0 */
2305 #define NDCR_CLR_PG_CNT (0x1<<20)
2306 #define NDCR_CLR_ECC (0x1<<19)
2307 #define NDCR_RD_ID_CNT (0x7<<16)
2308 #define NDCR_RA_START (0x1<<15)
2309 #define NDCR_PG_PER_BLK (0x1<<14)
2310 #define NDCR_ND_ARB_EN (0x1<<12)
2311 #define NDCR_RDYM (0x1<<11)
2312 #define NDCR_CS0_PAGEDM (0x1<<10)
2313 #define NDCR_CS1_PAGEDM (0x1<<9)
2314 #define NDCR_CS0_CMDDM (0x1<<8)
2315 #define NDCR_CS1_CMDDM (0x1<<7)
2316 #define NDCR_CS0_BBDM (0x1<<6)
2317 #define NDCR_CS1_BBDM (0x1<<5)
2318 #define NDCR_DBERRM (0x1<<4)
2319 #define NDCR_SBERRM (0x1<<3)
2320 #define NDCR_WRDREQM (0x1<<2)
2321 #define NDCR_RDDREQM (0x1<<1)
2322 #define NDCR_WRCMDREQM (0x1)
2324 #define NDSR_RDY (0x1<<11)
2325 #define NDSR_CS0_PAGED (0x1<<10)
2326 #define NDSR_CS1_PAGED (0x1<<9)
2327 #define NDSR_CS0_CMDD (0x1<<8)
2328 #define NDSR_CS1_CMDD (0x1<<7)
2329 #define NDSR_CS0_BBD (0x1<<6)
2330 #define NDSR_CS1_BBD (0x1<<5)
2331 #define NDSR_DBERR (0x1<<4)
2332 #define NDSR_SBERR (0x1<<3)
2333 #define NDSR_WRDREQ (0x1<<2)
2334 #define NDSR_RDDREQ (0x1<<1)
2335 #define NDSR_WRCMDREQ (0x1)
2337 #define NDCB0_AUTO_RS (0x1<<25)
2338 #define NDCB0_CSEL (0x1<<24)
2339 #define NDCB0_CMD_TYPE (0x7<<21)
2340 #define NDCB0_NC (0x1<<20)
2341 #define NDCB0_DBC (0x1<<19)
2342 #define NDCB0_ADDR_CYC (0x7<<16)
2343 #define NDCB0_CMD2 (0xff<<8)
2344 #define NDCB0_CMD1 (0xff)
2345 #define MCMEM(s) MCMEM0
2346 #define MCATT(s) MCATT0
2347 #define MCIO(s) MCIO0
2348 #define MECR_CIT (1 << 1)/* Card Is There: 0 -> no card, 1 -> card inserted */
2350 /* Maximum values for NAND Interface Timing Registers in DFC clock
2352 #define DFC_MAX_tCH 7
2353 #define DFC_MAX_tCS 7
2354 #define DFC_MAX_tWH 7
2355 #define DFC_MAX_tWP 7
2356 #define DFC_MAX_tRH 7
2357 #define DFC_MAX_tRP 15
2358 #define DFC_MAX_tR 65535
2359 #define DFC_MAX_tWHR 15
2360 #define DFC_MAX_tAR 15
2362 #define DFC_CLOCK 104 /* DFC Clock is 104 MHz */
2363 #define DFC_CLK_PER_US DFC_CLOCK/1000 /* clock period in ns */
2365 #else /* CONFIG_CPU_MONAHANS */
2367 #define MEMC_BASE __REG(0x48000000) /* Base of Memory Controller */
2368 #define MDCNFG_OFFSET 0x0
2369 #define MDREFR_OFFSET 0x4
2370 #define MSC0_OFFSET 0x8
2371 #define MSC1_OFFSET 0xC
2372 #define MSC2_OFFSET 0x10
2373 #define MECR_OFFSET 0x14
2374 #define SXLCR_OFFSET 0x18
2375 #define SXCNFG_OFFSET 0x1C
2376 #define FLYCNFG_OFFSET 0x20
2377 #define SXMRS_OFFSET 0x24
2378 #define MCMEM0_OFFSET 0x28
2379 #define MCMEM1_OFFSET 0x2C
2380 #define MCATT0_OFFSET 0x30
2381 #define MCATT1_OFFSET 0x34
2382 #define MCIO0_OFFSET 0x38
2383 #define MCIO1_OFFSET 0x3C
2384 #define MDMRS_OFFSET 0x40
2386 #define MDCNFG __REG(0x48000000) /* SDRAM Configuration Register 0 */
2387 #define MDCNFG_DE0 0x00000001
2388 #define MDCNFG_DE1 0x00000002
2389 #define MDCNFG_DE2 0x00010000
2390 #define MDCNFG_DE3 0x00020000
2391 #define MDCNFG_DWID0 0x00000004
2393 #define MDREFR __REG(0x48000004) /* SDRAM Refresh Control Register */
2394 #define MSC0 __REG(0x48000008) /* Static Memory Control Register 0 */
2395 #define MSC1 __REG(0x4800000C) /* Static Memory Control Register 1 */
2396 #define MSC2 __REG(0x48000010) /* Static Memory Control Register 2 */
2397 #define MECR __REG(0x48000014) /* Expansion Memory (PCMCIA/Compact Flash) Bus Configuration */
2398 #define SXLCR __REG(0x48000018) /* LCR value to be written to SDRAM-Timing Synchronous Flash */
2399 #define SXCNFG __REG(0x4800001C) /* Synchronous Static Memory Control Register */
2400 #define SXMRS __REG(0x48000024) /* MRS value to be written to Synchronous Flash or SMROM */
2401 #define MCMEM0 __REG(0x48000028) /* Card interface Common Memory Space Socket 0 Timing */
2402 #define MCMEM1 __REG(0x4800002C) /* Card interface Common Memory Space Socket 1 Timing */
2403 #define MCATT0 __REG(0x48000030) /* Card interface Attribute Space Socket 0 Timing Configuration */
2404 #define MCATT1 __REG(0x48000034) /* Card interface Attribute Space Socket 1 Timing Configuration */
2405 #define MCIO0 __REG(0x48000038) /* Card interface I/O Space Socket 0 Timing Configuration */
2406 #define MCIO1 __REG(0x4800003C) /* Card interface I/O Space Socket 1 Timing Configuration */
2407 #define MDMRS __REG(0x48000040) /* MRS value to be written to SDRAM */
2408 #define BOOT_DEF __REG(0x48000044) /* Read-Only Boot-Time Register. Contains BOOT_SEL and PKG_SEL */
2410 #define MDREFR_K2FREE (1 << 25) /* SDRAM Free-Running Control */
2411 #define MDREFR_K1FREE (1 << 24) /* SDRAM Free-Running Control */
2412 #define MDREFR_K0FREE (1 << 23) /* SDRAM Free-Running Control */
2413 #define MDREFR_SLFRSH (1 << 22) /* SDRAM Self-Refresh Control/Status */
2414 #define MDREFR_APD (1 << 20) /* SDRAM/SSRAM Auto-Power-Down Enable */
2415 #define MDREFR_K2DB2 (1 << 19) /* SDCLK2 Divide by 2 Control/Status */
2416 #define MDREFR_K2RUN (1 << 18) /* SDCLK2 Run Control/Status */
2417 #define MDREFR_K1DB2 (1 << 17) /* SDCLK1 Divide by 2 Control/Status */
2418 #define MDREFR_K1RUN (1 << 16) /* SDCLK1 Run Control/Status */
2419 #define MDREFR_E1PIN (1 << 15) /* SDCKE1 Level Control/Status */
2420 #define MDREFR_K0DB2 (1 << 14) /* SDCLK0 Divide by 2 Control/Status */
2421 #define MDREFR_K0RUN (1 << 13) /* SDCLK0 Run Control/Status */
2422 #define MDREFR_E0PIN (1 << 12) /* SDCKE0 Level Control/Status */
2424 #if defined(CONFIG_PXA27X)
2426 #define ARB_CNTRL __REG(0x48000048) /* Arbiter Control Register */
2428 #define ARB_DMA_SLV_PARK (1<<31) /* Be parked with DMA slave when idle */
2429 #define ARB_CI_PARK (1<<30) /* Be parked with Camera Interface when idle */
2430 #define ARB_EX_MEM_PARK (1<<29) /* Be parked with external MEMC when idle */
2431 #define ARB_INT_MEM_PARK (1<<28) /* Be parked with internal MEMC when idle */
2432 #define ARB_USB_PARK (1<<27) /* Be parked with USB when idle */
2433 #define ARB_LCD_PARK (1<<26) /* Be parked with LCD when idle */
2434 #define ARB_DMA_PARK (1<<25) /* Be parked with DMA when idle */
2435 #define ARB_CORE_PARK (1<<24) /* Be parked with core when idle */
2436 #define ARB_LOCK_FLAG (1<<23) /* Only Locking masters gain access to the bus */
2438 #endif /* CONFIG_CPU_MONAHANS */
2440 /* Interrupt Controller */
2442 #define ICIP2 __REG(0x40D0009C) /* Interrupt Controller IRQ Pending Register 2 */
2443 #define ICMR2 __REG(0x40D000A0) /* Interrupt Controller Mask Register 2 */
2444 #define ICLR2 __REG(0x40D000A4) /* Interrupt Controller Level Register 2 */
2445 #define ICFP2 __REG(0x40D000A8) /* Interrupt Controller FIQ Pending Register 2 */
2446 #define ICPR2 __REG(0x40D000AC) /* Interrupt Controller Pending Register 2 */
2448 /* General Purpose I/O */
2450 #define GAFR3_L __REG(0x40E0006C) /* GPIO Alternate Function Select Register GPIO<111:96> */
2451 #define GAFR3_U __REG(0x40E00070) /* GPIO Alternate Function Select Register GPIO<127:112> */
2452 #define GPLR3 __REG(0x40E00100) /* GPIO Pin-Level Register GPIO<127:96> */
2453 #define GPDR3 __REG(0x40E0010C) /* GPIO Pin Direction Register GPIO<127:96> */
2454 #define GPSR3 __REG(0x40E00118) /* GPIO Pin Output Set Register GPIO<127:96> */
2455 #define GPCR3 __REG(0x40E00124) /* GPIO Pin Output Clear Register GPIO <127:96> */
2456 #define GRER3 __REG(0x40E00130) /* GPIO Rising-Edge Detect Register GPIO<127:96> */
2457 #define GFER3 __REG(0x40E0013C) /* GPIO Falling-Edge Detect Register GPIO<31:0> */
2458 #define GEDR3 __REG(0x40E00148) /* GPIO Edge Detect Status Register GPIO<127:96> */
2462 #define CCSR __REG(0x4130000C) /* Core Clock Status Register */
2464 #define CKEN23_SSP1 (1 << 23) /* SSP1 Unit Clock Enable */
2465 #define CKEN22_MEMC (1 << 22) /* Memory Controler */
2466 #define CKEN21_MSHC (1 << 21) /* Memery Stick Host Controller */
2467 #define CKEN20_IM (1 << 20) /* Internal Memory Clock Enable */
2468 #define CKEN19_KEYPAD (1 << 19) /* Keypad Interface Clock Enable */
2469 #define CKEN18_USIM (1 << 18) /* USIM Unit Clock Enable */
2470 #define CKEN17_MSL (1 << 17) /* MSL Interface Unit Clock Enable */
2471 #define CKEN15_PWR_I2C (1 << 15) /* PWR_I2C Unit Clock Enable */
2472 #define CKEN9_OST (1 << 9) /* OS Timer Unit Clock Enable */
2473 #define CKEN4_SSP3 (1 << 4) /* SSP3 Unit Clock Enable */
2475 /* Memory controller */
2477 #define MDREFR_K0DB4 (1 << 29) /* SDCLK[0] divide by 4 */
2480 #define LCCR4 __REG(0x44000010) /* LCD Controller Control Register 4 */
2481 #define LCCR5 __REG(0x44000014) /* LCD Controller Control Register 5 */
2482 #define FBR0 __REG(0x44000020) /* DMA Channel 0 Frame Branch Register */
2483 #define FBR1 __REG(0x44000024) /* DMA Channel 1 Frame Branch Register */
2484 #define FBR2 __REG(0x44000028) /* DMA Channel 2 Frame Branch Register */
2485 #define FBR3 __REG(0x4400002C) /* DMA Channel 3 Frame Branch Register */
2486 #define FBR4 __REG(0x44000030) /* DMA Channel 4 Frame Branch Register */
2487 #define FDADR2 __REG(0x44000220) /* DMA Channel 2 Frame Descriptor Address Register */
2488 #define FSADR2 __REG(0x44000224) /* DMA Channel 2 Frame Source Address Register */
2489 #define FIDR2 __REG(0x44000228) /* DMA Channel 2 Frame ID Register */
2490 #define LDCMD2 __REG(0x4400022C) /* DMA Channel 2 Command Register */
2491 #define FDADR3 __REG(0x44000230) /* DMA Channel 3 Frame Descriptor Address Register */
2492 #define FSADR3 __REG(0x44000234) /* DMA Channel 3 Frame Source Address Register */
2493 #define FIDR3 __REG(0x44000238) /* DMA Channel 3 Frame ID Register */
2494 #define LDCMD3 __REG(0x4400023C) /* DMA Channel 3 Command Register */
2495 #define FDADR4 __REG(0x44000240) /* DMA Channel 4 Frame Descriptor Address Register */
2496 #define FSADR4 __REG(0x44000244) /* DMA Channel 4 Frame Source Address Register */
2497 #define FIDR4 __REG(0x44000248) /* DMA Channel 4 Frame ID Register */
2498 #define LDCMD4 __REG(0x4400024C) /* DMA Channel 4 Command Register */
2499 #define FDADR5 __REG(0x44000250) /* DMA Channel 5 Frame Descriptor Address Register */
2500 #define FSADR5 __REG(0x44000254) /* DMA Channel 5 Frame Source Address Register */
2501 #define FIDR5 __REG(0x44000258) /* DMA Channel 5 Frame ID Register */
2502 #define LDCMD5 __REG(0x4400025C) /* DMA Channel 5 Command Register */
2504 #define OVL1C1 __REG(0x44000050) /* Overlay 1 Control Register 1 */
2505 #define OVL1C2 __REG(0x44000060) /* Overlay 1 Control Register 2 */
2506 #define OVL2C1 __REG(0x44000070) /* Overlay 2 Control Register 1 */
2507 #define OVL2C2 __REG(0x44000080) /* Overlay 2 Control Register 2 */
2508 #define CCR __REG(0x44000090) /* Cursor Control Register */
2510 #define FBR5 __REG(0x44000110) /* DMA Channel 5 Frame Branch Register */
2511 #define FBR6 __REG(0x44000114) /* DMA Channel 6 Frame Branch Register */
2513 #define LCCR0_LDDALT (1<<26) /* LDD Alternate mapping bit when base pixel is RGBT16 */
2514 #define LCCR0_OUC (1<<25) /* Overlay Underlay Control Bit */
2516 #define LCCR5_SOFM1 (1<<0) /* Start Of Frame Mask for Overlay 1 (channel 1) */
2517 #define LCCR5_SOFM2 (1<<1) /* Start Of Frame Mask for Overlay 2 (channel 2) */
2518 #define LCCR5_SOFM3 (1<<2) /* Start Of Frame Mask for Overlay 2 (channel 3) */
2519 #define LCCR5_SOFM4 (1<<3) /* Start Of Frame Mask for Overlay 2 (channel 4) */
2520 #define LCCR5_SOFM5 (1<<4) /* Start Of Frame Mask for cursor (channel 5) */
2521 #define LCCR5_SOFM6 (1<<5) /* Start Of Frame Mask for command data (channel 6) */
2523 #define LCCR5_EOFM1 (1<<8) /* End Of Frame Mask for Overlay 1 (channel 1) */
2524 #define LCCR5_EOFM2 (1<<9) /* End Of Frame Mask for Overlay 2 (channel 2) */
2525 #define LCCR5_EOFM3 (1<<10) /* End Of Frame Mask for Overlay 2 (channel 3) */
2526 #define LCCR5_EOFM4 (1<<11) /* End Of Frame Mask for Overlay 2 (channel 4) */
2527 #define LCCR5_EOFM5 (1<<12) /* End Of Frame Mask for cursor (channel 5) */
2528 #define LCCR5_EOFM6 (1<<13) /* End Of Frame Mask for command data (channel 6) */
2530 #define LCCR5_BSM1 (1<<16) /* Branch mask for Overlay 1 (channel 1) */
2531 #define LCCR5_BSM2 (1<<17) /* Branch mask for Overlay 2 (channel 2) */
2532 #define LCCR5_BSM3 (1<<18) /* Branch mask for Overlay 2 (channel 3) */
2533 #define LCCR5_BSM4 (1<<19) /* Branch mask for Overlay 2 (channel 4) */
2534 #define LCCR5_BSM5 (1<<20) /* Branch mask for cursor (channel 5) */
2535 #define LCCR5_BSM6 (1<<21) /* Branch mask for data command (channel 6) */
2537 #define LCCR5_IUM1 (1<<24) /* Input FIFO Underrun Mask for Overlay 1 */
2538 #define LCCR5_IUM2 (1<<25) /* Input FIFO Underrun Mask for Overlay 2 */
2539 #define LCCR5_IUM3 (1<<26) /* Input FIFO Underrun Mask for Overlay 2 */
2540 #define LCCR5_IUM4 (1<<27) /* Input FIFO Underrun Mask for Overlay 2 */
2541 #define LCCR5_IUM5 (1<<28) /* Input FIFO Underrun Mask for cursor */
2542 #define LCCR5_IUM6 (1<<29) /* Input FIFO Underrun Mask for data command */
2544 #define OVL1C1_O1EN (1<<31) /* Enable bit for Overlay 1 */
2545 #define OVL2C1_O2EN (1<<31) /* Enable bit for Overlay 2 */
2546 #define CCR_CEN (1<<31) /* Enable bit for Cursor */
2548 /* Keypad controller */
2550 #define KPC __REG(0x41500000) /* Keypad Interface Control register */
2551 #define KPDK __REG(0x41500008) /* Keypad Interface Direct Key register */
2552 #define KPREC __REG(0x41500010) /* Keypad Intefcace Rotary Encoder register */
2553 #define KPMK __REG(0x41500018) /* Keypad Intefcace Matrix Key register */
2554 #define KPAS __REG(0x41500020) /* Keypad Interface Automatic Scan register */
2555 #define KPASMKP0 __REG(0x41500028) /* Keypad Interface Automatic Scan Multiple Key Presser register 0 */
2556 #define KPASMKP1 __REG(0x41500030) /* Keypad Interface Automatic Scan Multiple Key Presser register 1 */
2557 #define KPASMKP2 __REG(0x41500038) /* Keypad Interface Automatic Scan Multiple Key Presser register 2 */
2558 #define KPASMKP3 __REG(0x41500040) /* Keypad Interface Automatic Scan Multiple Key Presser register 3 */
2559 #define KPKDI __REG(0x41500048) /* Keypad Interface Key Debounce Interval register */
2561 #define KPC_AS (0x1 << 30) /* Automatic Scan bit */
2562 #define KPC_ASACT (0x1 << 29) /* Automatic Scan on Activity */
2563 #define KPC_MI (0x1 << 22) /* Matrix interrupt bit */
2564 #define KPC_IMKP (0x1 << 21) /* Ignore Multiple Key Press */
2565 #define KPC_MS7 (0x1 << 20) /* Matrix scan line 7 */
2566 #define KPC_MS6 (0x1 << 19) /* Matrix scan line 6 */
2567 #define KPC_MS5 (0x1 << 18) /* Matrix scan line 5 */
2568 #define KPC_MS4 (0x1 << 17) /* Matrix scan line 4 */
2569 #define KPC_MS3 (0x1 << 16) /* Matrix scan line 3 */
2570 #define KPC_MS2 (0x1 << 15) /* Matrix scan line 2 */
2571 #define KPC_MS1 (0x1 << 14) /* Matrix scan line 1 */
2572 #define KPC_MS0 (0x1 << 13) /* Matrix scan line 0 */
2573 #define KPC_ME (0x1 << 12) /* Matrix Keypad Enable */
2574 #define KPC_MIE (0x1 << 11) /* Matrix Interrupt Enable */
2575 #define KPC_DK_DEB_SEL (0x1 << 9) /* Direct Key Debounce select */
2576 #define KPC_DI (0x1 << 5) /* Direct key interrupt bit */
2577 #define KPC_DEE0 (0x1 << 2) /* Rotary Encoder 0 Enable */
2578 #define KPC_DE (0x1 << 1) /* Direct Keypad Enable */
2579 #define KPC_DIE (0x1 << 0) /* Direct Keypad interrupt Enable */
2581 #define KPDK_DKP (0x1 << 31)
2582 #define KPDK_DK7 (0x1 << 7)
2583 #define KPDK_DK6 (0x1 << 6)
2584 #define KPDK_DK5 (0x1 << 5)
2585 #define KPDK_DK4 (0x1 << 4)
2586 #define KPDK_DK3 (0x1 << 3)
2587 #define KPDK_DK2 (0x1 << 2)
2588 #define KPDK_DK1 (0x1 << 1)
2589 #define KPDK_DK0 (0x1 << 0)
2591 #define KPREC_OF1 (0x1 << 31)
2592 #define kPREC_UF1 (0x1 << 30)
2593 #define KPREC_OF0 (0x1 << 15)
2594 #define KPREC_UF0 (0x1 << 14)
2596 #define KPMK_MKP (0x1 << 31)
2597 #define KPAS_SO (0x1 << 31)
2598 #define KPASMKPx_SO (0x1 << 31)
2600 #define GPIO113_BIT (1 << 17)/* GPIO113 in GPSR, GPCR, bit 17 */
2601 #define PSLR __REG(0x40F00034)
2602 #define PSTR __REG(0x40F00038) /* Power Manager Standby Configuration Reg */
2603 #define PSNR __REG(0x40F0003C) /* Power Manager Sense Configuration Reg */
2604 #define PVCR __REG(0x40F00040) /* Power Manager Voltage Change Control Reg */
2605 #define PKWR __REG(0x40F00050) /* Power Manager KB Wake-Up Enable Reg */
2606 #define PKSR __REG(0x40F00054) /* Power Manager KB Level-Detect Status Reg */
2607 #define OSMR4 __REG(0x40A00080) /* */
2608 #define OSCR4 __REG(0x40A00040) /* OS Timer Counter Register */
2609 #define OMCR4 __REG(0x40A000C0) /* */
2611 #endif /* CONFIG_PXA27X */
2613 #endif /* _PXA_REGS_H_ */
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