arch/arm/include/asm/arch-socfpga/freeze_controller.h

   1 /*
   2  *  Copyright (C) 2013 Altera Corporation <www.altera.com>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef _FREEZE_CONTROLLER_H_
   8 #define _FREEZE_CONTROLLER_H_
   9
  10 struct socfpga_freeze_controller {
  11         u32     vioctrl;
  12         u32     padding[3];
  13         u32     hioctrl;
  14         u32     src;
  15         u32     hwctrl;
  16 };
  17
  18 #define FREEZE_CHANNEL_NUM              (4)
  19
  20 typedef enum {
  21         FREEZE_CTRL_FROZEN = 0,
  22         FREEZE_CTRL_THAWED = 1
  23 } FREEZE_CTRL_CHAN_STATE;
  24
  25 #define SYSMGR_FRZCTRL_ADDRESS 0x40
  26 #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_SW 0x0
  27 #define SYSMGR_FRZCTRL_SRC_VIO1_ENUM_HW 0x1
  28 #define SYSMGR_FRZCTRL_VIOCTRL_SLEW_MASK 0x00000010
  29 #define SYSMGR_FRZCTRL_VIOCTRL_WKPULLUP_MASK 0x00000008
  30 #define SYSMGR_FRZCTRL_VIOCTRL_TRISTATE_MASK 0x00000004
  31 #define SYSMGR_FRZCTRL_VIOCTRL_BUSHOLD_MASK 0x00000002
  32 #define SYSMGR_FRZCTRL_VIOCTRL_CFG_MASK 0x00000001
  33 #define SYSMGR_FRZCTRL_HIOCTRL_SLEW_MASK 0x00000010
  34 #define SYSMGR_FRZCTRL_HIOCTRL_WKPULLUP_MASK 0x00000008
  35 #define SYSMGR_FRZCTRL_HIOCTRL_TRISTATE_MASK 0x00000004
  36 #define SYSMGR_FRZCTRL_HIOCTRL_BUSHOLD_MASK 0x00000002
  37 #define SYSMGR_FRZCTRL_HIOCTRL_CFG_MASK 0x00000001
  38 #define SYSMGR_FRZCTRL_HIOCTRL_REGRST_MASK 0x00000080
  39 #define SYSMGR_FRZCTRL_HIOCTRL_OCTRST_MASK 0x00000040
  40 #define SYSMGR_FRZCTRL_HIOCTRL_OCT_CFGEN_CALSTART_MASK 0x00000100
  41 #define SYSMGR_FRZCTRL_HIOCTRL_DLLRST_MASK 0x00000020
  42 #define SYSMGR_FRZCTRL_HWCTRL_VIO1REQ_MASK 0x00000001
  43 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_FROZEN 0x2
  44 #define SYSMGR_FRZCTRL_HWCTRL_VIO1STATE_ENUM_THAWED 0x1
  45
  46 void sys_mgr_frzctrl_freeze_req(void);
  47 void sys_mgr_frzctrl_thaw_req(void);
  48
  49 #endif /* _FREEZE_CONTROLLER_H_ */