arch/arm/include/asm/arch-spear/spr_misc.h

   1 /*
   2  * (C) Copyright 2009
   3  * Vipin Kumar, ST Micoelectronics, vipin.kumar@st.com.
   4  *
   5  * See file CREDITS for list of people who contributed to this
   6  * project.
   7  *
   8  * This program is free software; you can redistribute it and/or
   9  * modify it under the terms of the GNU General Public License as
  10  * published by the Free Software Foundation; either version 2 of
  11  * the License, or (at your option) any later version.
  12  *
  13  * This program is distributed in the hope that it will be useful,
  14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16  * GNU General Public License for more details.
  17  *
  18  * You should have received a copy of the GNU General Public License
  19  * along with this program; if not, write to the Free Software
  20  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21  * MA 02111-1307 USA
  22  */
  23
  24 #ifndef _SPR_MISC_H
  25 #define _SPR_MISC_H
  26
  27 struct misc_regs {
  28         u32 auto_cfg_reg;       /* 0x0 */
  29         u32 armdbg_ctr_reg;     /* 0x4 */
  30         u32 pll1_cntl;          /* 0x8 */
  31         u32 pll1_frq;           /* 0xc */
  32         u32 pll1_mod;           /* 0x10 */
  33         u32 pll2_cntl;          /* 0x14 */
  34         u32 pll2_frq;           /* 0x18 */
  35         u32 pll2_mod;           /* 0x1C */
  36         u32 pll_ctr_reg;        /* 0x20 */
  37         u32 amba_clk_cfg;       /* 0x24 */
  38         u32 periph_clk_cfg;     /* 0x28 */
  39         u32 periph1_clken;      /* 0x2C */
  40         u32 periph2_clken;      /* 0x30 */
  41         u32 ras_clken;          /* 0x34 */
  42         u32 periph1_rst;        /* 0x38 */
  43         u32 periph2_rst;        /* 0x3C */
  44         u32 ras_rst;            /* 0x40 */
  45         u32 prsc1_clk_cfg;      /* 0x44 */
  46         u32 prsc2_clk_cfg;      /* 0x48 */
  47         u32 prsc3_clk_cfg;      /* 0x4C */
  48         u32 amem_cfg_ctrl;      /* 0x50 */
  49         u32 port_cfg_ctrl;      /* 0x54 */
  50         u32 reserved_1;         /* 0x58 */
  51         u32 clcd_synth_clk;     /* 0x5C */
  52         u32 irda_synth_clk;     /* 0x60 */
  53         u32 uart_synth_clk;     /* 0x64 */
  54         u32 gmac_synth_clk;     /* 0x68 */
  55         u32 ras_synth1_clk;     /* 0x6C */
  56         u32 ras_synth2_clk;     /* 0x70 */
  57         u32 ras_synth3_clk;     /* 0x74 */
  58         u32 ras_synth4_clk;     /* 0x78 */
  59         u32 arb_icm_ml1;        /* 0x7C */
  60         u32 arb_icm_ml2;        /* 0x80 */
  61         u32 arb_icm_ml3;        /* 0x84 */
  62         u32 arb_icm_ml4;        /* 0x88 */
  63         u32 arb_icm_ml5;        /* 0x8C */
  64         u32 arb_icm_ml6;        /* 0x90 */
  65         u32 arb_icm_ml7;        /* 0x94 */
  66         u32 arb_icm_ml8;        /* 0x98 */
  67         u32 arb_icm_ml9;        /* 0x9C */
  68         u32 dma_src_sel;        /* 0xA0 */
  69         u32 uphy_ctr_reg;       /* 0xA4 */
  70         u32 gmac_ctr_reg;       /* 0xA8 */
  71         u32 port_bridge_ctrl;   /* 0xAC */
  72         u32 reserved_2[4];      /* 0xB0--0xBC */
  73         u32 prc1_ilck_ctrl_reg; /* 0xC0 */
  74         u32 prc2_ilck_ctrl_reg; /* 0xC4 */
  75         u32 prc3_ilck_ctrl_reg; /* 0xC8 */
  76         u32 prc4_ilck_ctrl_reg; /* 0xCC */
  77         u32 prc1_intr_ctrl_reg; /* 0xD0 */
  78         u32 prc2_intr_ctrl_reg; /* 0xD4 */
  79         u32 prc3_intr_ctrl_reg; /* 0xD8 */
  80         u32 prc4_intr_ctrl_reg; /* 0xDC */
  81         u32 powerdown_cfg_reg;  /* 0xE0 */
  82         u32 ddr_1v8_compensation;       /* 0xE4  */
  83         u32 ddr_2v5_compensation;       /* 0xE8 */
  84         u32 core_3v3_compensation;      /* 0xEC */
  85         u32 ddr_pad;            /* 0xF0 */
  86         u32 bist1_ctr_reg;      /* 0xF4 */
  87         u32 bist2_ctr_reg;      /* 0xF8 */
  88         u32 bist3_ctr_reg;      /* 0xFC */
  89         u32 bist4_ctr_reg;      /* 0x100 */
  90         u32 bist5_ctr_reg;      /* 0x104 */
  91         u32 bist1_rslt_reg;     /* 0x108 */
  92         u32 bist2_rslt_reg;     /* 0x10C */
  93         u32 bist3_rslt_reg;     /* 0x110 */
  94         u32 bist4_rslt_reg;     /* 0x114 */
  95         u32 bist5_rslt_reg;     /* 0x118 */
  96         u32 syst_error_reg;     /* 0x11C */
  97         u32 reserved_3[0x1FB8]; /* 0x120--0x7FFC */
  98         u32 ras_gpp1_in;        /* 0x8000 */
  99         u32 ras_gpp2_in;        /* 0x8004 */
 100         u32 ras_gpp1_out;       /* 0x8008 */
 101         u32 ras_gpp2_out;       /* 0x800C */
 102 };
 103
 104 /* AUTO_CFG_REG value */
 105 #define MISC_SOCCFGMSK                  0x0000003F
 106 #define MISC_SOCCFG30                   0x0000000C
 107 #define MISC_SOCCFG31                   0x0000000D
 108 #define MISC_NANDDIS                    0x00020000
 109
 110 /* PERIPH_CLK_CFG value */
 111 #define MISC_GPT3SYNTH                  0x00000400
 112 #define MISC_GPT4SYNTH                  0x00000800
 113
 114 /* PRSC_CLK_CFG value */
 115 /*
 116  * Fout = Fin / (2^(N+1) * (M + 1))
 117  */
 118 #define MISC_PRSC_N_1                   0x00001000
 119 #define MISC_PRSC_M_9                   0x00000009
 120 #define MISC_PRSC_N_4                   0x00004000
 121 #define MISC_PRSC_M_399                 0x0000018F
 122 #define MISC_PRSC_N_6                   0x00006000
 123 #define MISC_PRSC_M_2593                0x00000A21
 124 #define MISC_PRSC_M_124                 0x0000007C
 125 #define MISC_PRSC_CFG                   (MISC_PRSC_N_1 | MISC_PRSC_M_9)
 126
 127 /* PERIPH1_CLKEN, PERIPH1_RST value */
 128 #define MISC_USBDENB                    0x01000000
 129
 130 #endif