arch/arm/include/asm/arch-sunxi/dram_sun8i.h

   1 /*
   2  * Sun8i platform dram controller register and constant defines
   3  *
   4  * (C) Copyright 2007-2013
   5  * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
   6  * CPL <cplanxy@allwinnertech.com>
   7  * Jerry Wang <wangflord@allwinnertech.com>
   8  *
   9  * (C) Copyright 2014 Hans de Goede <hdegoede@redhat.com>
  10  *
  11  * SPDX-License-Identifier:     GPL-2.0+
  12  */
  13
  14 #ifndef _SUNXI_DRAM_SUN8I_H
  15 #define _SUNXI_DRAM_SUN8I_H
  16
  17 struct dram_para {
  18         u32 clock;
  19         u32 type;
  20         u32 zq;
  21         u32 odt_en;
  22         u32 para1;
  23         u32 para2;
  24         u32 mr0;
  25         u32 mr1;
  26         u32 mr2;
  27         u32 mr3;
  28         u32 tpr0;
  29         u32 tpr1;
  30         u32 tpr2;
  31         u32 tpr3;
  32         u32 tpr4;
  33         u32 tpr5;
  34         u32 tpr6;
  35         u32 tpr7;
  36         u32 tpr8;
  37         u32 tpr9;
  38         u32 tpr10;
  39         u32 tpr11;
  40         u32 tpr12;
  41         u32 tpr13;
  42 };
  43
  44 struct sunxi_mctl_com_reg {
  45         u32 cr;                 /* 0x00 */
  46         u32 ccr;                /* 0x04 controller configuration register */
  47         u32 dbgcr;              /* 0x08 */
  48         u8 res0[0x4];           /* 0x0c */
  49         u32 mcr0_0;             /* 0x10 */
  50         u32 mcr1_0;             /* 0x14 */
  51         u32 mcr0_1;             /* 0x18 */
  52         u32 mcr1_1;             /* 0x1c */
  53         u32 mcr0_2;             /* 0x20 */
  54         u32 mcr1_2;             /* 0x24 */
  55         u32 mcr0_3;             /* 0x28 */
  56         u32 mcr1_3;             /* 0x2c */
  57         u32 mcr0_4;             /* 0x30 */
  58         u32 mcr1_4;             /* 0x34 */
  59         u32 mcr0_5;             /* 0x38 */
  60         u32 mcr1_5;             /* 0x3c */
  61         u32 mcr0_6;             /* 0x40 */
  62         u32 mcr1_6;             /* 0x44 */
  63         u32 mcr0_7;             /* 0x48 */
  64         u32 mcr1_7;             /* 0x4c */
  65         u32 mcr0_8;             /* 0x50 */
  66         u32 mcr1_8;             /* 0x54 */
  67         u32 mcr0_9;             /* 0x58 */
  68         u32 mcr1_9;             /* 0x5c */
  69         u32 mcr0_10;            /* 0x60 */
  70         u32 mcr1_10;            /* 0x64 */
  71         u32 mcr0_11;            /* 0x68 */
  72         u32 mcr1_11;            /* 0x6c */
  73         u32 mcr0_12;            /* 0x70 */
  74         u32 mcr1_12;            /* 0x74 */
  75         u32 mcr0_13;            /* 0x78 */
  76         u32 mcr1_13;            /* 0x7c */
  77         u32 mcr0_14;            /* 0x80 */
  78         u32 mcr1_14;            /* 0x84 */
  79         u32 mcr0_15;            /* 0x88 */
  80         u32 mcr1_15;            /* 0x8c */
  81         u32 bwcr;               /* 0x90 */
  82         u32 maer;               /* 0x94 */
  83         u8 res1[0x4];           /* 0x98 */
  84         u32 mcgcr;              /* 0x9c */
  85         u32 bwctr;              /* 0xa0 */
  86         u8 res2[0x4];           /* 0xa4 */
  87         u32 swonr;              /* 0xa8 */
  88         u32 swoffr;             /* 0xac */
  89 };
  90
  91 struct sunxi_mctl_ctl_reg {
  92         u32 mstr;               /* 0x00 */
  93         u32 statr;              /* 0x04 */
  94         u8 res0[0x08];          /* 0x08 */
  95         u32 mrctrl0;            /* 0x10 */
  96         u32 mrctrl1;            /* 0x14 */
  97         u32 mrstatr;            /* 0x18 */
  98         u8 res1[0x04];          /* 0x1c */
  99         u32 derateen;           /* 0x20 */
 100         u32 deratenint;         /* 0x24 */
 101         u8 res2[0x08];          /* 0x28 */
 102         u32 pwrctl;             /* 0x30 */
 103         u32 pwrtmg;             /* 0x34 */
 104         u8 res3[0x18];          /* 0x38 */
 105         u32 rfshctl0;           /* 0x50 */
 106         u32 rfshctl1;           /* 0x54 */
 107         u8 res4[0x8];           /* 0x58 */
 108         u32 rfshctl3;           /* 0x60 */
 109         u32 rfshtmg;            /* 0x64 */
 110         u8 res6[0x68];          /* 0x68 */
 111         u32 init0;              /* 0xd0 */
 112         u32 init1;              /* 0xd4 */
 113         u32 init2;              /* 0xd8 */
 114         u32 init3;              /* 0xdc */
 115         u32 init4;              /* 0xe0 */
 116         u32 init5;              /* 0xe4 */
 117         u8 res7[0x0c];          /* 0xe8 */
 118         u32 rankctl;            /* 0xf4 */
 119         u8 res8[0x08];          /* 0xf8 */
 120         u32 dramtmg0;           /* 0x100 */
 121         u32 dramtmg1;           /* 0x104 */
 122         u32 dramtmg2;           /* 0x108 */
 123         u32 dramtmg3;           /* 0x10c */
 124         u32 dramtmg4;           /* 0x110 */
 125         u32 dramtmg5;           /* 0x114 */
 126         u32 dramtmg6;           /* 0x118 */
 127         u32 dramtmg7;           /* 0x11c */
 128         u32 dramtmg8;           /* 0x120 */
 129         u8 res9[0x5c];          /* 0x124 */
 130         u32 zqctl0;             /* 0x180 */
 131         u32 zqctl1;             /* 0x184 */
 132         u32 zqctl2;             /* 0x188 */
 133         u32 zqstat;             /* 0x18c */
 134         u32 pitmg0;             /* 0x190 */
 135         u32 pitmg1;             /* 0x194 */
 136         u32 plpcfg0;            /* 0x198 */
 137         u8 res10[0x04];         /* 0x19c */
 138         u32 upd0;               /* 0x1a0 */
 139         u32 upd1;               /* 0x1a4 */
 140         u32 upd2;               /* 0x1a8 */
 141         u32 upd3;               /* 0x1ac */
 142         u32 pimisc;             /* 0x1b0 */
 143         u8 res11[0x1c];         /* 0x1b4 */
 144         u32 trainctl0;          /* 0x1d0 */
 145         u32 trainctl1;          /* 0x1d4 */
 146         u32 trainctl2;          /* 0x1d8 */
 147         u32 trainstat;          /* 0x1dc */
 148         u8 res12[0x60];         /* 0x1e0 */
 149         u32 odtcfg;             /* 0x240 */
 150         u32 odtmap;             /* 0x244 */
 151         u8 res13[0x08];         /* 0x248 */
 152         u32 sched;              /* 0x250 */
 153         u8 res14[0x04];         /* 0x254 */
 154         u32 perfshpr0;          /* 0x258 */
 155         u32 perfshpr1;          /* 0x25c */
 156         u32 perflpr0;           /* 0x260 */
 157         u32 perflpr1;           /* 0x264 */
 158         u32 perfwr0;            /* 0x268 */
 159         u32 perfwr1;            /* 0x26c */
 160 };
 161
 162 struct sunxi_mctl_phy_reg {
 163         u8 res0[0x04];          /* 0x00 */
 164         u32 pir;                /* 0x04 */
 165         u32 pgcr0;              /* 0x08 phy general configuration register */
 166         u32 pgcr1;              /* 0x0c phy general configuration register */
 167         u32 pgsr0;              /* 0x10 */
 168         u32 pgsr1;              /* 0x14 */
 169         u32 dllgcr;             /* 0x18 */
 170         u32 ptr0;               /* 0x1c */
 171         u32 ptr1;               /* 0x20 */
 172         u32 ptr2;               /* 0x24 */
 173         u32 ptr3;               /* 0x28 */
 174         u32 ptr4;               /* 0x2c */
 175         u32 acmdlr;             /* 0x30 */
 176         u32 acbdlr;             /* 0x34 */
 177         u32 aciocr;             /* 0x38 */
 178         u32 dxccr;              /* 0x3c DATX8 common configuration register */
 179         u32 dsgcr;              /* 0x40 dram system general config register */
 180         u32 dcr;                /* 0x44 */
 181         u32 dtpr0;              /* 0x48 dram timing parameters register 0 */
 182         u32 dtpr1;              /* 0x4c dram timing parameters register 1 */
 183         u32 dtpr2;              /* 0x50 dram timing parameters register 2 */
 184         u32 mr0;                /* 0x54 mode register 0 */
 185         u32 mr1;                /* 0x58 mode register 1 */
 186         u32 mr2;                /* 0x5c mode register 2 */
 187         u32 mr3;                /* 0x60 mode register 3 */
 188         u32 odtcr;              /* 0x64 */
 189         u32 dtcr;               /* 0x68 */
 190         u32 dtar0;              /* 0x6c data training address register 0 */
 191         u32 dtar1;              /* 0x70 data training address register 1 */
 192         u32 dtar2;              /* 0x74 data training address register 2 */
 193         u32 dtar3;              /* 0x78 data training address register 3 */
 194         u32 dtdr0;              /* 0x7c */
 195         u32 dtdr1;              /* 0x80 */
 196         u32 dtedr0;             /* 0x84 */
 197         u32 dtedr1;             /* 0x88 */
 198         u32 pgcr2;              /* 0x8c */
 199         u8 res1[0x70];          /* 0x90 */
 200         u32 bistrr;             /* 0x100 */
 201         u32 bistwcr;            /* 0x104 */
 202         u32 bistmskr0;          /* 0x108 */
 203         u32 bistmskr1;          /* 0x10c */
 204         u32 bistmskr2;          /* 0x110 */
 205         u32 bistlsr;            /* 0x114 */
 206         u32 bistar0;            /* 0x118 */
 207         u32 bistar1;            /* 0x11c */
 208         u32 bistar2;            /* 0x120 */
 209         u32 bistupdr;           /* 0x124 */
 210         u32 bistgsr;            /* 0x128 */
 211         u32 bistwer;            /* 0x12c */
 212         u32 bistber0;           /* 0x130 */
 213         u32 bistber1;           /* 0x134 */
 214         u32 bistber2;           /* 0x138 */
 215         u32 bistber3;           /* 0x13c */
 216         u32 bistwcsr;           /* 0x140 */
 217         u32 bistfwr0;           /* 0x144 */
 218         u32 bistfwr1;           /* 0x148 */
 219         u32 bistfwr2;           /* 0x14c */
 220         u8 res2[0x30];          /* 0x150 */
 221         u32 zqcr0;              /* 0x180 zq control register 0 */
 222         u32 zqcr1;              /* 0x184 zq control register 1 */
 223         u32 zqsr0;              /* 0x188 zq status register 0 */
 224         u32 zqsr1;              /* 0x18c zq status register 1 */
 225         u32 zqcr2;              /* 0x190 zq control register 2 */
 226         u8 res3[0x2c];          /* 0x194 */
 227         u32 dx0gcr;             /* 0x1c0 */
 228         u32 dx0gsr0;            /* 0x1c4 */
 229         u32 dx0gsr1;            /* 0x1c8 */
 230         u32 dx0bdlr0;           /* 0x1cc */
 231         u32 dx0bdlr1;           /* 0x1d0 */
 232         u32 dx0bdlr2;           /* 0x1d4 */
 233         u32 dx0bdlr3;           /* 0x1d8 */
 234         u32 dx0bdlr4;           /* 0x1dc */
 235         u32 dx0lcdlr0;          /* 0x1e0 */
 236         u32 dx0lcdlr1;          /* 0x1e4 */
 237         u32 dx0lcdlr2;          /* 0x1e8 */
 238         u32 dx0mdlr;            /* 0x1ec */
 239         u32 dx0gtr;             /* 0x1f0 */
 240         u32 dx0gsr2;            /* 0x1f4 */
 241         u8 res4[0x08];          /* 0x1f8 */
 242         u32 dx1gcr;             /* 0x200 */
 243         u32 dx1gsr0;            /* 0x204 */
 244         u32 dx1gsr1;            /* 0x208 */
 245         u32 dx1bdlr0;           /* 0x20c */
 246         u32 dx1bdlr1;           /* 0x210 */
 247         u32 dx1bdlr2;           /* 0x214 */
 248         u32 dx1bdlr3;           /* 0x218 */
 249         u32 dx1bdlr4;           /* 0x21c */
 250         u32 dx1lcdlr0;          /* 0x220 */
 251         u32 dx1lcdlr1;          /* 0x224 */
 252         u32 dx1lcdlr2;          /* 0x228 */
 253         u32 dx1mdlr;            /* 0x22c */
 254         u32 dx1gtr;             /* 0x230 */
 255         u32 dx1gsr2;            /* 0x234 */
 256 };
 257
 258 /*
 259  * DRAM common (sunxi_mctl_com_reg) register constants.
 260  */
 261 #define MCTL_CR_ROW_MASK                (0xf << 4)
 262 #define MCTL_CR_ROW(x)                  (((x) - 1) << 4)
 263 #define MCTL_CR_PAGE_SIZE_MASK          (0xf << 8)
 264 #define MCTL_CR_PAGE_SIZE(x)            ((x) << 8)
 265
 266 #endif /* _SUNXI_DRAM_SUN8I_H */