arch/arm/include/asm/arch-tegra/tegra_mmc.h

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Portions Copyright (C) 2011-2012 NVIDIA Corporation
   5  *
   6  * This program is free software; you can redistribute it and/or modify
   7  * it under the terms of the GNU General Public License as published by
   8  * the Free Software Foundation; either version 2 of the License, or
   9  * (at your option) any later version.
  10  *
  11  * This program is distributed in the hope that it will be useful,
  12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14  * GNU General Public License for more details.
  15  *
  16  * You should have received a copy of the GNU General Public License
  17  * along with this program; if not, write to the Free Software
  18  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
  19  *
  20  */
  21
  22 #ifndef __TEGRA_MMC_H_
  23 #define __TEGRA_MMC_H_
  24
  25 #include <fdtdec.h>
  26
  27 #define MAX_HOSTS               4       /* Max number of 'hosts'/controllers */
  28
  29 #ifndef __ASSEMBLY__
  30 struct tegra_mmc {
  31         unsigned int    sysad;          /* _SYSTEM_ADDRESS_0 */
  32         unsigned short  blksize;        /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
  33         unsigned short  blkcnt;         /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
  34         unsigned int    argument;       /* _ARGUMENT_0 */
  35         unsigned short  trnmod;         /* _CMD_XFER_MODE_0 15:00 xfer mode */
  36         unsigned short  cmdreg;         /* _CMD_XFER_MODE_0 31:16 cmd reg */
  37         unsigned int    rspreg0;        /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
  38         unsigned int    rspreg1;        /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
  39         unsigned int    rspreg2;        /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
  40         unsigned int    rspreg3;        /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
  41         unsigned int    bdata;          /* _BUFFER_DATA_PORT_0 */
  42         unsigned int    prnsts;         /* _PRESENT_STATE_0 */
  43         unsigned char   hostctl;        /* _POWER_CONTROL_HOST_0 7:00 */
  44         unsigned char   pwrcon;         /* _POWER_CONTROL_HOST_0 15:8 */
  45         unsigned char   blkgap;         /* _POWER_CONTROL_HOST_9 23:16 */
  46         unsigned char   wakcon;         /* _POWER_CONTROL_HOST_0 31:24 */
  47         unsigned short  clkcon;         /* _CLOCK_CONTROL_0 15:00 */
  48         unsigned char   timeoutcon;     /* _TIMEOUT_CTRL 23:16 */
  49         unsigned char   swrst;          /* _SW_RESET_ 31:24 */
  50         unsigned int    norintsts;      /* _INTERRUPT_STATUS_0 */
  51         unsigned int    norintstsen;    /* _INTERRUPT_STATUS_ENABLE_0 */
  52         unsigned int    norintsigen;    /* _INTERRUPT_SIGNAL_ENABLE_0 */
  53         unsigned short  acmd12errsts;   /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
  54         unsigned char   res1[2];        /* _RESERVED 31:16 */
  55         unsigned int    capareg;        /* _CAPABILITIES_0 */
  56         unsigned char   res2[4];        /* RESERVED, offset 44h-47h */
  57         unsigned int    maxcurr;        /* _MAXIMUM_CURRENT_0 */
  58         unsigned char   res3[4];        /* RESERVED, offset 4Ch-4Fh */
  59         unsigned short  setacmd12err;   /* offset 50h */
  60         unsigned short  setinterr;      /* offset 52h */
  61         unsigned char   admaerr;        /* offset 54h */
  62         unsigned char   res4[3];        /* RESERVED, offset 55h-57h */
  63         unsigned long   admaaddr;       /* offset 58h-5Fh */
  64         unsigned char   res5[0xa0];     /* RESERVED, offset 60h-FBh */
  65         unsigned short  slotintstatus;  /* offset FCh */
  66         unsigned short  hcver;          /* HOST Version */
  67         unsigned int    venclkctl;      /* _VENDOR_CLOCK_CNTRL_0,    100h */
  68         unsigned int    venspictl;      /* _VENDOR_SPI_CNTRL_0,      104h */
  69         unsigned int    venspiintsts;   /* _VENDOR_SPI_INT_STATUS_0, 108h */
  70         unsigned int    venceatactl;    /* _VENDOR_CEATA_CNTRL_0,    10Ch */
  71         unsigned int    venbootctl;     /* _VENDOR_BOOT_CNTRL_0,     110h */
  72         unsigned int    venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
  73         unsigned int    venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
  74         unsigned int    vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
  75         unsigned int    venmiscctl;     /* _VENDOR_MISC_CNTRL_0,     120h */
  76         unsigned int    res6[47];       /* 0x124 ~ 0x1DC */
  77         unsigned int    sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0,      1E0h */
  78         unsigned int    autocalcfg;     /* _AUTO_CAL_CONFIG_0,       1E4h */
  79         unsigned int    autocalintval;  /* _AUTO_CAL_INTERVAL_0,     1E8h */
  80         unsigned int    autocalsts;     /* _AUTO_CAL_STATUS_0,       1ECh */
  81 };
  82
  83 #define TEGRA_MMC_PWRCTL_SD_BUS_POWER                           (1 << 0)
  84 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8                    (5 << 1)
  85 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0                    (6 << 1)
  86 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3                    (7 << 1)
  87
  88 #define TEGRA_MMC_HOSTCTL_DMASEL_MASK                           (3 << 3)
  89 #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                           (0 << 3)
  90 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                    (2 << 3)
  91 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                    (3 << 3)
  92
  93 #define TEGRA_MMC_TRNMOD_DMA_ENABLE                             (1 << 0)
  94 #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                     (1 << 1)
  95 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE                (0 << 4)
  96 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                 (1 << 4)
  97 #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                     (1 << 5)
  98
  99 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                  (3 << 0)
 100 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE           (0 << 0)
 101 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136            (1 << 0)
 102 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48             (2 << 0)
 103 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY        (3 << 0)
 104
 105 #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                          (1 << 3)
 106 #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                        (1 << 4)
 107 #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER      (1 << 5)
 108
 109 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                        (1 << 0)
 110 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                        (1 << 1)
 111
 112 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                  (1 << 0)
 113 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                  (1 << 1)
 114 #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                        (1 << 2)
 115
 116 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                   8
 117 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                    (0xff << 8)
 118
 119 #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                        (1 << 0)
 120 #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                   (1 << 1)
 121 #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                   (1 << 2)
 122
 123 #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                        (1 << 0)
 124 #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                       (1 << 1)
 125 #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                       (1 << 3)
 126 #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                       (1 << 15)
 127 #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                         (1 << 16)
 128
 129 #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                      (1 << 0)
 130 #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                     (1 << 1)
 131 #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                     (1 << 3)
 132 #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY                (1 << 4)
 133 #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                 (1 << 5)
 134
 135 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                     (1 << 1)
 136
 137 /* SDMMC1/3 settings from section 24.6 of T30 TRM */
 138 #define MEMCOMP_PADCTRL_VREF    7
 139 #define AUTO_CAL_ENABLED        (1 << 29)
 140 #define AUTO_CAL_PD_OFFSET      (0x70 << 8)
 141 #define AUTO_CAL_PU_OFFSET      (0x62 << 0)
 142
 143 struct mmc_host {
 144         struct tegra_mmc *reg;
 145         int id;                 /* device id/number, 0-3 */
 146         int enabled;            /* 1 to enable, 0 to disable */
 147         int width;              /* Bus Width, 1, 4 or 8 */
 148         enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
 149         struct fdt_gpio_state cd_gpio;          /* Change Detect GPIO */
 150         struct fdt_gpio_state pwr_gpio;         /* Power GPIO */
 151         struct fdt_gpio_state wp_gpio;          /* Write Protect GPIO */
 152         unsigned int version;   /* SDHCI spec. version */
 153         unsigned int clock;     /* Current clock (MHz) */
 154 };
 155
 156 void pad_init_mmc(struct mmc_host *host);
 157
 158 #endif  /* __ASSEMBLY__ */
 159 #endif  /* __TEGRA_MMC_H_ */