arch/arm/include/asm/arch-tegra/tegra_mmc.h

   1 /*
   2  * (C) Copyright 2009 SAMSUNG Electronics
   3  * Minkyu Kang <mk7.kang@samsung.com>
   4  * Portions Copyright (C) 2011-2012 NVIDIA Corporation
   5  *
   6  * SPDX-License-Identifier:     GPL-2.0+
   7  */
   8
   9 #ifndef __TEGRA_MMC_H_
  10 #define __TEGRA_MMC_H_
  11
  12 #include <fdtdec.h>
  13
  14 #define MAX_HOSTS               4       /* Max number of 'hosts'/controllers */
  15
  16 #ifndef __ASSEMBLY__
  17 struct tegra_mmc {
  18         unsigned int    sysad;          /* _SYSTEM_ADDRESS_0 */
  19         unsigned short  blksize;        /* _BLOCK_SIZE_BLOCK_COUNT_0 15:00 */
  20         unsigned short  blkcnt;         /* _BLOCK_SIZE_BLOCK_COUNT_0 31:16 */
  21         unsigned int    argument;       /* _ARGUMENT_0 */
  22         unsigned short  trnmod;         /* _CMD_XFER_MODE_0 15:00 xfer mode */
  23         unsigned short  cmdreg;         /* _CMD_XFER_MODE_0 31:16 cmd reg */
  24         unsigned int    rspreg0;        /* _RESPONSE_R0_R1_0 CMD RESP 31:00 */
  25         unsigned int    rspreg1;        /* _RESPONSE_R2_R3_0 CMD RESP 63:32 */
  26         unsigned int    rspreg2;        /* _RESPONSE_R4_R5_0 CMD RESP 95:64 */
  27         unsigned int    rspreg3;        /* _RESPONSE_R6_R7_0 CMD RESP 127:96 */
  28         unsigned int    bdata;          /* _BUFFER_DATA_PORT_0 */
  29         unsigned int    prnsts;         /* _PRESENT_STATE_0 */
  30         unsigned char   hostctl;        /* _POWER_CONTROL_HOST_0 7:00 */
  31         unsigned char   pwrcon;         /* _POWER_CONTROL_HOST_0 15:8 */
  32         unsigned char   blkgap;         /* _POWER_CONTROL_HOST_9 23:16 */
  33         unsigned char   wakcon;         /* _POWER_CONTROL_HOST_0 31:24 */
  34         unsigned short  clkcon;         /* _CLOCK_CONTROL_0 15:00 */
  35         unsigned char   timeoutcon;     /* _TIMEOUT_CTRL 23:16 */
  36         unsigned char   swrst;          /* _SW_RESET_ 31:24 */
  37         unsigned int    norintsts;      /* _INTERRUPT_STATUS_0 */
  38         unsigned int    norintstsen;    /* _INTERRUPT_STATUS_ENABLE_0 */
  39         unsigned int    norintsigen;    /* _INTERRUPT_SIGNAL_ENABLE_0 */
  40         unsigned short  acmd12errsts;   /* _AUTO_CMD12_ERR_STATUS_0 15:00 */
  41         unsigned char   res1[2];        /* _RESERVED 31:16 */
  42         unsigned int    capareg;        /* _CAPABILITIES_0 */
  43         unsigned char   res2[4];        /* RESERVED, offset 44h-47h */
  44         unsigned int    maxcurr;        /* _MAXIMUM_CURRENT_0 */
  45         unsigned char   res3[4];        /* RESERVED, offset 4Ch-4Fh */
  46         unsigned short  setacmd12err;   /* offset 50h */
  47         unsigned short  setinterr;      /* offset 52h */
  48         unsigned char   admaerr;        /* offset 54h */
  49         unsigned char   res4[3];        /* RESERVED, offset 55h-57h */
  50         unsigned long   admaaddr;       /* offset 58h-5Fh */
  51         unsigned char   res5[0xa0];     /* RESERVED, offset 60h-FBh */
  52         unsigned short  slotintstatus;  /* offset FCh */
  53         unsigned short  hcver;          /* HOST Version */
  54         unsigned int    venclkctl;      /* _VENDOR_CLOCK_CNTRL_0,    100h */
  55         unsigned int    venspictl;      /* _VENDOR_SPI_CNTRL_0,      104h */
  56         unsigned int    venspiintsts;   /* _VENDOR_SPI_INT_STATUS_0, 108h */
  57         unsigned int    venceatactl;    /* _VENDOR_CEATA_CNTRL_0,    10Ch */
  58         unsigned int    venbootctl;     /* _VENDOR_BOOT_CNTRL_0,     110h */
  59         unsigned int    venbootacktout; /* _VENDOR_BOOT_ACK_TIMEOUT, 114h */
  60         unsigned int    venbootdattout; /* _VENDOR_BOOT_DAT_TIMEOUT, 118h */
  61         unsigned int    vendebouncecnt; /* _VENDOR_DEBOUNCE_COUNT_0, 11Ch */
  62         unsigned int    venmiscctl;     /* _VENDOR_MISC_CNTRL_0,     120h */
  63         unsigned int    res6[47];       /* 0x124 ~ 0x1DC */
  64         unsigned int    sdmemcmppadctl; /* _SDMEMCOMPPADCTRL_0,      1E0h */
  65         unsigned int    autocalcfg;     /* _AUTO_CAL_CONFIG_0,       1E4h */
  66         unsigned int    autocalintval;  /* _AUTO_CAL_INTERVAL_0,     1E8h */
  67         unsigned int    autocalsts;     /* _AUTO_CAL_STATUS_0,       1ECh */
  68 };
  69
  70 #define TEGRA_MMC_PWRCTL_SD_BUS_POWER                           (1 << 0)
  71 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V1_8                    (5 << 1)
  72 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_0                    (6 << 1)
  73 #define TEGRA_MMC_PWRCTL_SD_BUS_VOLTAGE_V3_3                    (7 << 1)
  74
  75 #define TEGRA_MMC_HOSTCTL_DMASEL_MASK                           (3 << 3)
  76 #define TEGRA_MMC_HOSTCTL_DMASEL_SDMA                           (0 << 3)
  77 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_32BIT                    (2 << 3)
  78 #define TEGRA_MMC_HOSTCTL_DMASEL_ADMA2_64BIT                    (3 << 3)
  79
  80 #define TEGRA_MMC_TRNMOD_DMA_ENABLE                             (1 << 0)
  81 #define TEGRA_MMC_TRNMOD_BLOCK_COUNT_ENABLE                     (1 << 1)
  82 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_WRITE                (0 << 4)
  83 #define TEGRA_MMC_TRNMOD_DATA_XFER_DIR_SEL_READ                 (1 << 4)
  84 #define TEGRA_MMC_TRNMOD_MULTI_BLOCK_SELECT                     (1 << 5)
  85
  86 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_MASK                  (3 << 0)
  87 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_NO_RESPONSE           (0 << 0)
  88 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_136            (1 << 0)
  89 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48             (2 << 0)
  90 #define TEGRA_MMC_CMDREG_RESP_TYPE_SELECT_LENGTH_48_BUSY        (3 << 0)
  91
  92 #define TEGRA_MMC_TRNMOD_CMD_CRC_CHECK                          (1 << 3)
  93 #define TEGRA_MMC_TRNMOD_CMD_INDEX_CHECK                        (1 << 4)
  94 #define TEGRA_MMC_TRNMOD_DATA_PRESENT_SELECT_DATA_TRANSFER      (1 << 5)
  95
  96 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_CMD                        (1 << 0)
  97 #define TEGRA_MMC_PRNSTS_CMD_INHIBIT_DAT                        (1 << 1)
  98
  99 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_ENABLE                  (1 << 0)
 100 #define TEGRA_MMC_CLKCON_INTERNAL_CLOCK_STABLE                  (1 << 1)
 101 #define TEGRA_MMC_CLKCON_SD_CLOCK_ENABLE                        (1 << 2)
 102
 103 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_SHIFT                   8
 104 #define TEGRA_MMC_CLKCON_SDCLK_FREQ_SEL_MASK                    (0xff << 8)
 105
 106 #define TEGRA_MMC_SWRST_SW_RESET_FOR_ALL                        (1 << 0)
 107 #define TEGRA_MMC_SWRST_SW_RESET_FOR_CMD_LINE                   (1 << 1)
 108 #define TEGRA_MMC_SWRST_SW_RESET_FOR_DAT_LINE                   (1 << 2)
 109
 110 #define TEGRA_MMC_NORINTSTS_CMD_COMPLETE                        (1 << 0)
 111 #define TEGRA_MMC_NORINTSTS_XFER_COMPLETE                       (1 << 1)
 112 #define TEGRA_MMC_NORINTSTS_DMA_INTERRUPT                       (1 << 3)
 113 #define TEGRA_MMC_NORINTSTS_ERR_INTERRUPT                       (1 << 15)
 114 #define TEGRA_MMC_NORINTSTS_CMD_TIMEOUT                         (1 << 16)
 115
 116 #define TEGRA_MMC_NORINTSTSEN_CMD_COMPLETE                      (1 << 0)
 117 #define TEGRA_MMC_NORINTSTSEN_XFER_COMPLETE                     (1 << 1)
 118 #define TEGRA_MMC_NORINTSTSEN_DMA_INTERRUPT                     (1 << 3)
 119 #define TEGRA_MMC_NORINTSTSEN_BUFFER_WRITE_READY                (1 << 4)
 120 #define TEGRA_MMC_NORINTSTSEN_BUFFER_READ_READY                 (1 << 5)
 121
 122 #define TEGRA_MMC_NORINTSIGEN_XFER_COMPLETE                     (1 << 1)
 123
 124 /* SDMMC1/3 settings from section 24.6 of T30 TRM */
 125 #define MEMCOMP_PADCTRL_VREF    7
 126 #define AUTO_CAL_ENABLED        (1 << 29)
 127 #define AUTO_CAL_PD_OFFSET      (0x70 << 8)
 128 #define AUTO_CAL_PU_OFFSET      (0x62 << 0)
 129
 130 struct mmc_host {
 131         struct tegra_mmc *reg;
 132         int id;                 /* device id/number, 0-3 */
 133         int enabled;            /* 1 to enable, 0 to disable */
 134         int width;              /* Bus Width, 1, 4 or 8 */
 135         enum periph_id mmc_id;  /* Peripheral ID: PERIPH_ID_... */
 136         struct fdt_gpio_state cd_gpio;          /* Change Detect GPIO */
 137         struct fdt_gpio_state pwr_gpio;         /* Power GPIO */
 138         struct fdt_gpio_state wp_gpio;          /* Write Protect GPIO */
 139         unsigned int version;   /* SDHCI spec. version */
 140         unsigned int clock;     /* Current clock (MHz) */
 141 };
 142
 143 void pad_init_mmc(struct mmc_host *host);
 144
 145 #endif  /* __ASSEMBLY__ */
 146 #endif  /* __TEGRA_MMC_H_ */