arch/arm/include/asm/arch-tegra/usb.h

   1 /*
   2  * Copyright (c) 2011 The Chromium OS Authors.
   3  * Copyright (c) 2013 NVIDIA Corporation
   4  *
   5  * SPDX-License-Identifier:     GPL-2.0+
   6  */
   7
   8 #ifndef _TEGRA_USB_H_
   9 #define _TEGRA_USB_H_
  10
  11 /* USB Controller (USBx_CONTROLLER_) regs */
  12 struct usb_ctlr {
  13         /* 0x000 */
  14         uint id;
  15         uint reserved0;
  16         uint host;
  17         uint device;
  18
  19         /* 0x010 */
  20         uint txbuf;
  21         uint rxbuf;
  22         uint reserved1[2];
  23
  24         /* 0x020 */
  25         uint reserved2[56];
  26
  27         /* 0x100 */
  28         u16 cap_length;
  29         u16 hci_version;
  30         uint hcs_params;
  31         uint hcc_params;
  32         uint reserved3[5];
  33
  34         /* 0x120 */
  35         uint dci_version;
  36         uint dcc_params;
  37         uint reserved4[2];
  38
  39 #ifdef CONFIG_TEGRA20
  40         /* 0x130 */
  41         uint reserved4_2[4];
  42
  43         /* 0x140 */
  44         uint usb_cmd;
  45         uint usb_sts;
  46         uint usb_intr;
  47         uint frindex;
  48
  49         /* 0x150 */
  50         uint reserved5;
  51         uint periodic_list_base;
  52         uint async_list_addr;
  53         uint async_tt_sts;
  54
  55         /* 0x160 */
  56         uint burst_size;
  57         uint tx_fill_tuning;
  58         uint reserved6;   /* is this port_sc1 on some controllers? */
  59         uint icusb_ctrl;
  60
  61         /* 0x170 */
  62         uint ulpi_viewport;
  63         uint reserved7;
  64         uint endpt_nak;
  65         uint endpt_nak_enable;
  66
  67         /* 0x180 */
  68         uint reserved;
  69         uint port_sc1;
  70         uint reserved8[6];
  71
  72         /* 0x1a0 */
  73         uint reserved9;
  74         uint otgsc;
  75         uint usb_mode;
  76         uint endpt_setup_stat;
  77
  78         /* 0x1b0 */
  79         uint reserved10[20];
  80
  81         /* 0x200 */
  82         uint reserved11[0x80];
  83 #else
  84         /* 0x130 */
  85         uint usb_cmd;
  86         uint usb_sts;
  87         uint usb_intr;
  88         uint frindex;
  89
  90         /* 0x140 */
  91         uint reserved5;
  92         uint periodic_list_base;
  93         uint async_list_addr;
  94         uint reserved5_1;
  95
  96         /* 0x150 */
  97         uint burst_size;
  98         uint tx_fill_tuning;
  99         uint reserved6;
 100         uint icusb_ctrl;
 101
 102         /* 0x160 */
 103         uint ulpi_viewport;
 104         uint reserved7[3];
 105
 106         /* 0x170 */
 107         uint reserved;
 108         uint port_sc1;
 109         uint reserved8[6];
 110
 111         /* 0x190 */
 112         uint reserved9[8];
 113
 114         /* 0x1b0 */
 115         uint reserved10;
 116         uint hostpc1_devlc;
 117         uint reserved10_1[2];
 118
 119         /* 0x1c0 */
 120         uint reserved10_2[4];
 121
 122         /* 0x1d0 */
 123         uint reserved10_3[4];
 124
 125         /* 0x1e0 */
 126         uint reserved10_4[4];
 127
 128         /* 0x1f0 */
 129         uint reserved10_5;
 130         uint otgsc;
 131         uint usb_mode;
 132         uint reserved10_6;
 133
 134         /* 0x200 */
 135         uint endpt_nak;
 136         uint endpt_nak_enable;
 137         uint endpt_setup_stat;
 138         uint reserved11_1[0x7D];
 139 #endif
 140
 141         /* 0x400 */
 142         uint susp_ctrl;
 143         uint phy_vbus_sensors;
 144         uint phy_vbus_wakeup_id;
 145         uint phy_alt_vbus_sys;
 146
 147 #ifdef CONFIG_TEGRA20
 148         /* 0x410 */
 149         uint usb1_legacy_ctrl;
 150         uint reserved12[4];
 151
 152         /* 0x424 */
 153         uint ulpi_timing_ctrl_0;
 154         uint ulpi_timing_ctrl_1;
 155         uint reserved13[53];
 156 #else
 157
 158         /* 0x410 */
 159         uint usb1_legacy_ctrl;
 160         uint reserved12[3];
 161
 162         /* 0x420 */
 163         uint reserved13[56];
 164 #endif
 165
 166         /* 0x500 */
 167         uint reserved14[64 * 3];
 168
 169         /* 0x800 */
 170         uint utmip_pll_cfg0;
 171         uint utmip_pll_cfg1;
 172         uint utmip_xcvr_cfg0;
 173         uint utmip_bias_cfg0;
 174
 175         /* 0x810 */
 176         uint utmip_hsrx_cfg0;
 177         uint utmip_hsrx_cfg1;
 178         uint utmip_fslsrx_cfg0;
 179         uint utmip_fslsrx_cfg1;
 180
 181         /* 0x820 */
 182         uint utmip_tx_cfg0;
 183         uint utmip_misc_cfg0;
 184         uint utmip_misc_cfg1;
 185         uint utmip_debounce_cfg0;
 186
 187         /* 0x830 */
 188         uint utmip_bat_chrg_cfg0;
 189         uint utmip_spare_cfg0;
 190         uint utmip_xcvr_cfg1;
 191         uint utmip_bias_cfg1;
 192 };
 193
 194 /* USB1_LEGACY_CTRL */
 195 #define USB1_NO_LEGACY_MODE             1
 196
 197 #define VBUS_SENSE_CTL_SHIFT                    1
 198 #define VBUS_SENSE_CTL_MASK                     (3 << VBUS_SENSE_CTL_SHIFT)
 199 #define VBUS_SENSE_CTL_VBUS_WAKEUP              0
 200 #define VBUS_SENSE_CTL_AB_SESS_VLD_OR_VBUS_WAKEUP       1
 201 #define VBUS_SENSE_CTL_AB_SESS_VLD              2
 202 #define VBUS_SENSE_CTL_A_SESS_VLD               3
 203
 204 /* USBx_IF_USB_SUSP_CTRL_0 */
 205 #define UTMIP_PHY_ENB                           (1 << 12)
 206 #define UTMIP_RESET                             (1 << 11)
 207 #define USB_PHY_CLK_VALID                       (1 << 7)
 208 #define USB_SUSP_CLR                            (1 << 5)
 209
 210 #if defined(CONFIG_TEGRA20) || defined(CONFIG_TEGRA30)
 211 /* USB2_IF_USB_SUSP_CTRL_0 */
 212 #define ULPI_PHY_ENB                            (1 << 13)
 213
 214 /* USB2_IF_ULPI_TIMING_CTRL_0 */
 215 #define ULPI_OUTPUT_PINMUX_BYP                  (1 << 10)
 216 #define ULPI_CLKOUT_PINMUX_BYP                  (1 << 11)
 217
 218 /* USB2_IF_ULPI_TIMING_CTRL_1 */
 219 #define ULPI_DATA_TRIMMER_LOAD                  (1 << 0)
 220 #define ULPI_DATA_TRIMMER_SEL(x)                (((x) & 0x7) << 1)
 221 #define ULPI_STPDIRNXT_TRIMMER_LOAD             (1 << 16)
 222 #define ULPI_STPDIRNXT_TRIMMER_SEL(x)   (((x) & 0x7) << 17)
 223 #define ULPI_DIR_TRIMMER_LOAD                   (1 << 24)
 224 #define ULPI_DIR_TRIMMER_SEL(x)                 (((x) & 0x7) << 25)
 225 #endif
 226
 227 /* USBx_UTMIP_MISC_CFG0 */
 228 #define UTMIP_SUSPEND_EXIT_ON_EDGE              (1 << 22)
 229
 230 /* USBx_UTMIP_MISC_CFG1 */
 231 #define UTMIP_PHY_XTAL_CLOCKEN                  (1 << 30)
 232
 233 /*
 234  * Tegra 3 and later: Moved to Clock and Reset register space, see
 235  * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
 236  */
 237 #define UTMIP_PLLU_STABLE_COUNT_SHIFT           6
 238 #define UTMIP_PLLU_STABLE_COUNT_MASK            \
 239                                 (0xfff << UTMIP_PLLU_STABLE_COUNT_SHIFT)
 240 /*
 241  * Tegra 3 and later: Moved to Clock and Reset register space, see
 242  * CLK_RST_CONTROLLER_UTMIP_PLL_CFG2_0
 243  */
 244 #define UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT        18
 245 #define UTMIP_PLL_ACTIVE_DLY_COUNT_MASK         \
 246                                 (0x1f << UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT)
 247
 248 /* USBx_UTMIP_PLL_CFG1_0 */
 249 /* Tegra 3 and later: Moved to Clock and Reset register space */
 250 #define UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT       27
 251 #define UTMIP_PLLU_ENABLE_DLY_COUNT_MASK        \
 252                                 (0x1f << UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT)
 253 #define UTMIP_XTAL_FREQ_COUNT_SHIFT             0
 254 #define UTMIP_XTAL_FREQ_COUNT_MASK              0xfff
 255
 256 /* USBx_UTMIP_BIAS_CFG0_0 */
 257 #define UTMIP_HSDISCON_LEVEL_MSB                (1 << 24)
 258 #define UTMIP_OTGPD                             (1 << 11)
 259 #define UTMIP_BIASPD                            (1 << 10)
 260 #define UTMIP_HSDISCON_LEVEL_SHIFT              2
 261 #define UTMIP_HSDISCON_LEVEL_MASK               \
 262                                 (0x3 << UTMIP_HSDISCON_LEVEL_SHIFT)
 263 #define UTMIP_HSSQUELCH_LEVEL_SHIFT             0
 264 #define UTMIP_HSSQUELCH_LEVEL_MASK              \
 265                                 (0x3 << UTMIP_HSSQUELCH_LEVEL_SHIFT)
 266
 267 /* USBx_UTMIP_BIAS_CFG1_0 */
 268 #define UTMIP_FORCE_PDTRK_POWERDOWN             1
 269 #define UTMIP_BIAS_PDTRK_COUNT_SHIFT            3
 270 #define UTMIP_BIAS_PDTRK_COUNT_MASK             \
 271                                 (0x1f << UTMIP_BIAS_PDTRK_COUNT_SHIFT)
 272
 273 /* USBx_UTMIP_DEBOUNCE_CFG0_0 */
 274 #define UTMIP_DEBOUNCE_CFG0_SHIFT               0
 275 #define UTMIP_DEBOUNCE_CFG0_MASK                0xffff
 276
 277 /* USBx_UTMIP_TX_CFG0_0 */
 278 #define UTMIP_FS_PREAMBLE_J                     (1 << 19)
 279
 280 /* USBx_UTMIP_BAT_CHRG_CFG0_0 */
 281 #define UTMIP_PD_CHRG                           1
 282
 283 /* USBx_UTMIP_SPARE_CFG0_0 */
 284 #define FUSE_SETUP_SEL                          (1 << 3)
 285
 286 /* USBx_UTMIP_HSRX_CFG0_0 */
 287 #define UTMIP_IDLE_WAIT_SHIFT                   15
 288 #define UTMIP_IDLE_WAIT_MASK                    (0x1f << UTMIP_IDLE_WAIT_SHIFT)
 289 #define UTMIP_ELASTIC_LIMIT_SHIFT               10
 290 #define UTMIP_ELASTIC_LIMIT_MASK                \
 291                                 (0x1f << UTMIP_ELASTIC_LIMIT_SHIFT)
 292
 293 /* USBx_UTMIP_HSRX_CFG1_0 */
 294 #define UTMIP_HS_SYNC_START_DLY_SHIFT           1
 295 #define UTMIP_HS_SYNC_START_DLY_MASK            \
 296                                 (0x1f << UTMIP_HS_SYNC_START_DLY_SHIFT)
 297
 298 /* USBx_CONTROLLER_2_USB2D_ICUSB_CTRL_0 */
 299 #define IC_ENB1                                 (1 << 3)
 300
 301 #ifdef CONFIG_TEGRA20
 302 /* PORTSC1, USB1 */
 303 #define PTS1_SHIFT                              31
 304 #define PTS1_MASK                               (1 << PTS1_SHIFT)
 305 #define STS1                                    (1 << 30)
 306
 307 /* PORTSC, USB2, USB3 */
 308 #define PTS_SHIFT               30
 309 #define PTS_MASK                (3U << PTS_SHIFT)
 310 #define STS                     (1 << 29)
 311 #else
 312 /* USB2D_HOSTPC1_DEVLC_0 */
 313 #define PTS_SHIFT                               29
 314 #define PTS_MASK                                (0x7U << PTS_SHIFT)
 315 #define STS                                             (1 << 28)
 316 #endif
 317
 318 #define PTS_UTMI        0
 319 #define PTS_RESERVED    1
 320 #define PTS_ULPI        2
 321 #define PTS_ICUSB_SER   3
 322 #define PTS_HSIC        4
 323
 324 /* SB2_CONTROLLER_2_USB2D_PORTSC1_0 */
 325 #define WKOC                            (1 << 22)
 326 #define WKDS                            (1 << 21)
 327 #define WKCN                            (1 << 20)
 328
 329 /* USBx_UTMIP_XCVR_CFG0_0 */
 330 #define UTMIP_FORCE_PD_POWERDOWN                (1 << 14)
 331 #define UTMIP_FORCE_PD2_POWERDOWN               (1 << 16)
 332 #define UTMIP_FORCE_PDZI_POWERDOWN              (1 << 18)
 333 #define UTMIP_XCVR_LSBIAS_SE                    (1 << 21)
 334 #define UTMIP_XCVR_HSSLEW_MSB_SHIFT             25
 335 #define UTMIP_XCVR_HSSLEW_MSB_MASK              \
 336                         (0x7f << UTMIP_XCVR_HSSLEW_MSB_SHIFT)
 337 #define UTMIP_XCVR_SETUP_MSB_SHIFT      22
 338 #define UTMIP_XCVR_SETUP_MSB_MASK       (0x7 << UTMIP_XCVR_SETUP_MSB_SHIFT)
 339 #define UTMIP_XCVR_SETUP_SHIFT          0
 340 #define UTMIP_XCVR_SETUP_MASK           (0xf << UTMIP_XCVR_SETUP_SHIFT)
 341
 342 /* USBx_UTMIP_XCVR_CFG1_0 */
 343 #define UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT         18
 344 #define UTMIP_XCVR_TERM_RANGE_ADJ_MASK          \
 345                         (0xf << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT)
 346 #define UTMIP_FORCE_PDDISC_POWERDOWN            (1 << 0)
 347 #define UTMIP_FORCE_PDCHRP_POWERDOWN            (1 << 2)
 348 #define UTMIP_FORCE_PDDR_POWERDOWN              (1 << 4)
 349
 350 /* USB3_IF_USB_PHY_VBUS_SENSORS_0 */
 351 #define VBUS_VLD_STS                    (1 << 26)
 352
 353 /* Setup USB on the board */
 354 int usb_process_devicetree(const void *blob);
 355
 356 #endif  /* _TEGRA_USB_H_ */