3 * NVIDIA Corporation <www.nvidia.com>
5 * SPDX-License-Identifier: GPL-2.0+
8 #ifndef _TEGRA124_PINMUX_H_
9 #define _TEGRA124_PINMUX_H_
12 * Pin groups which we adjust. There are three basic attributes of each pin
13 * group which use this enum:
17 * - tristate or normal
20 PINGRP_ULPI_DATA0 = 0, /* offset 0x3000 */
44 PINGRP_CLK2_OUT = PINGRP_SDMMC1_DAT0 + 3,
46 PINGRP_HDMI_INT = PINGRP_CLK2_REQ + 41,
49 PINGRP_UART2_RXD = PINGRP_DDC_SDA + 19,
72 /* Renamed on Tegra124, from GMI_xx to GPIO_Pxx */
73 PINGRP_GPIO_PC7, /* offset 0x31c0 */
108 PINGRP_GPIO_PI4, /* offset 0x324c */
121 PINGRP_CAM_MCLK = PINGRP_SDMMC4_DAT7 + 2,
151 PINGRP_KB_COL0, /* offset 0x32fc */
160 PINGRP_CORE_PWR_REQ = PINGRP_CLK_32K_OUT + 2, /* offset 0x3324 */
185 PINGRP_SDMMC3_CLK = PINGRP_GPIO_X7_AUD + 3,
191 PINGRP_PEX_L0_RST = PINGRP_SDMMC3_DAT3 + 6, /* offset 0x33bc */
192 PINGRP_PEX_L0_CLKREQ,
194 PINGRP_PEX_L1_RST = PINGRP_PEX_WAKE + 2,
195 PINGRP_PEX_L1_CLKREQ,
196 PINGRP_HDMI_CEC = PINGRP_PEX_L1_CLKREQ + 4, /* offset 0x33e0 */
203 PINGRP_SDMMC3_CLK_LB_IN,
204 PINGRP_SDMMC3_CLK_LB_OUT,
207 PINGRP_KB_ROW16, /* offset 0x340c */
211 PINGRP_DP_HPD, /* last reg offset = 0x3430 */
216 PDRIVE_PINGROUP_AO1 = 0, /* offset 0x868 */
223 PDRIVE_PINGROUP_CDEV1,
224 PDRIVE_PINGROUP_CDEV2,
225 PDRIVE_PINGROUP_DAP1 = 10, /* offset 0x890 */
226 PDRIVE_PINGROUP_DAP2,
227 PDRIVE_PINGROUP_DAP3,
228 PDRIVE_PINGROUP_DAP4,
230 PDRIVE_PINGROUP_SDIO3 = 18, /* offset 0x8B0 */
234 PDRIVE_PINGROUP_UART2,
235 PDRIVE_PINGROUP_UART3,
236 PDRIVE_PINGROUP_SDIO1 = 33, /* offset 0x8EC */
237 PDRIVE_PINGROUP_DDC = 37, /* offset 0x8FC */
239 PDRIVE_PINGROUP_GME = 42, /* offset 0x910 */
245 PDRIVE_PINGROUP_DEV3 = 49, /* offset 0x92c */
246 PDRIVE_PINGROUP_CEC = 52, /* offset 0x938 */
247 PDRIVE_PINGROUP_AT6 = 75, /* offset 0x994 */
248 PDRIVE_PINGROUP_DAP5,
249 PDRIVE_PINGROUP_VBUS,
252 PDRIVE_PINGROUP_SDIO4,
254 PDRIVE_PINGROUP_COUNT,
258 * Functions which can be assigned to each of the pin groups. The values here
259 * bear no relation to the values programmed into pinmux registers and are
260 * purely a convenience. The translation is done through a table search.
265 PMUX_FUNC_AUDIO_SYNC,
274 PMUX_FUNC_EMC_TEST0_DLL,
275 PMUX_FUNC_EMC_TEST1_DLL,
320 PMUX_FUNC_VI_SENSOR_CLK,
322 /* End of Tegra2 MUX selectors */
335 PMUX_FUNC_EXTPERIPH1,
336 PMUX_FUNC_EXTPERIPH2,
337 PMUX_FUNC_EXTPERIPH3,
366 /* End of Tegra3 MUX selectors */
374 PMUX_FUNC_RESET_OUT_N,
375 /* End of Tegra114 MUX selectors */
379 PMUX_FUNC_INVALID = 0x4000,
380 PMUX_FUNC_RSVD1 = 0x8000,
381 PMUX_FUNC_RSVD2 = 0x8001,
382 PMUX_FUNC_RSVD3 = 0x8002,
383 PMUX_FUNC_RSVD4 = 0x8003,
386 #define TEGRA_PMX_HAS_PIN_IO_BIT_ETC
387 #define TEGRA_PMX_HAS_RCV_SEL
388 #define TEGRA_PMX_HAS_PADGRPS
389 #include <asm/arch-tegra/pinmux.h>
391 #endif /* _TEGRA124_PINMUX_H_ */