arch/arm/include/asm/arch-vf610/crm_regs.h

   1 /*
   2  * Copyright 2013 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #ifndef __ARCH_ARM_MACH_VF610_CCM_REGS_H__
   8 #define __ARCH_ARM_MACH_VF610_CCM_REGS_H__
   9
  10 #ifndef __ASSEMBLY__
  11
  12 /* Clock Controller Module (CCM) */
  13 struct ccm_reg {
  14         u32 ccr;
  15         u32 csr;
  16         u32 ccsr;
  17         u32 cacrr;
  18         u32 cscmr1;
  19         u32 cscdr1;
  20         u32 cscdr2;
  21         u32 cscdr3;
  22         u32 cscmr2;
  23         u32 cscdr4;
  24         u32 ctor;
  25         u32 clpcr;
  26         u32 cisr;
  27         u32 cimr;
  28         u32 ccosr;
  29         u32 cgpr;
  30         u32 ccgr0;
  31         u32 ccgr1;
  32         u32 ccgr2;
  33         u32 ccgr3;
  34         u32 ccgr4;
  35         u32 ccgr5;
  36         u32 ccgr6;
  37         u32 ccgr7;
  38         u32 ccgr8;
  39         u32 ccgr9;
  40         u32 ccgr10;
  41         u32 ccgr11;
  42         u32 cmeor0;
  43         u32 cmeor1;
  44         u32 cmeor2;
  45         u32 cmeor3;
  46         u32 cmeor4;
  47         u32 cmeor5;
  48         u32 cppdsr;
  49         u32 ccowr;
  50         u32 ccpgr0;
  51         u32 ccpgr1;
  52         u32 ccpgr2;
  53         u32 ccpgr3;
  54 };
  55
  56 /* Analog components control digital interface (ANADIG) */
  57 struct anadig_reg {
  58         u32 pll3_ctrl;
  59         u32 resv0[3];
  60         u32 pll7_ctrl;
  61         u32 resv1[3];
  62         u32 pll2_ctrl;
  63         u32 resv2[3];
  64         u32 pll2_ss;
  65         u32 resv3[3];
  66         u32 pll2_num;
  67         u32 resv4[3];
  68         u32 pll2_denom;
  69         u32 resv5[3];
  70         u32 pll4_ctrl;
  71         u32 resv6[3];
  72         u32 pll4_num;
  73         u32 resv7[3];
  74         u32 pll4_denom;
  75         u32 pll6_ctrl;
  76         u32 resv8[3];
  77         u32 pll6_num;
  78         u32 resv9[3];
  79         u32 pll6_denom;
  80         u32 resv10[3];
  81         u32 pll5_ctrl;
  82         u32 resv11[3];
  83         u32 pll3_pfd;
  84         u32 resv12[3];
  85         u32 pll2_pfd;
  86         u32 resv13[3];
  87         u32 reg_1p1;
  88         u32 resv14[3];
  89         u32 reg_3p0;
  90         u32 resv15[3];
  91         u32 reg_2p5;
  92         u32 resv16[7];
  93         u32 ana_misc0;
  94         u32 resv17[3];
  95         u32 ana_misc1;
  96         u32 resv18[63];
  97         u32 anadig_digprog;
  98         u32 resv19[3];
  99         u32 pll1_ctrl;
 100         u32 resv20[3];
 101         u32 pll1_ss;
 102         u32 resv21[3];
 103         u32 pll1_num;
 104         u32 resv22[3];
 105         u32 pll1_denom;
 106         u32 resv23[3];
 107         u32 pll1_pdf;
 108         u32 resv24[3];
 109         u32 pll_lock;
 110 };
 111 #endif
 112
 113 #define CCM_CCR_FIRC_EN                         (1 << 16)
 114 #define CCM_CCR_OSCNT_MASK                      0xff
 115 #define CCM_CCR_OSCNT(v)                        ((v) & 0xff)
 116
 117 #define CCM_CCSR_PLL2_PFD_CLK_SEL_OFFSET        19
 118 #define CCM_CCSR_PLL2_PFD_CLK_SEL_MASK          (0x7 << 19)
 119 #define CCM_CCSR_PLL2_PFD_CLK_SEL(v)            (((v) & 0x7) << 19)
 120
 121 #define CCM_CCSR_PLL1_PFD_CLK_SEL_OFFSET        16
 122 #define CCM_CCSR_PLL1_PFD_CLK_SEL_MASK          (0x7 << 16)
 123 #define CCM_CCSR_PLL1_PFD_CLK_SEL(v)            (((v) & 0x7) << 16)
 124
 125 #define CCM_CCSR_PLL2_PFD4_EN                   (1 << 15)
 126 #define CCM_CCSR_PLL2_PFD3_EN                   (1 << 14)
 127 #define CCM_CCSR_PLL2_PFD2_EN                   (1 << 13)
 128 #define CCM_CCSR_PLL2_PFD1_EN                   (1 << 12)
 129 #define CCM_CCSR_PLL1_PFD4_EN                   (1 << 11)
 130 #define CCM_CCSR_PLL1_PFD3_EN                   (1 << 10)
 131 #define CCM_CCSR_PLL1_PFD2_EN                   (1 << 9)
 132 #define CCM_CCSR_PLL1_PFD1_EN                   (1 << 8)
 133
 134 #define CCM_CCSR_DDRC_CLK_SEL(v)                ((v) << 6)
 135 #define CCM_CCSR_FAST_CLK_SEL(v)                ((v) << 5)
 136
 137 #define CCM_CCSR_SYS_CLK_SEL_OFFSET             0
 138 #define CCM_CCSR_SYS_CLK_SEL_MASK               0x7
 139 #define CCM_CCSR_SYS_CLK_SEL(v)                 ((v) & 0x7)
 140
 141 #define CCM_CACRR_IPG_CLK_DIV_OFFSET            11
 142 #define CCM_CACRR_IPG_CLK_DIV_MASK              (0x3 << 11)
 143 #define CCM_CACRR_IPG_CLK_DIV(v)                (((v) & 0x3) << 11)
 144 #define CCM_CACRR_BUS_CLK_DIV_OFFSET            3
 145 #define CCM_CACRR_BUS_CLK_DIV_MASK              (0x7 << 3)
 146 #define CCM_CACRR_BUS_CLK_DIV(v)                (((v) & 0x7) << 3)
 147 #define CCM_CACRR_ARM_CLK_DIV_OFFSET            0
 148 #define CCM_CACRR_ARM_CLK_DIV_MASK              0x7
 149 #define CCM_CACRR_ARM_CLK_DIV(v)                ((v) & 0x7)
 150
 151 #define CCM_CSCMR1_ESDHC1_CLK_SEL_OFFSET        18
 152 #define CCM_CSCMR1_ESDHC1_CLK_SEL_MASK          (0x3 << 18)
 153 #define CCM_CSCMR1_ESDHC1_CLK_SEL(v)            (((v) & 0x3) << 18)
 154
 155 #define CCM_CSCDR1_RMII_CLK_EN                  (1 << 24)
 156
 157 #define CCM_CSCDR2_ESDHC1_EN                    (1 << 29)
 158 #define CCM_CSCDR2_ESDHC1_CLK_DIV_OFFSET        20
 159 #define CCM_CSCDR2_ESDHC1_CLK_DIV_MASK          (0xf << 20)
 160 #define CCM_CSCDR2_ESDHC1_CLK_DIV(v)            (((v) & 0xf) << 20)
 161
 162 #define CCM_CSCMR2_RMII_CLK_SEL_OFFSET          4
 163 #define CCM_CSCMR2_RMII_CLK_SEL_MASK            (0x3 << 4)
 164 #define CCM_CSCMR2_RMII_CLK_SEL(v)              (((v) & 0x3) << 4)
 165
 166 #define CCM_REG_CTRL_MASK                       0xffffffff
 167 #define CCM_CCGR0_UART1_CTRL_MASK               (0x3 << 16)
 168 #define CCM_CCGR1_PIT_CTRL_MASK                 (0x3 << 14)
 169 #define CCM_CCGR1_WDOGA5_CTRL_MASK              (0x3 << 28)
 170 #define CCM_CCGR2_IOMUXC_CTRL_MASK              (0x3 << 16)
 171 #define CCM_CCGR2_PORTA_CTRL_MASK               (0x3 << 18)
 172 #define CCM_CCGR2_PORTB_CTRL_MASK               (0x3 << 20)
 173 #define CCM_CCGR2_PORTC_CTRL_MASK               (0x3 << 22)
 174 #define CCM_CCGR2_PORTD_CTRL_MASK               (0x3 << 24)
 175 #define CCM_CCGR2_PORTE_CTRL_MASK               (0x3 << 26)
 176 #define CCM_CCGR3_ANADIG_CTRL_MASK              0x3
 177 #define CCM_CCGR4_WKUP_CTRL_MASK                (0x3 << 20)
 178 #define CCM_CCGR4_CCM_CTRL_MASK                 (0x3 << 22)
 179 #define CCM_CCGR4_GPC_CTRL_MASK                 (0x3 << 24)
 180 #define CCM_CCGR4_I2C0_CTRL_MASK                (0x3 << 12)
 181 #define CCM_CCGR6_OCOTP_CTRL_MASK               (0x3 << 10)
 182 #define CCM_CCGR6_DDRMC_CTRL_MASK               (0x3 << 28)
 183 #define CCM_CCGR7_SDHC1_CTRL_MASK               (0x3 << 4)
 184 #define CCM_CCGR9_FEC0_CTRL_MASK                0x3
 185 #define CCM_CCGR9_FEC1_CTRL_MASK                (0x3 << 2)
 186
 187 #define ANADIG_PLL2_CTRL_ENABLE                 (1 << 13)
 188 #define ANADIG_PLL2_CTRL_POWERDOWN              (1 << 12)
 189 #define ANADIG_PLL2_CTRL_DIV_SELECT             1
 190 #define ANADIG_PLL1_CTRL_ENABLE                 (1 << 13)
 191 #define ANADIG_PLL1_CTRL_POWERDOWN              (1 << 12)
 192 #define ANADIG_PLL1_CTRL_DIV_SELECT             1
 193
 194 #define FASE_CLK_FREQ           24000000
 195 #define SLOW_CLK_FREQ           32000
 196 #define PLL1_PFD1_FREQ          500000000
 197 #define PLL1_PFD2_FREQ          452000000
 198 #define PLL1_PFD3_FREQ          396000000
 199 #define PLL1_PFD4_FREQ          528000000
 200 #define PLL1_MAIN_FREQ          528000000
 201 #define PLL2_PFD1_FREQ          500000000
 202 #define PLL2_PFD2_FREQ          396000000
 203 #define PLL2_PFD3_FREQ          339000000
 204 #define PLL2_PFD4_FREQ          413000000
 205 #define PLL2_MAIN_FREQ          528000000
 206 #define PLL3_MAIN_FREQ          480000000
 207 #define PLL3_PFD3_FREQ          298000000
 208 #define PLL5_MAIN_FREQ          500000000
 209
 210 #define ENET_EXTERNAL_CLK       50000000
 211 #define AUDIO_EXTERNAL_CLK      24576000
 212
 213 #endif /*__ARCH_ARM_MACH_VF610_CCM_REGS_H__ */