arch/arm/include/asm/imx-common/regs-gpmi.h

   1 /*
   2  * Freescale i.MX28 GPMI Register Definitions
   3  *
   4  * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
   5  * on behalf of DENX Software Engineering GmbH
   6  *
   7  * Based on code from LTIB:
   8  * Copyright 2008-2010 Freescale Semiconductor, Inc. All Rights Reserved.
   9  *
  10  * SPDX-License-Identifier:     GPL-2.0+
  11  */
  12
  13 #ifndef __MX28_REGS_GPMI_H__
  14 #define __MX28_REGS_GPMI_H__
  15
  16 #include <asm/imx-common/regs-common.h>
  17
  18 #ifndef __ASSEMBLY__
  19 struct gpmi_regs {
  20         mxs_reg_32(hw_gpmi_ctrl0);
  21         mxs_reg_32(hw_gpmi_compare);
  22         mxs_reg_32(hw_gpmi_eccctrl);
  23         mxs_reg_32(hw_gpmi_ecccount);
  24         mxs_reg_32(hw_gpmi_payload);
  25         mxs_reg_32(hw_gpmi_auxiliary);
  26         mxs_reg_32(hw_gpmi_ctrl1);
  27         mxs_reg_32(hw_gpmi_timing0);
  28         mxs_reg_32(hw_gpmi_timing1);
  29
  30         uint32_t        reserved[4];
  31
  32         mxs_reg_32(hw_gpmi_data);
  33         mxs_reg_32(hw_gpmi_stat);
  34         mxs_reg_32(hw_gpmi_debug);
  35         mxs_reg_32(hw_gpmi_version);
  36         mxs_reg_32(hw_gpmi_debug2);
  37         mxs_reg_32(hw_gpmi_debug3);
  38 };
  39 #endif
  40
  41 #define GPMI_BASE_ADDRESS                               MXS_GPMI_BASE
  42
  43 #define GPMI_CTRL0_SFTRST                               (1 << 31)
  44 #define GPMI_CTRL0_CLKGATE                              (1 << 30)
  45 #define GPMI_CTRL0_RUN                                  (1 << 29)
  46 #define GPMI_CTRL0_DEV_IRQ_EN                           (1 << 28)
  47 #define GPMI_CTRL0_LOCK_CS                              (1 << 27)
  48 #define GPMI_CTRL0_UDMA                                 (1 << 26)
  49 #define GPMI_CTRL0_COMMAND_MODE_MASK                    (0x3 << 24)
  50 #define GPMI_CTRL0_COMMAND_MODE_OFFSET                  24
  51 #define GPMI_CTRL0_COMMAND_MODE_WRITE                   (0x0 << 24)
  52 #define GPMI_CTRL0_COMMAND_MODE_READ                    (0x1 << 24)
  53 #define GPMI_CTRL0_COMMAND_MODE_READ_AND_COMPARE        (0x2 << 24)
  54 #define GPMI_CTRL0_COMMAND_MODE_WAIT_FOR_READY          (0x3 << 24)
  55 #define GPMI_CTRL0_WORD_LENGTH                          (1 << 23)
  56 #define GPMI_CTRL0_CS_MASK                              (0x7 << 20)
  57 #define GPMI_CTRL0_CS_OFFSET                            20
  58 #define GPMI_CTRL0_ADDRESS_MASK                         (0x7 << 17)
  59 #define GPMI_CTRL0_ADDRESS_OFFSET                       17
  60 #define GPMI_CTRL0_ADDRESS_NAND_DATA                    (0x0 << 17)
  61 #define GPMI_CTRL0_ADDRESS_NAND_CLE                     (0x1 << 17)
  62 #define GPMI_CTRL0_ADDRESS_NAND_ALE                     (0x2 << 17)
  63 #define GPMI_CTRL0_ADDRESS_INCREMENT                    (1 << 16)
  64 #define GPMI_CTRL0_XFER_COUNT_MASK                      0xffff
  65 #define GPMI_CTRL0_XFER_COUNT_OFFSET                    0
  66
  67 #define GPMI_COMPARE_MASK_MASK                          (0xffff << 16)
  68 #define GPMI_COMPARE_MASK_OFFSET                        16
  69 #define GPMI_COMPARE_REFERENCE_MASK                     0xffff
  70 #define GPMI_COMPARE_REFERENCE_OFFSET                   0
  71
  72 #define GPMI_ECCCTRL_HANDLE_MASK                        (0xffff << 16)
  73 #define GPMI_ECCCTRL_HANDLE_OFFSET                      16
  74 #define GPMI_ECCCTRL_ECC_CMD_MASK                       (0x3 << 13)
  75 #define GPMI_ECCCTRL_ECC_CMD_OFFSET                     13
  76 #define GPMI_ECCCTRL_ECC_CMD_DECODE                     (0x0 << 13)
  77 #define GPMI_ECCCTRL_ECC_CMD_ENCODE                     (0x1 << 13)
  78 #define GPMI_ECCCTRL_ENABLE_ECC                         (1 << 12)
  79 #define GPMI_ECCCTRL_BUFFER_MASK_MASK                   0x1ff
  80 #define GPMI_ECCCTRL_BUFFER_MASK_OFFSET                 0
  81 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_AUXONLY            0x100
  82 #define GPMI_ECCCTRL_BUFFER_MASK_BCH_PAGE               0x1ff
  83
  84 #define GPMI_ECCCOUNT_COUNT_MASK                        0xffff
  85 #define GPMI_ECCCOUNT_COUNT_OFFSET                      0
  86
  87 #define GPMI_PAYLOAD_ADDRESS_MASK                       (0x3fffffff << 2)
  88 #define GPMI_PAYLOAD_ADDRESS_OFFSET                     2
  89
  90 #define GPMI_AUXILIARY_ADDRESS_MASK                     (0x3fffffff << 2)
  91 #define GPMI_AUXILIARY_ADDRESS_OFFSET                   2
  92
  93 #define GPMI_CTRL1_DECOUPLE_CS                          (1 << 24)
  94 #define GPMI_CTRL1_WRN_DLY_SEL_MASK                     (0x3 << 22)
  95 #define GPMI_CTRL1_WRN_DLY_SEL_OFFSET                   22
  96 #define GPMI_CTRL1_TIMEOUT_IRQ_EN                       (1 << 20)
  97 #define GPMI_CTRL1_GANGED_RDYBUSY                       (1 << 19)
  98 #define GPMI_CTRL1_BCH_MODE                             (1 << 18)
  99 #define GPMI_CTRL1_DLL_ENABLE                           (1 << 17)
 100 #define GPMI_CTRL1_HALF_PERIOD                          (1 << 16)
 101 #define GPMI_CTRL1_RDN_DELAY_MASK                       (0xf << 12)
 102 #define GPMI_CTRL1_RDN_DELAY_OFFSET                     12
 103 #define GPMI_CTRL1_DMA2ECC_MODE                         (1 << 11)
 104 #define GPMI_CTRL1_DEV_IRQ                              (1 << 10)
 105 #define GPMI_CTRL1_TIMEOUT_IRQ                          (1 << 9)
 106 #define GPMI_CTRL1_BURST_EN                             (1 << 8)
 107 #define GPMI_CTRL1_ABORT_WAIT_REQUEST                   (1 << 7)
 108 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_MASK    (0x7 << 4)
 109 #define GPMI_CTRL1_ABORT_WAIT_FOR_READY_CHANNEL_OFFSET  4
 110 #define GPMI_CTRL1_DEV_RESET                            (1 << 3)
 111 #define GPMI_CTRL1_ATA_IRQRDY_POLARITY                  (1 << 2)
 112 #define GPMI_CTRL1_CAMERA_MODE                          (1 << 1)
 113 #define GPMI_CTRL1_GPMI_MODE                            (1 << 0)
 114
 115 #define GPMI_TIMING0_ADDRESS_SETUP_MASK                 (0xff << 16)
 116 #define GPMI_TIMING0_ADDRESS_SETUP_OFFSET               16
 117 #define GPMI_TIMING0_DATA_HOLD_MASK                     (0xff << 8)
 118 #define GPMI_TIMING0_DATA_HOLD_OFFSET                   8
 119 #define GPMI_TIMING0_DATA_SETUP_MASK                    0xff
 120 #define GPMI_TIMING0_DATA_SETUP_OFFSET                  0
 121
 122 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_MASK           (0xffff << 16)
 123 #define GPMI_TIMING1_DEVICE_BUSY_TIMEOUT_OFFSET         16
 124
 125 #define GPMI_TIMING2_UDMA_TRP_MASK                      (0xff << 24)
 126 #define GPMI_TIMING2_UDMA_TRP_OFFSET                    24
 127 #define GPMI_TIMING2_UDMA_ENV_MASK                      (0xff << 16)
 128 #define GPMI_TIMING2_UDMA_ENV_OFFSET                    16
 129 #define GPMI_TIMING2_UDMA_HOLD_MASK                     (0xff << 8)
 130 #define GPMI_TIMING2_UDMA_HOLD_OFFSET                   8
 131 #define GPMI_TIMING2_UDMA_SETUP_MASK                    0xff
 132 #define GPMI_TIMING2_UDMA_SETUP_OFFSET                  0
 133
 134 #define GPMI_DATA_DATA_MASK                             0xffffffff
 135 #define GPMI_DATA_DATA_OFFSET                           0
 136
 137 #define GPMI_STAT_READY_BUSY_MASK                       (0xff << 24)
 138 #define GPMI_STAT_READY_BUSY_OFFSET                     24
 139 #define GPMI_STAT_RDY_TIMEOUT_MASK                      (0xff << 16)
 140 #define GPMI_STAT_RDY_TIMEOUT_OFFSET                    16
 141 #define GPMI_STAT_DEV7_ERROR                            (1 << 15)
 142 #define GPMI_STAT_DEV6_ERROR                            (1 << 14)
 143 #define GPMI_STAT_DEV5_ERROR                            (1 << 13)
 144 #define GPMI_STAT_DEV4_ERROR                            (1 << 12)
 145 #define GPMI_STAT_DEV3_ERROR                            (1 << 11)
 146 #define GPMI_STAT_DEV2_ERROR                            (1 << 10)
 147 #define GPMI_STAT_DEV1_ERROR                            (1 << 9)
 148 #define GPMI_STAT_DEV0_ERROR                            (1 << 8)
 149 #define GPMI_STAT_ATA_IRQ                               (1 << 4)
 150 #define GPMI_STAT_INVALID_BUFFER_MASK                   (1 << 3)
 151 #define GPMI_STAT_FIFO_EMPTY                            (1 << 2)
 152 #define GPMI_STAT_FIFO_FULL                             (1 << 1)
 153 #define GPMI_STAT_PRESENT                               (1 << 0)
 154
 155 #define GPMI_DEBUG_WAIT_FOR_READY_END_MASK              (0xff << 24)
 156 #define GPMI_DEBUG_WAIT_FOR_READY_END_OFFSET            24
 157 #define GPMI_DEBUG_DMA_SENSE_MASK                       (0xff << 16)
 158 #define GPMI_DEBUG_DMA_SENSE_OFFSET                     16
 159 #define GPMI_DEBUG_DMAREQ_MASK                          (0xff << 8)
 160 #define GPMI_DEBUG_DMAREQ_OFFSET                        8
 161 #define GPMI_DEBUG_CMD_END_MASK                         0xff
 162 #define GPMI_DEBUG_CMD_END_OFFSET                       0
 163
 164 #define GPMI_VERSION_MAJOR_MASK                         (0xff << 24)
 165 #define GPMI_VERSION_MAJOR_OFFSET                       24
 166 #define GPMI_VERSION_MINOR_MASK                         (0xff << 16)
 167 #define GPMI_VERSION_MINOR_OFFSET                       16
 168 #define GPMI_VERSION_STEP_MASK                          0xffff
 169 #define GPMI_VERSION_STEP_OFFSET                        0
 170
 171 #define GPMI_DEBUG2_UDMA_STATE_MASK                     (0xf << 24)
 172 #define GPMI_DEBUG2_UDMA_STATE_OFFSET                   24
 173 #define GPMI_DEBUG2_BUSY                                (1 << 23)
 174 #define GPMI_DEBUG2_PIN_STATE_MASK                      (0x7 << 20)
 175 #define GPMI_DEBUG2_PIN_STATE_OFFSET                    20
 176 #define GPMI_DEBUG2_PIN_STATE_PSM_IDLE                  (0x0 << 20)
 177 #define GPMI_DEBUG2_PIN_STATE_PSM_BYTCNT                (0x1 << 20)
 178 #define GPMI_DEBUG2_PIN_STATE_PSM_ADDR                  (0x2 << 20)
 179 #define GPMI_DEBUG2_PIN_STATE_PSM_STALL                 (0x3 << 20)
 180 #define GPMI_DEBUG2_PIN_STATE_PSM_STROBE                (0x4 << 20)
 181 #define GPMI_DEBUG2_PIN_STATE_PSM_ATARDY                (0x5 << 20)
 182 #define GPMI_DEBUG2_PIN_STATE_PSM_DHOLD                 (0x6 << 20)
 183 #define GPMI_DEBUG2_PIN_STATE_PSM_DONE                  (0x7 << 20)
 184 #define GPMI_DEBUG2_MAIN_STATE_MASK                     (0xf << 16)
 185 #define GPMI_DEBUG2_MAIN_STATE_OFFSET                   16
 186 #define GPMI_DEBUG2_MAIN_STATE_MSM_IDLE                 (0x0 << 16)
 187 #define GPMI_DEBUG2_MAIN_STATE_MSM_BYTCNT               (0x1 << 16)
 188 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFE               (0x2 << 16)
 189 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFR               (0x3 << 16)
 190 #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAREQ               (0x4 << 16)
 191 #define GPMI_DEBUG2_MAIN_STATE_MSM_DMAACK               (0x5 << 16)
 192 #define GPMI_DEBUG2_MAIN_STATE_MSM_WAITFF               (0x6 << 16)
 193 #define GPMI_DEBUG2_MAIN_STATE_MSM_LDFIFO               (0x7 << 16)
 194 #define GPMI_DEBUG2_MAIN_STATE_MSM_LDDMAR               (0x8 << 16)
 195 #define GPMI_DEBUG2_MAIN_STATE_MSM_RDCMP                (0x9 << 16)
 196 #define GPMI_DEBUG2_MAIN_STATE_MSM_DONE                 (0xa << 16)
 197 #define GPMI_DEBUG2_SYND2GPMI_BE_MASK                   (0xf << 12)
 198 #define GPMI_DEBUG2_SYND2GPMI_BE_OFFSET                 12
 199 #define GPMI_DEBUG2_GPMI2SYND_VALID                     (1 << 11)
 200 #define GPMI_DEBUG2_GPMI2SYND_READY                     (1 << 10)
 201 #define GPMI_DEBUG2_SYND2GPMI_VALID                     (1 << 9)
 202 #define GPMI_DEBUG2_SYND2GPMI_READY                     (1 << 8)
 203 #define GPMI_DEBUG2_VIEW_DELAYED_RDN                    (1 << 7)
 204 #define GPMI_DEBUG2_UPDATE_WINDOW                       (1 << 6)
 205 #define GPMI_DEBUG2_RDN_TAP_MASK                        0x3f
 206 #define GPMI_DEBUG2_RDN_TAP_OFFSET                      0
 207
 208 #define GPMI_DEBUG3_APB_WORD_CNTR_MASK                  (0xffff << 16)
 209 #define GPMI_DEBUG3_APB_WORD_CNTR_OFFSET                16
 210 #define GPMI_DEBUG3_DEV_WORD_CNTR_MASK                  0xffff
 211 #define GPMI_DEBUG3_DEV_WORD_CNTR_OFFSET                0
 212
 213 #endif  /* __MX28_REGS_GPMI_H__ */