arch/blackfin/cpu/cpu.c

   1 /*
   2  * U-boot - cpu.c CPU specific functions
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * (C) Copyright 2000-2004
   7  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   8  *
   9  * Licensed under the GPL-2 or later.
  10  */
  11
  12 #include <common.h>
  13 #include <command.h>
  14 #include <asm/blackfin.h>
  15 #include <asm/cplb.h>
  16 #include <asm/mach-common/bits/core.h>
  17 #include <asm/mach-common/bits/ebiu.h>
  18 #include <asm/mach-common/bits/trace.h>
  19
  20 #include "cpu.h"
  21 #include "serial.h"
  22 #include "initcode.h"
  23
  24 ulong bfin_poweron_retx;
  25
  26 void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
  27 {
  28 #ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
  29         /* Build a NOP slide over the LDR jump block.  Whee! */
  30         char nops[0xC];
  31         serial_early_puts("NOP Slide\n");
  32         memset(nops, 0x00, sizeof(nops));
  33         memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
  34 #endif
  35
  36         if (!loaded_from_ldr) {
  37                 /* Relocate sections into L1 if the LDR didn't do it -- don't
  38                  * check length because the linker script does the size
  39                  * checking at build time.
  40                  */
  41                 serial_early_puts("L1 Relocate\n");
  42                 extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
  43                 memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
  44                 extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
  45                 memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
  46         }
  47
  48         /*
  49          * Make sure our async settings are committed.  Some bootroms
  50          * (like the BF537) will reset some registers on us after it
  51          * has finished loading the LDR.  Or if we're booting over
  52          * JTAG, the initcode never got a chance to run.  Or if we
  53          * aren't booting from parallel flash, the initcode skipped
  54          * this step completely.
  55          */
  56         program_async_controller(NULL);
  57
  58         /* Save RETX so we can pass it while booting Linux */
  59         bfin_poweron_retx = bootflag;
  60
  61 #ifdef CONFIG_DEBUG_DUMP
  62         /* Turn on hardware trace buffer */
  63         bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
  64 #endif
  65
  66 #ifndef CONFIG_PANIC_HANG
  67         /* Reset upon a double exception rather than just hanging.
  68          * Do not do bfin_read on SWRST as that will reset status bits.
  69          */
  70 # ifdef SWRST
  71         bfin_write_SWRST(DOUBLE_FAULT);
  72 # endif
  73 #endif
  74
  75         serial_early_puts("Board init flash\n");
  76         board_init_f(bootflag);
  77 }
  78
  79 int exception_init(void)
  80 {
  81         bfin_write_EVT3(trap);
  82         return 0;
  83 }
  84
  85 int irq_init(void)
  86 {
  87 #ifdef SIC_IMASK0
  88         bfin_write_SIC_IMASK0(0);
  89         bfin_write_SIC_IMASK1(0);
  90 # ifdef SIC_IMASK2
  91         bfin_write_SIC_IMASK2(0);
  92 # endif
  93 #elif defined(SICA_IMASK0)
  94         bfin_write_SICA_IMASK0(0);
  95         bfin_write_SICA_IMASK1(0);
  96 #elif defined(SIC_IMASK)
  97         bfin_write_SIC_IMASK(0);
  98 #endif
  99         /* Set up a dummy NMI handler if needed.  */
 100         if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
 101                 bfin_write_EVT2(evt_nmi);       /* NMI */
 102         bfin_write_EVT5(evt_default);   /* hardware error */
 103         bfin_write_EVT6(evt_default);   /* core timer */
 104         bfin_write_EVT7(evt_default);
 105         bfin_write_EVT8(evt_default);
 106         bfin_write_EVT9(evt_default);
 107         bfin_write_EVT10(evt_default);
 108         bfin_write_EVT11(evt_default);
 109         bfin_write_EVT12(evt_default);
 110         bfin_write_EVT13(evt_default);
 111         bfin_write_EVT14(evt_default);
 112         bfin_write_EVT15(evt_default);
 113         bfin_write_ILAT(0);
 114         CSYNC();
 115         /* enable hardware error irq */
 116         irq_flags = 0x3f;
 117         local_irq_enable();
 118         return 0;
 119 }