arch/blackfin/cpu/initcode.h

   1 /*
   2  * Code for early processor initialization
   3  *
   4  * Copyright (c) 2004-2011 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #ifndef __BFIN_INITCODE_H__
  10 #define __BFIN_INITCODE_H__
  11
  12 #include <asm/mach-common/bits/bootrom.h>
  13
  14 #ifndef BFIN_IN_INITCODE
  15 # define serial_putc(c)
  16 #endif
  17
  18 #ifndef __ADSPBF60x__
  19
  20 #ifndef CONFIG_EBIU_RSTCTL_VAL
  21 # define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
  22 #endif
  23 #if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
  24 # error invalid EBIU_RSTCTL value: must not set reserved bits
  25 #endif
  26
  27 #ifndef CONFIG_EBIU_MBSCTL_VAL
  28 # define CONFIG_EBIU_MBSCTL_VAL 0
  29 #endif
  30
  31 #if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
  32 # error invalid EBIU_DDRQUE value: must not set reserved bits
  33 #endif
  34
  35 #endif /* __ADSPBF60x__ */
  36
  37 __attribute__((always_inline)) static inline void
  38 program_async_controller(ADI_BOOT_DATA *bs)
  39 {
  40 #ifdef BFIN_IN_INITCODE
  41         /*
  42          * We really only need to setup the async banks early if we're
  43          * booting out of it.  Otherwise, do it later on in cpu_init.
  44          */
  45         if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
  46             CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
  47                 return;
  48 #endif
  49
  50         serial_putc('a');
  51
  52 #ifdef __ADSPBF60x__
  53         /* Program the async banks controller. */
  54 #ifdef EBIU_AMGCTL
  55         bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
  56         bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
  57         bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
  58 #endif
  59
  60         serial_putc('b');
  61
  62         /* Not all parts have these additional MMRs. */
  63 #ifdef EBIU_MBSCTL
  64         bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
  65 #endif
  66 #ifdef EBIU_MODE
  67 # ifdef CONFIG_EBIU_MODE_VAL
  68         bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
  69 # endif
  70 # ifdef CONFIG_EBIU_FCTL_VAL
  71         bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
  72 # endif
  73 #endif
  74
  75         serial_putc('c');
  76
  77 #else   /* __ADSPBF60x__ */
  78         /* Program the static memory controller. */
  79 # ifdef CONFIG_SMC_GCTL_VAL
  80         bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
  81 # endif
  82 # ifdef CONFIG_SMC_B0CTL_VAL
  83         bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
  84 # endif
  85 # ifdef CONFIG_SMC_B0TIM_VAL
  86         bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
  87 # endif
  88 # ifdef CONFIG_SMC_B0ETIM_VAL
  89         bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
  90 # endif
  91 # ifdef CONFIG_SMC_B1CTL_VAL
  92         bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
  93 # endif
  94 # ifdef CONFIG_SMC_B1TIM_VAL
  95         bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
  96 # endif
  97 # ifdef CONFIG_SMC_B1ETIM_VAL
  98         bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
  99 # endif
 100 # ifdef CONFIG_SMC_B2CTL_VAL
 101         bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
 102 # endif
 103 # ifdef CONFIG_SMC_B2TIM_VAL
 104         bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
 105 # endif
 106 # ifdef CONFIG_SMC_B2ETIM_VAL
 107         bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
 108 # endif
 109 # ifdef CONFIG_SMC_B3CTL_VAL
 110         bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
 111 # endif
 112 # ifdef CONFIG_SMC_B3TIM_VAL
 113         bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
 114 # endif
 115 # ifdef CONFIG_SMC_B3ETIM_VAL
 116         bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
 117 # endif
 118
 119 #endif
 120         serial_putc('d');
 121 }
 122
 123 #endif