arch/blackfin/include/asm/mach-bf561/BF561_def.h

   1 /* DO NOT EDIT THIS FILE
   2  * Automatically generated by generate-def-headers.xsl
   3  * DO NOT EDIT THIS FILE
   4  */
   5
   6 #ifndef __BFIN_DEF_ADSP_BF561_proc__
   7 #define __BFIN_DEF_ADSP_BF561_proc__
   8
   9 #include "../mach-common/ADSP-EDN-core_def.h"
  10
  11 #include "../mach-common/ADSP-EDN-DUAL-CORE-extended_def.h"
  12
  13 #define SRAM_BASE_ADDR                 0xFFE00000
  14 #define DMEM_CONTROL                   0xFFE00004
  15 #define DCPLB_STATUS                   0xFFE00008
  16 #define DCPLB_FAULT_ADDR               0xFFE0000C
  17 #define DCPLB_ADDR0                    0xFFE00100
  18 #define DCPLB_ADDR1                    0xFFE00104
  19 #define DCPLB_ADDR2                    0xFFE00108
  20 #define DCPLB_ADDR3                    0xFFE0010C
  21 #define DCPLB_ADDR4                    0xFFE00110
  22 #define DCPLB_ADDR5                    0xFFE00114
  23 #define DCPLB_ADDR6                    0xFFE00118
  24 #define DCPLB_ADDR7                    0xFFE0011C
  25 #define DCPLB_ADDR8                    0xFFE00120
  26 #define DCPLB_ADDR9                    0xFFE00124
  27 #define DCPLB_ADDR10                   0xFFE00128
  28 #define DCPLB_ADDR11                   0xFFE0012C
  29 #define DCPLB_ADDR12                   0xFFE00130
  30 #define DCPLB_ADDR13                   0xFFE00134
  31 #define DCPLB_ADDR14                   0xFFE00138
  32 #define DCPLB_ADDR15                   0xFFE0013C
  33 #define DCPLB_DATA0                    0xFFE00200
  34 #define DCPLB_DATA1                    0xFFE00204
  35 #define DCPLB_DATA2                    0xFFE00208
  36 #define DCPLB_DATA3                    0xFFE0020C
  37 #define DCPLB_DATA4                    0xFFE00210
  38 #define DCPLB_DATA5                    0xFFE00214
  39 #define DCPLB_DATA6                    0xFFE00218
  40 #define DCPLB_DATA7                    0xFFE0021C
  41 #define DCPLB_DATA8                    0xFFE00220
  42 #define DCPLB_DATA9                    0xFFE00224
  43 #define DCPLB_DATA10                   0xFFE00228
  44 #define DCPLB_DATA11                   0xFFE0022C
  45 #define DCPLB_DATA12                   0xFFE00230
  46 #define DCPLB_DATA13                   0xFFE00234
  47 #define DCPLB_DATA14                   0xFFE00238
  48 #define DCPLB_DATA15                   0xFFE0023C
  49 #define DTEST_COMMAND                  0xFFE00300
  50 #define DTEST_DATA0                    0xFFE00400
  51 #define DTEST_DATA1                    0xFFE00404
  52 #define IMEM_CONTROL                   0xFFE01004
  53 #define ICPLB_STATUS                   0xFFE01008
  54 #define ICPLB_FAULT_ADDR               0xFFE0100C
  55 #define ICPLB_ADDR0                    0xFFE01100
  56 #define ICPLB_ADDR1                    0xFFE01104
  57 #define ICPLB_ADDR2                    0xFFE01108
  58 #define ICPLB_ADDR3                    0xFFE0110C
  59 #define ICPLB_ADDR4                    0xFFE01110
  60 #define ICPLB_ADDR5                    0xFFE01114
  61 #define ICPLB_ADDR6                    0xFFE01118
  62 #define ICPLB_ADDR7                    0xFFE0111C
  63 #define ICPLB_ADDR8                    0xFFE01120
  64 #define ICPLB_ADDR9                    0xFFE01124
  65 #define ICPLB_ADDR10                   0xFFE01128
  66 #define ICPLB_ADDR11                   0xFFE0112C
  67 #define ICPLB_ADDR12                   0xFFE01130
  68 #define ICPLB_ADDR13                   0xFFE01134
  69 #define ICPLB_ADDR14                   0xFFE01138
  70 #define ICPLB_ADDR15                   0xFFE0113C
  71 #define ICPLB_DATA0                    0xFFE01200
  72 #define ICPLB_DATA1                    0xFFE01204
  73 #define ICPLB_DATA2                    0xFFE01208
  74 #define ICPLB_DATA3                    0xFFE0120C
  75 #define ICPLB_DATA4                    0xFFE01210
  76 #define ICPLB_DATA5                    0xFFE01214
  77 #define ICPLB_DATA6                    0xFFE01218
  78 #define ICPLB_DATA7                    0xFFE0121C
  79 #define ICPLB_DATA8                    0xFFE01220
  80 #define ICPLB_DATA9                    0xFFE01224
  81 #define ICPLB_DATA10                   0xFFE01228
  82 #define ICPLB_DATA11                   0xFFE0122C
  83 #define ICPLB_DATA12                   0xFFE01230
  84 #define ICPLB_DATA13                   0xFFE01234
  85 #define ICPLB_DATA14                   0xFFE01238
  86 #define ICPLB_DATA15                   0xFFE0123C
  87 #define ITEST_COMMAND                  0xFFE01300
  88 #define ITEST_DATA0                    0xFFE01400
  89 #define ITEST_DATA1                    0xFFE01404
  90 #define SICA_SWRST                     0xFFC00100
  91 #define SICA_SYSCR                     0xFFC00104
  92 #define SICA_RVECT                     0xFFC00108
  93 #define SICA_IMASK0                    0xFFC0010C
  94 #define SICA_IMASK1                    0xFFC00110
  95 #define SICA_ISR0                      0xFFC00114
  96 #define SICA_ISR1                      0xFFC00118
  97 #define SICA_IWR0                      0xFFC0011C
  98 #define SICA_IWR1                      0xFFC00120
  99 #define SICA_IAR0                      0xFFC00124
 100 #define SICA_IAR1                      0xFFC00128
 101 #define SICA_IAR2                      0xFFC0012C
 102 #define SICA_IAR3                      0xFFC00130
 103 #define SICA_IAR4                      0xFFC00134
 104 #define SICA_IAR5                      0xFFC00138
 105 #define SICA_IAR6                      0xFFC0013C
 106 #define SICA_IAR7                      0xFFC00140
 107 #define SICB_SWRST                     0xFFC01100
 108 #define SICB_SYSCR                     0xFFC01104
 109 #define SICB_RVECT                     0xFFC01108
 110 #define SICB_IMASK0                    0xFFC0110C
 111 #define SICB_IMASK1                    0xFFC01110
 112 #define SICB_ISR0                      0xFFC01114
 113 #define SICB_ISR1                      0xFFC01118
 114 #define SICB_IWR0                      0xFFC0111C
 115 #define SICB_IWR1                      0xFFC01120
 116 #define SICB_IAR0                      0xFFC01124
 117 #define SICB_IAR1                      0xFFC01128
 118 #define SICB_IAR2                      0xFFC0112C
 119 #define SICB_IAR3                      0xFFC01130
 120 #define SICB_IAR4                      0xFFC01134
 121 #define SICB_IAR5                      0xFFC01138
 122 #define SICB_IAR6                      0xFFC0113C
 123 #define SICB_IAR7                      0xFFC01140
 124 #define PPI0_CONTROL                   0xFFC01000
 125 #define PPI0_STATUS                    0xFFC01004
 126 #define PPI0_DELAY                     0xFFC0100C
 127 #define PPI0_COUNT                     0xFFC01008
 128 #define PPI0_FRAME                     0xFFC01010
 129 #define PPI1_CONTROL                   0xFFC01300
 130 #define PPI1_STATUS                    0xFFC01304
 131 #define PPI1_DELAY                     0xFFC0130C
 132 #define PPI1_COUNT                     0xFFC01308
 133 #define PPI1_FRAME                     0xFFC01310
 134 #define TBUFCTL                        0xFFE06000
 135 #define TBUFSTAT                       0xFFE06004
 136 #define TBUF                           0xFFE06100
 137 #define PFCTL                          0xFFE08000
 138 #define PFCNTR0                        0xFFE08100
 139 #define PFCNTR1                        0xFFE08104
 140 #define SRAM_BASE_ADDR_CORE_A          0xFFE00000
 141 #define SRAM_BASE_ADDR_CORE_B          0xFFE00000
 142 #define EVT_OVERRIDE                   0xFFE02100
 143 #define UART_THR                       0xFFC00400
 144 #define UART_RBR                       0xFFC00400
 145 #define UART_DLL                       0xFFC00400
 146 #define UART_DLH                       0xFFC00404
 147 #define UART_IER                       0xFFC00404
 148 #define UART_IIR                       0xFFC00408
 149 #define UART_LCR                       0xFFC0040C
 150 #define UART_MCR                       0xFFC00410
 151 #define UART_LSR                       0xFFC00414
 152 #define UART_MSR                       0xFFC00418
 153 #define UART_SCR                       0xFFC0041C
 154 #define UART_GCTL                      0xFFC00424
 155 #define UART_GBL                       0xFFC00424
 156 #define EBIU_AMGCTL                    0xFFC00A00
 157 #define EBIU_AMBCTL0                   0xFFC00A04
 158 #define EBIU_AMBCTL1                   0xFFC00A08
 159 #define EBIU_SDGCTL                    0xFFC00A10
 160 #define EBIU_SDBCTL                    0xFFC00A14
 161 #define EBIU_SDRRC                     0xFFC00A18
 162 #define EBIU_SDSTAT                    0xFFC00A1C
 163 #define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA03FFF Instruction Bank A SRAM */
 164 #define L1_INST_SRAM_SIZE (0xFFA03FFF - 0xFFA00000 + 1)
 165 #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
 166 #define L1_SRAM_SCRATCH 0xFFB00000 /* 0xFFB00000 -> 0xFFB00FFF Scratchpad SRAM */
 167 #define L1_SRAM_SCRATCH_SIZE (0xFFB00FFF - 0xFFB00000 + 1)
 168 #define L1_SRAM_SCRATCH_END (L1_SRAM_SCRATCH + L1_SRAM_SCRATCH_SIZE)
 169 #define SYSMMR_BASE 0xFFC00000 /* 0xFFC00000 -> 0xFFFFFFFF MMR registers */
 170 #define SYSMMR_BASE_SIZE (0xFFFFFFFF - 0xFFC00000 + 1)
 171 #define SYSMMR_BASE_END (SYSMMR_BASE + SYSMMR_BASE_SIZE)
 172
 173 #endif /* __BFIN_DEF_ADSP_BF561_proc__ */