1 /* DO NOT EDIT THIS FILE
2 * Automatically generated by generate-def-headers.xsl
3 * DO NOT EDIT THIS FILE
6 #ifndef __BFIN_DEF_ADSP_EDN_extended__
7 #define __BFIN_DEF_ADSP_EDN_extended__
9 #define ILAT 0xFFE0210C /* Interrupt Latch Register */
10 #define IMASK 0xFFE02104 /* Interrupt Mask Register */
11 #define IPEND 0xFFE02108 /* Interrupt Pending Register */
12 #define IPRIO 0xFFE02110 /* Interrupt Priority Register */
13 #define TCNTL 0xFFE03000 /* Core Timer Control Register */
14 #define TPERIOD 0xFFE03004 /* Core Timer Period Register */
15 #define TSCALE 0xFFE03008 /* Core Timer Scale Register */
16 #define TCOUNT 0xFFE0300C /* Core Timer Count Register */
17 #define SRAM_BASE_ADDR 0xFFE00000 /* SRAM Base Address (Read Only) */
18 #define DMEM_CONTROL 0xFFE00004 /* Data memory control */
19 #define DCPLB_FAULT_STATUS 0xFFE00008 /* L1 Data Memory Controller Register */
20 #define DCPLB_FAULT_ADDR 0xFFE0000C
21 #define DCPLB_ADDR0 0xFFE00100 /* Data Cache Protection Lookaside Buffer 0 */
22 #define DCPLB_ADDR1 0xFFE00104 /* Data Cache Protection Lookaside Buffer 1 */
23 #define DCPLB_ADDR2 0xFFE00108 /* Data Cache Protection Lookaside Buffer 2 */
24 #define DCPLB_ADDR3 0xFFE0010C /* Data Cache Protection Lookaside Buffer 3 */
25 #define DCPLB_ADDR4 0xFFE00110 /* Data Cache Protection Lookaside Buffer 4 */
26 #define DCPLB_ADDR5 0xFFE00114 /* Data Cache Protection Lookaside Buffer 5 */
27 #define DCPLB_ADDR6 0xFFE00118 /* Data Cache Protection Lookaside Buffer 6 */
28 #define DCPLB_ADDR7 0xFFE0011C /* Data Cache Protection Lookaside Buffer 7 */
29 #define DCPLB_ADDR8 0xFFE00120 /* Data Cache Protection Lookaside Buffer 8 */
30 #define DCPLB_ADDR9 0xFFE00124 /* Data Cache Protection Lookaside Buffer 9 */
31 #define DCPLB_ADDR10 0xFFE00128 /* Data Cache Protection Lookaside Buffer 10 */
32 #define DCPLB_ADDR11 0xFFE0012C /* Data Cache Protection Lookaside Buffer 11 */
33 #define DCPLB_ADDR12 0xFFE00130 /* Data Cache Protection Lookaside Buffer 12 */
34 #define DCPLB_ADDR13 0xFFE00134 /* Data Cache Protection Lookaside Buffer 13 */
35 #define DCPLB_ADDR14 0xFFE00138 /* Data Cache Protection Lookaside Buffer 14 */
36 #define DCPLB_ADDR15 0xFFE0013C /* Data Cache Protection Lookaside Buffer 15 */
37 #define DCPLB_DATA0 0xFFE00200 /* Data Cache 0 Status */
38 #define DCPLB_DATA1 0xFFE00204 /* Data Cache 1 Status */
39 #define DCPLB_DATA2 0xFFE00208 /* Data Cache 2 Status */
40 #define DCPLB_DATA3 0xFFE0020C /* Data Cache 3 Status */
41 #define DCPLB_DATA4 0xFFE00210 /* Data Cache 4 Status */
42 #define DCPLB_DATA5 0xFFE00214 /* Data Cache 5 Status */
43 #define DCPLB_DATA6 0xFFE00218 /* Data Cache 6 Status */
44 #define DCPLB_DATA7 0xFFE0021C /* Data Cache 7 Status */
45 #define DCPLB_DATA8 0xFFE00220 /* Data Cache 8 Status */
46 #define DCPLB_DATA9 0xFFE00224 /* Data Cache 9 Status */
47 #define DCPLB_DATA10 0xFFE00228 /* Data Cache 10 Status */
48 #define DCPLB_DATA11 0xFFE0022C /* Data Cache 11 Status */
49 #define DCPLB_DATA12 0xFFE00230 /* Data Cache 12 Status */
50 #define DCPLB_DATA13 0xFFE00234 /* Data Cache 13 Status */
51 #define DCPLB_DATA14 0xFFE00238 /* Data Cache 14 Status */
52 #define DCPLB_DATA15 0xFFE0023C /* Data Cache 15 Status */
53 #define DTEST_COMMAND 0xFFE00300 /* Data Test Command Register */
54 #define DTEST_DATA0 0xFFE00400 /* Data Test Data Register */
55 #define DTEST_DATA1 0xFFE00404 /* Data Test Data Register */
56 #define EVT0 0xFFE02000 /* Event Vector 0 ESR Address */
57 #define EVT1 0xFFE02004 /* Event Vector 1 ESR Address */
58 #define EVT2 0xFFE02008 /* Event Vector 2 ESR Address */
59 #define EVT3 0xFFE0200C /* Event Vector 3 ESR Address */
60 #define EVT4 0xFFE02010 /* Event Vector 4 ESR Address */
61 #define EVT5 0xFFE02014 /* Event Vector 5 ESR Address */
62 #define EVT6 0xFFE02018 /* Event Vector 6 ESR Address */
63 #define EVT7 0xFFE0201C /* Event Vector 7 ESR Address */
64 #define EVT8 0xFFE02020 /* Event Vector 8 ESR Address */
65 #define EVT9 0xFFE02024 /* Event Vector 9 ESR Address */
66 #define EVT10 0xFFE02028 /* Event Vector 10 ESR Address */
67 #define EVT11 0xFFE0202C /* Event Vector 11 ESR Address */
68 #define EVT12 0xFFE02030 /* Event Vector 12 ESR Address */
69 #define EVT13 0xFFE02034 /* Event Vector 13 ESR Address */
70 #define EVT14 0xFFE02038 /* Event Vector 14 ESR Address */
71 #define EVT15 0xFFE0203C /* Event Vector 15 ESR Address */
72 #define IMEM_CONTROL 0xFFE01004 /* Instruction Memory Control */
73 #define ICPLB_FAULT_STATUS 0xFFE01008
74 #define ICPLB_FAULT_ADDR 0xFFE0100C
75 #define ICPLB_ADDR0 0xFFE01100 /* Instruction Cacheability Protection Lookaside Buffer 0 */
76 #define ICPLB_ADDR1 0xFFE01104 /* Instruction Cacheability Protection Lookaside Buffer 1 */
77 #define ICPLB_ADDR2 0xFFE01108 /* Instruction Cacheability Protection Lookaside Buffer 2 */
78 #define ICPLB_ADDR3 0xFFE0110C /* Instruction Cacheability Protection Lookaside Buffer 3 */
79 #define ICPLB_ADDR4 0xFFE01110 /* Instruction Cacheability Protection Lookaside Buffer 4 */
80 #define ICPLB_ADDR5 0xFFE01114 /* Instruction Cacheability Protection Lookaside Buffer 5 */
81 #define ICPLB_ADDR6 0xFFE01118 /* Instruction Cacheability Protection Lookaside Buffer 6 */
82 #define ICPLB_ADDR7 0xFFE0111C /* Instruction Cacheability Protection Lookaside Buffer 7 */
83 #define ICPLB_ADDR8 0xFFE01120 /* Instruction Cacheability Protection Lookaside Buffer 8 */
84 #define ICPLB_ADDR9 0xFFE01124 /* Instruction Cacheability Protection Lookaside Buffer 9 */
85 #define ICPLB_ADDR10 0xFFE01128 /* Instruction Cacheability Protection Lookaside Buffer 10 */
86 #define ICPLB_ADDR11 0xFFE0112C /* Instruction Cacheability Protection Lookaside Buffer 11 */
87 #define ICPLB_ADDR12 0xFFE01130 /* Instruction Cacheability Protection Lookaside Buffer 12 */
88 #define ICPLB_ADDR13 0xFFE01134 /* Instruction Cacheability Protection Lookaside Buffer 13 */
89 #define ICPLB_ADDR14 0xFFE01138 /* Instruction Cacheability Protection Lookaside Buffer 14 */
90 #define ICPLB_ADDR15 0xFFE0113C /* Instruction Cacheability Protection Lookaside Buffer 15 */
91 #define ICPLB_DATA0 0xFFE01200 /* Instruction Cache 0 Status */
92 #define ICPLB_DATA1 0xFFE01204 /* Instruction Cache 1 Status */
93 #define ICPLB_DATA2 0xFFE01208 /* Instruction Cache 2 Status */
94 #define ICPLB_DATA3 0xFFE0120C /* Instruction Cache 3 Status */
95 #define ICPLB_DATA4 0xFFE01210 /* Instruction Cache 4 Status */
96 #define ICPLB_DATA5 0xFFE01214 /* Instruction Cache 5 Status */
97 #define ICPLB_DATA6 0xFFE01218 /* Instruction Cache 6 Status */
98 #define ICPLB_DATA7 0xFFE0121C /* Instruction Cache 7 Status */
99 #define ICPLB_DATA8 0xFFE01220 /* Instruction Cache 8 Status */
100 #define ICPLB_DATA9 0xFFE01224 /* Instruction Cache 9 Status */
101 #define ICPLB_DATA10 0xFFE01228 /* Instruction Cache 10 Status */
102 #define ICPLB_DATA11 0xFFE0122C /* Instruction Cache 11 Status */
103 #define ICPLB_DATA12 0xFFE01230 /* Instruction Cache 12 Status */
104 #define ICPLB_DATA13 0xFFE01234 /* Instruction Cache 13 Status */
105 #define ICPLB_DATA14 0xFFE01238 /* Instruction Cache 14 Status */
106 #define ICPLB_DATA15 0xFFE0123C /* Instruction Cache 15 Status */
107 #define ITEST_COMMAND 0xFFE01300 /* Instruction Test Command Register */
108 #define ITEST_DATA0 0xFFE01400 /* Instruction Test Data Register */
109 #define ITEST_DATA1 0xFFE01404 /* Instruction Test Data Register */
110 #define MDMAFLX0_DMACNFG_D 0xFFC00E08
111 #define MDMAFLX0_XCOUNT_D 0xFFC00E10
112 #define MDMAFLX0_XMODIFY_D 0xFFC00E14
113 #define MDMAFLX0_YCOUNT_D 0xFFC00E18
114 #define MDMAFLX0_YMODIFY_D 0xFFC00E1C
115 #define MDMAFLX0_IRQSTAT_D 0xFFC00E28
116 #define MDMAFLX0_PMAP_D 0xFFC00E2C
117 #define MDMAFLX0_CURXCOUNT_D 0xFFC00E30
118 #define MDMAFLX0_CURYCOUNT_D 0xFFC00E38
119 #define MDMAFLX0_DMACNFG_S 0xFFC00E48
120 #define MDMAFLX0_XCOUNT_S 0xFFC00E50
121 #define MDMAFLX0_XMODIFY_S 0xFFC00E54
122 #define MDMAFLX0_YCOUNT_S 0xFFC00E58
123 #define MDMAFLX0_YMODIFY_S 0xFFC00E5C
124 #define MDMAFLX0_IRQSTAT_S 0xFFC00E68
125 #define MDMAFLX0_PMAP_S 0xFFC00E6C
126 #define MDMAFLX0_CURXCOUNT_S 0xFFC00E70
127 #define MDMAFLX0_CURYCOUNT_S 0xFFC00E78
128 #define MDMAFLX1_DMACNFG_D 0xFFC00E88
129 #define MDMAFLX1_XCOUNT_D 0xFFC00E90
130 #define MDMAFLX1_XMODIFY_D 0xFFC00E94
131 #define MDMAFLX1_YCOUNT_D 0xFFC00E98
132 #define MDMAFLX1_YMODIFY_D 0xFFC00E9C
133 #define MDMAFLX1_IRQSTAT_D 0xFFC00EA8
134 #define MDMAFLX1_PMAP_D 0xFFC00EAC
135 #define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0
136 #define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8
137 #define MDMAFLX1_DMACNFG_S 0xFFC00EC8
138 #define MDMAFLX1_XCOUNT_S 0xFFC00ED0
139 #define MDMAFLX1_XMODIFY_S 0xFFC00ED4
140 #define MDMAFLX1_YCOUNT_S 0xFFC00ED8
141 #define MDMAFLX1_YMODIFY_S 0xFFC00EDC
142 #define MDMAFLX1_IRQSTAT_S 0xFFC00EE8
143 #define MDMAFLX1_PMAP_S 0xFFC00EEC
144 #define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0
145 #define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8
146 #define DMAFLX0_DMACNFG 0xFFC00C08
147 #define DMAFLX0_XCOUNT 0xFFC00C10
148 #define DMAFLX0_XMODIFY 0xFFC00C14
149 #define DMAFLX0_YCOUNT 0xFFC00C18
150 #define DMAFLX0_YMODIFY 0xFFC00C1C
151 #define DMAFLX0_IRQSTAT 0xFFC00C28
152 #define DMAFLX0_PMAP 0xFFC00C2C
153 #define DMAFLX0_CURXCOUNT 0xFFC00C30
154 #define DMAFLX0_CURYCOUNT 0xFFC00C38
155 #define DMAFLX1_DMACNFG 0xFFC00C48
156 #define DMAFLX1_XCOUNT 0xFFC00C50
157 #define DMAFLX1_XMODIFY 0xFFC00C54
158 #define DMAFLX1_YCOUNT 0xFFC00C58
159 #define DMAFLX1_YMODIFY 0xFFC00C5C
160 #define DMAFLX1_IRQSTAT 0xFFC00C68
161 #define DMAFLX1_PMAP 0xFFC00C6C
162 #define DMAFLX1_CURXCOUNT 0xFFC00C70
163 #define DMAFLX1_CURYCOUNT 0xFFC00C78
164 #define DMAFLX2_DMACNFG 0xFFC00C88
165 #define DMAFLX2_XCOUNT 0xFFC00C90
166 #define DMAFLX2_XMODIFY 0xFFC00C94
167 #define DMAFLX2_YCOUNT 0xFFC00C98
168 #define DMAFLX2_YMODIFY 0xFFC00C9C
169 #define DMAFLX2_IRQSTAT 0xFFC00CA8
170 #define DMAFLX2_PMAP 0xFFC00CAC
171 #define DMAFLX2_CURXCOUNT 0xFFC00CB0
172 #define DMAFLX2_CURYCOUNT 0xFFC00CB8
173 #define DMAFLX3_DMACNFG 0xFFC00CC8
174 #define DMAFLX3_XCOUNT 0xFFC00CD0
175 #define DMAFLX3_XMODIFY 0xFFC00CD4
176 #define DMAFLX3_YCOUNT 0xFFC00CD8
177 #define DMAFLX3_YMODIFY 0xFFC00CDC
178 #define DMAFLX3_IRQSTAT 0xFFC00CE8
179 #define DMAFLX3_PMAP 0xFFC00CEC
180 #define DMAFLX3_CURXCOUNT 0xFFC00CF0
181 #define DMAFLX3_CURYCOUNT 0xFFC00CF8
182 #define DMAFLX4_DMACNFG 0xFFC00D08
183 #define DMAFLX4_XCOUNT 0xFFC00D10
184 #define DMAFLX4_XMODIFY 0xFFC00D14
185 #define DMAFLX4_YCOUNT 0xFFC00D18
186 #define DMAFLX4_YMODIFY 0xFFC00D1C
187 #define DMAFLX4_IRQSTAT 0xFFC00D28
188 #define DMAFLX4_PMAP 0xFFC00D2C
189 #define DMAFLX4_CURXCOUNT 0xFFC00D30
190 #define DMAFLX4_CURYCOUNT 0xFFC00D38
191 #define DMAFLX5_DMACNFG 0xFFC00D48
192 #define DMAFLX5_XCOUNT 0xFFC00D50
193 #define DMAFLX5_XMODIFY 0xFFC00D54
194 #define DMAFLX5_YCOUNT 0xFFC00D58
195 #define DMAFLX5_YMODIFY 0xFFC00D5C
196 #define DMAFLX5_IRQSTAT 0xFFC00D68
197 #define DMAFLX5_PMAP 0xFFC00D6C
198 #define DMAFLX5_CURXCOUNT 0xFFC00D70
199 #define DMAFLX5_CURYCOUNT 0xFFC00D78
200 #define DMAFLX6_DMACNFG 0xFFC00D88
201 #define DMAFLX6_XCOUNT 0xFFC00D90
202 #define DMAFLX6_XMODIFY 0xFFC00D94
203 #define DMAFLX6_YCOUNT 0xFFC00D98
204 #define DMAFLX6_YMODIFY 0xFFC00D9C
205 #define DMAFLX6_IRQSTAT 0xFFC00DA8
206 #define DMAFLX6_PMAP 0xFFC00DAC
207 #define DMAFLX6_CURXCOUNT 0xFFC00DB0
208 #define DMAFLX6_CURYCOUNT 0xFFC00DB8
209 #define DMAFLX7_DMACNFG 0xFFC00DC8
210 #define DMAFLX7_XCOUNT 0xFFC00DD0
211 #define DMAFLX7_XMODIFY 0xFFC00DD4
212 #define DMAFLX7_YCOUNT 0xFFC00DD8
213 #define DMAFLX7_YMODIFY 0xFFC00DDC
214 #define DMAFLX7_IRQSTAT 0xFFC00DE8
215 #define DMAFLX7_PMAP 0xFFC00DEC
216 #define DMAFLX7_CURXCOUNT 0xFFC00DF0
217 #define DMAFLX7_CURYCOUNT 0xFFC00DF8
218 #define TIMER0_CONFIG 0xFFC00600
219 #define TIMER0_COUNTER 0xFFC00604
220 #define TIMER0_PERIOD 0xFFC00608
221 #define TIMER0_WIDTH 0xFFC0060C
222 #define TIMER1_CONFIG 0xFFC00610
223 #define TIMER1_COUNTER 0xFFC00614
224 #define TIMER1_PERIOD 0xFFC00618
225 #define TIMER1_WIDTH 0xFFC0061C
226 #define TIMER2_CONFIG 0xFFC00620
227 #define TIMER2_COUNTER 0xFFC00624
228 #define TIMER2_PERIOD 0xFFC00628
229 #define TIMER2_WIDTH 0xFFC0062C
230 #define TIMER_ENABLE 0xFFC00640
231 #define TIMER_DISABLE 0xFFC00644
232 #define TIMER_STATUS 0xFFC00648
233 #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
234 #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
235 #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
236 #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
237 #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
238 #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
239 #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
240 #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
241 #define UART_THR 0xFFC00400 /* Transmit Holding */
242 #define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */
243 #define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */
244 #define UART_IER 0xFFC00404
245 #define UART_IIR 0xFFC00408
246 #define UART_LCR 0xFFC0040C
247 #define UART_MCR 0xFFC00410
248 #define UART_LSR 0xFFC00414
249 #define UART_SCR 0xFFC0041C
250 #define UART_RBR 0xFFC00400 /* Receive Buffer */
251 #define UART_GCTL 0xFFC00424
252 #define SPT0_TX_CONFIG0 0xFFC00800
253 #define SPT0_TX_CONFIG1 0xFFC00804
254 #define SPT0_RX_CONFIG0 0xFFC00820
255 #define SPT0_RX_CONFIG1 0xFFC00824
256 #define SPT0_TX 0xFFC00810
257 #define SPT0_RX 0xFFC00818
258 #define SPT0_TSCLKDIV 0xFFC00808
259 #define SPT0_RSCLKDIV 0xFFC00828
260 #define SPT0_TFSDIV 0xFFC0080C
261 #define SPT0_RFSDIV 0xFFC0082C
262 #define SPT0_STAT 0xFFC00830
263 #define SPT0_MTCS0 0xFFC00840
264 #define SPT0_MTCS1 0xFFC00844
265 #define SPT0_MTCS2 0xFFC00848
266 #define SPT0_MTCS3 0xFFC0084C
267 #define SPT0_MRCS0 0xFFC00850
268 #define SPT0_MRCS1 0xFFC00854
269 #define SPT0_MRCS2 0xFFC00858
270 #define SPT0_MRCS3 0xFFC0085C
271 #define SPT0_MCMC1 0xFFC00838
272 #define SPT0_MCMC2 0xFFC0083C
273 #define SPT0_CHNL 0xFFC00834
274 #define SPT1_TX_CONFIG0 0xFFC00900
275 #define SPT1_TX_CONFIG1 0xFFC00904
276 #define SPT1_RX_CONFIG0 0xFFC00920
277 #define SPT1_RX_CONFIG1 0xFFC00924
278 #define SPT1_TX 0xFFC00910
279 #define SPT1_RX 0xFFC00918
280 #define SPT1_TSCLKDIV 0xFFC00908
281 #define SPT1_RSCLKDIV 0xFFC00928
282 #define SPT1_TFSDIV 0xFFC0090C
283 #define SPT1_RFSDIV 0xFFC0092C
284 #define SPT1_STAT 0xFFC00930
285 #define SPT1_MTCS0 0xFFC00940
286 #define SPT1_MTCS1 0xFFC00944
287 #define SPT1_MTCS2 0xFFC00948
288 #define SPT1_MTCS3 0xFFC0094C
289 #define SPT1_MRCS0 0xFFC00950
290 #define SPT1_MRCS1 0xFFC00954
291 #define SPT1_MRCS2 0xFFC00958
292 #define SPT1_MRCS3 0xFFC0095C
293 #define SPT1_MCMC1 0xFFC00938
294 #define SPT1_MCMC2 0xFFC0093C
295 #define SPT1_CHNL 0xFFC00934
296 #define PPI_CONTROL 0xFFC01000
297 #define PPI_STATUS 0xFFC01004
298 #define PPI_DELAY 0xFFC0100C
299 #define PPI_COUNT 0xFFC01008
300 #define PPI_FRAME 0xFFC01010
301 #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
302 #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
303 #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
304 #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
305 #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
306 #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
307 #define SYSCR 0xFFC00104 /* System Configuration register */
308 #define EVT_OVERRIDE 0xFFE02100
309 #define CHIPID 0xFFC00014
310 #define TBUFCTL 0xFFE06000 /* Trace Buffer Control Register */
311 #define TBUFSTAT 0xFFE06004 /* Trace Buffer Status Register */
312 #define TBUF 0xFFE06100 /* Trace Buffer */
313 #define PFCTL 0xFFE08000
314 #define PFCNTR0 0xFFE08100
315 #define PFCNTR1 0xFFE08104
316 #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
317 #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
318 #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
319 #define RTC_STAT 0xFFC00300
320 #define RTC_ICTL 0xFFC00304
321 #define RTC_ISTAT 0xFFC00308
322 #define RTC_SWCNT 0xFFC0030C
323 #define RTC_ALARM 0xFFC00310
324 #define RTC_PREN 0xFFC00314
325 #define SPI_CTL 0xFFC00500
326 #define SPI_FLG 0xFFC00504
327 #define SPI_STAT 0xFFC00508
328 #define SPI_TDBR 0xFFC0050C
329 #define SPI_RDBR 0xFFC00510
330 #define SPI_BAUD 0xFFC00514
331 #define SPI_SHADOW 0xFFC00518
332 #define FIO_FLAG_D 0xFFC00700
333 #define FIO_FLAG_C 0xFFC00704
334 #define FIO_FLAG_S 0xFFC00708
335 #define FIO_FLAG_T 0xFFC0070C
336 #define FIO_MASKA_D 0xFFC00710
337 #define FIO_MASKA_C 0xFFC00714
338 #define FIO_MASKA_S 0xFFC00718
339 #define FIO_MASKA_T 0xFFC0071C
340 #define FIO_MASKB_D 0xFFC00720
341 #define FIO_MASKB_C 0xFFC00724
342 #define FIO_MASKB_S 0xFFC00728
343 #define FIO_MASKB_T 0xFFC0072C
344 #define FIO_DIR 0xFFC00730
345 #define FIO_POLAR 0xFFC00734
346 #define FIO_EDGE 0xFFC00738
347 #define FIO_BOTH 0xFFC0073C
348 #define FIO_INEN 0xFFC00740
349 #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
350 #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
351 #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
352 #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
353 #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
354 #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
355 #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
356 #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
357 #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
358 #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
359 #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
360 #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
361 #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
362 #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
363 #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
364 #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
365 #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
366 #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
367 #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
368 #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
369 #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
370 #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
371 #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
372 #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
373 #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
374 #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
375 #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
376 #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
377 #define DMA0_NEXT_DESC_PTR 0xFFC00C00
378 #define DMA0_START_ADDR 0xFFC00C04
379 #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
380 #define DMA0_X_COUNT 0xFFC00C10
381 #define DMA0_X_MODIFY 0xFFC00C14
382 #define DMA0_Y_COUNT 0xFFC00C18
383 #define DMA0_Y_MODIFY 0xFFC00C1C
384 #define DMA0_CURR_DESC_PTR 0xFFC00C20
385 #define DMA0_CURR_ADDR 0xFFC00C24
386 #define DMA0_IRQ_STATUS 0xFFC00C28
387 #define DMA0_PERIPHERAL_MAP 0xFFC00C2C
388 #define DMA0_CURR_X_COUNT 0xFFC00C30
389 #define DMA0_CURR_Y_COUNT 0xFFC00C38
390 #define DMA1_NEXT_DESC_PTR 0xFFC00C40
391 #define DMA1_START_ADDR 0xFFC00C44
392 #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
393 #define DMA1_X_COUNT 0xFFC00C50
394 #define DMA1_X_MODIFY 0xFFC00C54
395 #define DMA1_Y_COUNT 0xFFC00C58
396 #define DMA1_Y_MODIFY 0xFFC00C5C
397 #define DMA1_CURR_DESC_PTR 0xFFC00C60
398 #define DMA1_CURR_ADDR 0xFFC00C64
399 #define DMA1_IRQ_STATUS 0xFFC00C68
400 #define DMA1_PERIPHERAL_MAP 0xFFC00C6C
401 #define DMA1_CURR_X_COUNT 0xFFC00C70
402 #define DMA1_CURR_Y_COUNT 0xFFC00C78
403 #define DMA2_NEXT_DESC_PTR 0xFFC00C80
404 #define DMA2_START_ADDR 0xFFC00C84
405 #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
406 #define DMA2_X_COUNT 0xFFC00C90
407 #define DMA2_X_MODIFY 0xFFC00C94
408 #define DMA2_Y_COUNT 0xFFC00C98
409 #define DMA2_Y_MODIFY 0xFFC00C9C
410 #define DMA2_CURR_DESC_PTR 0xFFC00CA0
411 #define DMA2_CURR_ADDR 0xFFC00CA4
412 #define DMA2_IRQ_STATUS 0xFFC00CA8
413 #define DMA2_PERIPHERAL_MAP 0xFFC00CAC
414 #define DMA2_CURR_X_COUNT 0xFFC00CB0
415 #define DMA2_CURR_Y_COUNT 0xFFC00CB8
416 #define DMA3_NEXT_DESC_PTR 0xFFC00CC0
417 #define DMA3_START_ADDR 0xFFC00CC4
418 #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
419 #define DMA3_X_COUNT 0xFFC00CD0
420 #define DMA3_X_MODIFY 0xFFC00CD4
421 #define DMA3_Y_COUNT 0xFFC00CD8
422 #define DMA3_Y_MODIFY 0xFFC00CDC
423 #define DMA3_CURR_DESC_PTR 0xFFC00CE0
424 #define DMA3_CURR_ADDR 0xFFC00CE4
425 #define DMA3_IRQ_STATUS 0xFFC00CE8
426 #define DMA3_PERIPHERAL_MAP 0xFFC00CEC
427 #define DMA3_CURR_X_COUNT 0xFFC00CF0
428 #define DMA3_CURR_Y_COUNT 0xFFC00CF8
429 #define DMA4_NEXT_DESC_PTR 0xFFC00D00
430 #define DMA4_START_ADDR 0xFFC00D04
431 #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
432 #define DMA4_X_COUNT 0xFFC00D10
433 #define DMA4_X_MODIFY 0xFFC00D14
434 #define DMA4_Y_COUNT 0xFFC00D18
435 #define DMA4_Y_MODIFY 0xFFC00D1C
436 #define DMA4_CURR_DESC_PTR 0xFFC00D20
437 #define DMA4_CURR_ADDR 0xFFC00D24
438 #define DMA4_IRQ_STATUS 0xFFC00D28
439 #define DMA4_PERIPHERAL_MAP 0xFFC00D2C
440 #define DMA4_CURR_X_COUNT 0xFFC00D30
441 #define DMA4_CURR_Y_COUNT 0xFFC00D38
442 #define DMA5_NEXT_DESC_PTR 0xFFC00D40
443 #define DMA5_START_ADDR 0xFFC00D44
444 #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
445 #define DMA5_X_COUNT 0xFFC00D50
446 #define DMA5_X_MODIFY 0xFFC00D54
447 #define DMA5_Y_COUNT 0xFFC00D58
448 #define DMA5_Y_MODIFY 0xFFC00D5C
449 #define DMA5_CURR_DESC_PTR 0xFFC00D60
450 #define DMA5_CURR_ADDR 0xFFC00D64
451 #define DMA5_IRQ_STATUS 0xFFC00D68
452 #define DMA5_PERIPHERAL_MAP 0xFFC00D6C
453 #define DMA5_CURR_X_COUNT 0xFFC00D70
454 #define DMA5_CURR_Y_COUNT 0xFFC00D78
455 #define DMA6_NEXT_DESC_PTR 0xFFC00D80
456 #define DMA6_START_ADDR 0xFFC00D84
457 #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
458 #define DMA6_X_COUNT 0xFFC00D90
459 #define DMA6_X_MODIFY 0xFFC00D94
460 #define DMA6_Y_COUNT 0xFFC00D98
461 #define DMA6_Y_MODIFY 0xFFC00D9C
462 #define DMA6_CURR_DESC_PTR 0xFFC00DA0
463 #define DMA6_CURR_ADDR 0xFFC00DA4
464 #define DMA6_IRQ_STATUS 0xFFC00DA8
465 #define DMA6_PERIPHERAL_MAP 0xFFC00DAC
466 #define DMA6_CURR_X_COUNT 0xFFC00DB0
467 #define DMA6_CURR_Y_COUNT 0xFFC00DB8
468 #define DMA7_NEXT_DESC_PTR 0xFFC00DC0
469 #define DMA7_START_ADDR 0xFFC00DC4
470 #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
471 #define DMA7_X_COUNT 0xFFC00DD0
472 #define DMA7_X_MODIFY 0xFFC00DD4
473 #define DMA7_Y_COUNT 0xFFC00DD8
474 #define DMA7_Y_MODIFY 0xFFC00DDC
475 #define DMA7_CURR_DESC_PTR 0xFFC00DE0
476 #define DMA7_CURR_ADDR 0xFFC00DE4
477 #define DMA7_IRQ_STATUS 0xFFC00DE8
478 #define DMA7_PERIPHERAL_MAP 0xFFC00DEC
479 #define DMA7_CURR_X_COUNT 0xFFC00DF0
480 #define DMA7_CURR_Y_COUNT 0xFFC00DF8
481 #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00
482 #define MDMA_D0_START_ADDR 0xFFC00E04
483 #define MDMA_D0_CONFIG 0xFFC00E08
484 #define MDMA_D0_X_COUNT 0xFFC00E10
485 #define MDMA_D0_X_MODIFY 0xFFC00E14
486 #define MDMA_D0_Y_COUNT 0xFFC00E18
487 #define MDMA_D0_Y_MODIFY 0xFFC00E1C
488 #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20
489 #define MDMA_D0_CURR_ADDR 0xFFC00E24
490 #define MDMA_D0_IRQ_STATUS 0xFFC00E28
491 #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C
492 #define MDMA_D0_CURR_X_COUNT 0xFFC00E30
493 #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38
494 #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40
495 #define MDMA_S0_START_ADDR 0xFFC00E44
496 #define MDMA_S0_CONFIG 0xFFC00E48
497 #define MDMA_S0_X_COUNT 0xFFC00E50
498 #define MDMA_S0_X_MODIFY 0xFFC00E54
499 #define MDMA_S0_Y_COUNT 0xFFC00E58
500 #define MDMA_S0_Y_MODIFY 0xFFC00E5C
501 #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60
502 #define MDMA_S0_CURR_ADDR 0xFFC00E64
503 #define MDMA_S0_IRQ_STATUS 0xFFC00E68
504 #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C
505 #define MDMA_S0_CURR_X_COUNT 0xFFC00E70
506 #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78
507 #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80
508 #define MDMA_D1_START_ADDR 0xFFC00E84
509 #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
510 #define MDMA_D1_X_COUNT 0xFFC00E90
511 #define MDMA_D1_X_MODIFY 0xFFC00E94
512 #define MDMA_D1_Y_COUNT 0xFFC00E98
513 #define MDMA_D1_Y_MODIFY 0xFFC00E9C
514 #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0
515 #define MDMA_D1_CURR_ADDR 0xFFC00EA4
516 #define MDMA_D1_IRQ_STATUS 0xFFC00EA8
517 #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC
518 #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0
519 #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8
520 #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0
521 #define MDMA_S1_START_ADDR 0xFFC00EC4
522 #define MDMA_S1_CONFIG 0xFFC00EC8
523 #define MDMA_S1_X_COUNT 0xFFC00ED0
524 #define MDMA_S1_X_MODIFY 0xFFC00ED4
525 #define MDMA_S1_Y_COUNT 0xFFC00ED8
526 #define MDMA_S1_Y_MODIFY 0xFFC00EDC
527 #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0
528 #define MDMA_S1_CURR_ADDR 0xFFC00EE4
529 #define MDMA_S1_IRQ_STATUS 0xFFC00EE8
530 #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC
531 #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0
532 #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8
533 #define EBIU_AMGCTL 0xFFC00A00
534 #define EBIU_AMBCTL0 0xFFC00A04
535 #define EBIU_AMBCTL1 0xFFC00A08
536 #define EBIU_SDGCTL 0xFFC00A10
537 #define EBIU_SDBCTL 0xFFC00A14
538 #define EBIU_SDRRC 0xFFC00A18
539 #define EBIU_SDSTAT 0xFFC00A1C
540 #define DMA_TC_CNT 0xFFC00B0C
541 #define DMA_TC_PER 0xFFC00B10
543 #endif /* __BFIN_DEF_ADSP_EDN_extended__ */
projects / karo-tx-uboot.git / blob