arch/blackfin/include/asm/mach-common/bits/cgu.h

   1 /*
   2  * CGU Masks
   3  */
   4
   5 #ifndef __BFIN_PERIPHERAL_CGU__
   6 #define __BFIN_PERIPHERAL_CGU__
   7
   8 /* CGU_CTL Masks */
   9 #define DF                      (1 << 0)
  10 #define MSEL                    (0x7f << MSEL_P)
  11 #define WIDLE                   (1 << WIDLE_P)
  12 #define LOCK                    (1 << LOCK_P)
  13
  14 #define DF_P                    0
  15 #define MSEL_P                  8
  16 #define WIDLE_P                 30
  17 #define LOCK_P                  31
  18 #define MSEL_MASK               0x7F00
  19 #define DF_MASK                 0x1
  20
  21 /* CGU_STAT Masks */
  22 #define PLLEN                   (1 << 0)
  23 #define PLLBP                   (1 << 1)
  24 #define PLLLK                   (1 << 2)
  25 #define CLKSALGN                (1 << 3)
  26 #define CCBF0EN                 (1 << 4)
  27 #define CCBF1EN                 (1 << 5)
  28 #define SCBF0EN                 (1 << 6)
  29 #define SCBF1EN                 (1 << 7)
  30 #define DCBFEN                  (1 << 8)
  31 #define OCBFEN                  (1 << 9)
  32 #define ADRERR                  (1 << 16)
  33 #define LWERR                   (1 << 17)
  34 #define DIVERR                  (1 << 18)
  35 #define WDFMSERR                (1 << 19)
  36 #define WDIVERR                 (1 << 20)
  37 #define PLLLKERR                (1 << 21)
  38
  39 /* CGU_DIV Masks */
  40 #define CSEL                    (0x1f << CSEL_P)
  41 #define S0SEL                   (3 << S0SEL_P)
  42 #define SYSSEL                  (0x1f << SYSSEL_P)
  43 #define S1SEL                   (3 << S1SEL_P)
  44 #define DSEL                    (0x1f << DSEL_P)
  45 #define OSEL                    (0x7f << OSEL_P)
  46 #define ALGN                    (1 << ALGN_P)
  47 #define UPDT                    (1 << UPDT_P)
  48 #define LOCK                    (1 << LOCK_P)
  49
  50 #define CSEL_P                  0
  51 #define S0SEL_P                 5
  52 #define SYSSEL_P                8
  53 #define S1SEL_P                 13
  54 #define DSEL_P                  16
  55 #define OSEL_P                  22
  56 #define ALGN_P                  29
  57 #define UPDT_P                  30
  58 #define LOCK_P                  31
  59
  60 /* CGU_CLKOUTSEL Masks */
  61 #define CLKOUTSEL               (0xf << 0)
  62 #define USBCLKSEL               (0x3f << 16)
  63 #define LOCK                    (1 << LOCK_P)
  64
  65 #define LOCK_P                  31
  66
  67 #define CLKOUTSEL_CLKIN         0x0
  68 #define CLKOUTSEL_CCLK          0x1
  69 #define CLKOUTSEL_SYSCLK        0x2
  70 #define CLKOUTSEL_SCLK0         0x3
  71 #define CLKOUTSEL_SCLK1         0x4
  72 #define CLKOUTSEL_DCLK          0x5
  73 #define CLKOUTSEL_USB_PLL       0x6
  74 #define CLKOUTSEL_OUTCLK        0x7
  75 #define CLKOUTSEL_USB_CLKIN     0x8
  76 #define CLKOUTSEL_WDOG          0x9
  77 #define CLKOUTSEL_PMON          0xA
  78 #define CLKOUTSEL_GND           0xB
  79
  80 #endif