arch/blackfin/lib/clocks.c

   1 /*
   2  * clocks.c - figure out sclk/cclk/vco and such
   3  *
   4  * Copyright (c) 2005-2008 Analog Devices Inc.
   5  *
   6  * Licensed under the GPL-2 or later.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/blackfin.h>
  11
  12 #ifdef PLL_CTL
  13 # include <asm/mach-common/bits/pll.h>
  14 # define pll_is_bypassed() (bfin_read_PLL_STAT() & DF)
  15 #else
  16 # include <asm/mach-common/bits/cgu.h>
  17 # define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
  18 # define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
  19 # define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
  20 #endif
  21
  22 /* Get the voltage input multiplier */
  23 u_long get_vco(void)
  24 {
  25         static u_long cached_vco_pll_ctl, cached_vco;
  26
  27         u_long msel, pll_ctl;
  28
  29         pll_ctl = bfin_read_PLL_CTL();
  30         if (pll_ctl == cached_vco_pll_ctl)
  31                 return cached_vco;
  32         else
  33                 cached_vco_pll_ctl = pll_ctl;
  34
  35         msel = (pll_ctl & MSEL) >> MSEL_P;
  36         if (0 == msel)
  37                 msel = (MSEL >> MSEL_P) + 1;
  38
  39         cached_vco = CONFIG_CLKIN_HZ;
  40         cached_vco >>= (pll_ctl & DF);
  41         cached_vco *= msel;
  42         return cached_vco;
  43 }
  44
  45 /* Get the Core clock */
  46 u_long get_cclk(void)
  47 {
  48         static u_long cached_cclk_pll_div, cached_cclk;
  49         u_long div, csel, ssel;
  50
  51         if (pll_is_bypassed())
  52                 return CONFIG_CLKIN_HZ;
  53
  54         div = bfin_read_PLL_DIV();
  55         if (div == cached_cclk_pll_div)
  56                 return cached_cclk;
  57         else
  58                 cached_cclk_pll_div = div;
  59
  60         csel = (div & CSEL) >> CSEL_P;
  61 #ifndef CGU_DIV
  62         ssel = (div & SSEL) >> SSEL_P;
  63         if (ssel && ssel < (1 << csel)) /* SCLK > CCLK */
  64                 cached_cclk = get_vco() / ssel;
  65         else
  66                 cached_cclk = get_vco() >> csel;
  67 #else
  68         cached_cclk = get_vco() / csel;
  69 #endif
  70         return cached_cclk;
  71 }
  72
  73 /* Get the System clock */
  74 #ifdef CGU_DIV
  75
  76 static u_long cached_sclk_pll_div, cached_sclk;
  77 static u_long cached_sclk0, cached_sclk1, cached_dclk;
  78 static u_long _get_sclk(u_long *cache)
  79 {
  80         u_long div, ssel;
  81
  82         if (pll_is_bypassed())
  83                 return CONFIG_CLKIN_HZ;
  84
  85         div = bfin_read_PLL_DIV();
  86         if (div == cached_sclk_pll_div)
  87                 return *cache;
  88         else
  89                 cached_sclk_pll_div = div;
  90
  91         ssel = (div & SYSSEL) >> SYSSEL_P;
  92         cached_sclk = get_vco() / ssel;
  93
  94         ssel = (div & S0SEL) >> S0SEL_P;
  95         cached_sclk0 = cached_sclk / ssel;
  96
  97         ssel = (div & S1SEL) >> S1SEL_P;
  98         cached_sclk1 = cached_sclk / ssel;
  99
 100         ssel = (div & DSEL) >> DSEL_P;
 101         cached_dclk = get_vco() / ssel;
 102
 103         return *cache;
 104 }
 105
 106 u_long get_sclk(void)
 107 {
 108         return _get_sclk(&cached_sclk);
 109 }
 110
 111 u_long get_sclk0(void)
 112 {
 113         return _get_sclk(&cached_sclk0);
 114 }
 115
 116 u_long get_sclk1(void)
 117 {
 118         return _get_sclk(&cached_sclk1);
 119 }
 120
 121 u_long get_dclk(void)
 122 {
 123         return _get_sclk(&cached_dclk);
 124 }
 125 #else
 126
 127 u_long get_sclk(void)
 128 {
 129         static u_long cached_sclk_pll_div, cached_sclk;
 130         u_long div, ssel;
 131
 132         if (pll_is_bypassed())
 133                 return CONFIG_CLKIN_HZ;
 134
 135         div = bfin_read_PLL_DIV();
 136         if (div == cached_sclk_pll_div)
 137                 return cached_sclk;
 138         else
 139                 cached_sclk_pll_div = div;
 140
 141         ssel = (div & SSEL) >> SSEL_P;
 142         cached_sclk = get_vco() / ssel;
 143
 144         return cached_sclk;
 145 }
 146
 147 #endif