arch/blackfin/lib/outs.S

   1 /*
   2  * Implementation of outs{bwl} for BlackFin processors using zero overhead loops.
   3  *
   4  * Copyright 2005-2009 Analog Devices Inc.
   5  *                2005 BuyWays BV
   6  *                      Bas Vermeulen <bas@buyways.nl>
   7  *
   8  * Licensed under the GPL-2.
   9  */
  10
  11 #include <asm/linkage.h>
  12
  13 .align 2
  14
  15 .section .text._outsl
  16 ENTRY(_outsl)
  17         P0 = R0;        /* P0 = port */
  18         P1 = R1;        /* P1 = address */
  19         P2 = R2;        /* P2 = count */
  20
  21         LSETUP( .Llong_loop_s, .Llong_loop_e) LC0 = P2;
  22 .Llong_loop_s: R0 = [P1++];
  23 .Llong_loop_e: [P0] = R0;
  24         RTS;
  25 ENDPROC(_outsl)
  26
  27 .section .text._outsw
  28 ENTRY(_outsw)
  29         P0 = R0;        /* P0 = port */
  30         P1 = R1;        /* P1 = address */
  31         P2 = R2;        /* P2 = count */
  32
  33         LSETUP( .Lword_loop_s, .Lword_loop_e) LC0 = P2;
  34 .Lword_loop_s: R0 = W[P1++];
  35 .Lword_loop_e: W[P0] = R0;
  36         RTS;
  37 ENDPROC(_outsw)
  38
  39 .section .text._outsb
  40 ENTRY(_outsb)
  41         P0 = R0;        /* P0 = port */
  42         P1 = R1;        /* P1 = address */
  43         P2 = R2;        /* P2 = count */
  44
  45         LSETUP( .Lbyte_loop_s, .Lbyte_loop_e) LC0 = P2;
  46 .Lbyte_loop_s: R0 = B[P1++];
  47 .Lbyte_loop_e: B[P0] = R0;
  48         RTS;
  49 ENDPROC(_outsb)
  50
  51 .section .text._outsw_8
  52 ENTRY(_outsw_8)
  53         P0 = R0;        /* P0 = port */
  54         P1 = R1;        /* P1 = address */
  55         P2 = R2;        /* P2 = count */
  56
  57         LSETUP( .Lword8_loop_s, .Lword8_loop_e) LC0 = P2;
  58 .Lword8_loop_s: R1 = B[P1++];
  59                 R0 = B[P1++];
  60                 R0 = R0 << 8;
  61                 R0 = R0 + R1;
  62 .Lword8_loop_e: W[P0] = R0;
  63         RTS;
  64 ENDPROC(_outsw_8)