arch/mips/mach-au1x00/au1x00_usb_ohci.c

   1 /*
   2  * URB OHCI HCD (Host Controller Driver) for USB on the AU1x00.
   3  *
   4  * (C) Copyright 2003
   5  * Gary Jennejohn, DENX Software Engineering <garyj@denx.de>
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  * Note: Part of this code has been derived from linux
   9  *
  10  */
  11 /*
  12  * IMPORTANT NOTES
  13  * 1 - this driver is intended for use with USB Mass Storage Devices
  14  *     (BBB) ONLY. There is NO support for Interrupt or Isochronous pipes!
  15  */
  16
  17 #include <config.h>
  18
  19 #ifdef CONFIG_USB_OHCI
  20
  21 /* #include <pci.h> no PCI on the AU1x00 */
  22
  23 #include <common.h>
  24 #include <malloc.h>
  25 #include <asm/io.h>
  26 #include <asm/au1x00.h>
  27 #include <usb.h>
  28 #include "au1x00_usb_ohci.h"
  29
  30 #define OHCI_USE_NPS            /* force NoPowerSwitching mode */
  31 #define OHCI_VERBOSE_DEBUG      /* not always helpful */
  32 #define OHCI_FILL_TRACE
  33
  34 #define USBH_ENABLE_BE (1<<0)
  35 #define USBH_ENABLE_C  (1<<1)
  36 #define USBH_ENABLE_E  (1<<2)
  37 #define USBH_ENABLE_CE (1<<3)
  38 #define USBH_ENABLE_RD (1<<4)
  39
  40 #ifdef __LITTLE_ENDIAN
  41 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C)
  42 #else
  43 #define USBH_ENABLE_INIT (USBH_ENABLE_CE | USBH_ENABLE_E | USBH_ENABLE_C | USBH_ENABLE_BE)
  44 #endif
  45
  46
  47 /* For initializing controller (mask in an HCFS mode too) */
  48 #define OHCI_CONTROL_INIT \
  49         (OHCI_CTRL_CBSR & 0x3) | OHCI_CTRL_IE | OHCI_CTRL_PLE
  50
  51 #undef readl
  52 #undef writel
  53
  54 #define readl(a)     au_readl((long)(a))
  55 #define writel(v,a)  au_writel((v),(int)(a))
  56
  57 #define DEBUG
  58 #ifdef DEBUG
  59 #define dbg(format, arg...) printf("DEBUG: " format "\n", ## arg)
  60 #else
  61 #define dbg(format, arg...) do {} while(0)
  62 #endif /* DEBUG */
  63 #define err(format, arg...) printf("ERROR: " format "\n", ## arg)
  64 #define SHOW_INFO
  65 #ifdef SHOW_INFO
  66 #define info(format, arg...) printf("INFO: " format "\n", ## arg)
  67 #else
  68 #define info(format, arg...) do {} while(0)
  69 #endif
  70
  71 #define m16_swap(x) swap_16(x)
  72 #define m32_swap(x) swap_32(x)
  73
  74 /* global ohci_t */
  75 static ohci_t gohci;
  76 /* this must be aligned to a 256 byte boundary */
  77 struct ohci_hcca ghcca[1];
  78 /* a pointer to the aligned storage */
  79 struct ohci_hcca *phcca;
  80 /* this allocates EDs for all possible endpoints */
  81 struct ohci_device ohci_dev;
  82 /* urb_priv */
  83 urb_priv_t urb_priv;
  84 /* RHSC flag */
  85 int got_rhsc;
  86 /* device which was disconnected */
  87 struct usb_device *devgone;
  88
  89 /*-------------------------------------------------------------------------*/
  90
  91 /* AMD-756 (D2 rev) reports corrupt register contents in some cases.
  92  * The erratum (#4) description is incorrect.  AMD's workaround waits
  93  * till some bits (mostly reserved) are clear; ok for all revs.
  94  */
  95 #define OHCI_QUIRK_AMD756 0xabcd
  96 #define read_roothub(hc, register, mask) ({ \
  97         u32 temp = readl (&hc->regs->roothub.register); \
  98         if (hc->flags & OHCI_QUIRK_AMD756) \
  99                 while (temp & mask) \
 100                         temp = readl (&hc->regs->roothub.register); \
 101         temp; })
 102
 103 static u32 roothub_a (struct ohci *hc)
 104         { return read_roothub (hc, a, 0xfc0fe000); }
 105 static inline u32 roothub_b (struct ohci *hc)
 106         { return readl (&hc->regs->roothub.b); }
 107 static inline u32 roothub_status (struct ohci *hc)
 108         { return readl (&hc->regs->roothub.status); }
 109 static u32 roothub_portstatus (struct ohci *hc, int i)
 110         { return read_roothub (hc, portstatus [i], 0xffe0fce0); }
 111
 112
 113 /* forward declaration */
 114 static int hc_interrupt (void);
 115 static void
 116 td_submit_job (struct usb_device * dev, unsigned long pipe, void * buffer,
 117         int transfer_len, struct devrequest * setup, urb_priv_t * urb, int interval);
 118
 119 /*-------------------------------------------------------------------------*
 120  * URB support functions
 121  *-------------------------------------------------------------------------*/
 122
 123 /* free HCD-private data associated with this URB */
 124
 125 static void urb_free_priv (urb_priv_t * urb)
 126 {
 127         int             i;
 128         int             last;
 129         struct td       * td;
 130
 131         last = urb->length - 1;
 132         if (last >= 0) {
 133                 for (i = 0; i <= last; i++) {
 134                         td = urb->td[i];
 135                         if (td) {
 136                                 td->usb_dev = NULL;
 137                                 urb->td[i] = NULL;
 138                         }
 139                 }
 140         }
 141 }
 142
 143 /*-------------------------------------------------------------------------*/
 144
 145 #ifdef DEBUG
 146 static int sohci_get_current_frame_number (struct usb_device * dev);
 147
 148 /* debug| print the main components of an URB
 149  * small: 0) header + data packets 1) just header */
 150
 151 static void pkt_print (struct usb_device * dev, unsigned long pipe, void * buffer,
 152         int transfer_len, struct devrequest * setup, char * str, int small)
 153 {
 154         urb_priv_t * purb = &urb_priv;
 155
 156         dbg("%s URB:[%4x] dev:%2d,ep:%2d-%c,type:%s,len:%d/%d stat:%#lx",
 157                         str,
 158                         sohci_get_current_frame_number (dev),
 159                         usb_pipedevice (pipe),
 160                         usb_pipeendpoint (pipe),
 161                         usb_pipeout (pipe)? 'O': 'I',
 162                         usb_pipetype (pipe) < 2? (usb_pipeint (pipe)? "INTR": "ISOC"):
 163                                 (usb_pipecontrol (pipe)? "CTRL": "BULK"),
 164                         purb->actual_length,
 165                         transfer_len, dev->status);
 166 #ifdef  OHCI_VERBOSE_DEBUG
 167         if (!small) {
 168                 int i, len;
 169
 170                 if (usb_pipecontrol (pipe)) {
 171                         printf (__FILE__ ": cmd(8):");
 172                         for (i = 0; i < 8 ; i++)
 173                                 printf (" %02x", ((__u8 *) setup) [i]);
 174                         printf ("\n");
 175                 }
 176                 if (transfer_len > 0 && buffer) {
 177                         printf (__FILE__ ": data(%d/%d):",
 178                                 purb->actual_length,
 179                                 transfer_len);
 180                         len = usb_pipeout (pipe)?
 181                                         transfer_len: purb->actual_length;
 182                         for (i = 0; i < 16 && i < len; i++)
 183                                 printf (" %02x", ((__u8 *) buffer) [i]);
 184                         printf ("%s\n", i < len? "...": "");
 185                 }
 186         }
 187 #endif
 188 }
 189
 190 /* just for debugging; prints non-empty branches of the int ed tree inclusive iso eds*/
 191 void ep_print_int_eds (ohci_t *ohci, char * str) {
 192         int i, j;
 193          __u32 * ed_p;
 194         for (i= 0; i < 32; i++) {
 195                 j = 5;
 196                 ed_p = &(ohci->hcca->int_table [i]);
 197                 if (*ed_p == 0)
 198                     continue;
 199                 printf (__FILE__ ": %s branch int %2d(%2x):", str, i, i);
 200                 while (*ed_p != 0 && j--) {
 201                         ed_t *ed = (ed_t *)m32_swap(ed_p);
 202                         printf (" ed: %4x;", ed->hwINFO);
 203                         ed_p = &ed->hwNextED;
 204                 }
 205                 printf ("\n");
 206         }
 207 }
 208
 209 static void ohci_dump_intr_mask (char *label, __u32 mask)
 210 {
 211         dbg ("%s: 0x%08x%s%s%s%s%s%s%s%s%s",
 212                 label,
 213                 mask,
 214                 (mask & OHCI_INTR_MIE) ? " MIE" : "",
 215                 (mask & OHCI_INTR_OC) ? " OC" : "",
 216                 (mask & OHCI_INTR_RHSC) ? " RHSC" : "",
 217                 (mask & OHCI_INTR_FNO) ? " FNO" : "",
 218                 (mask & OHCI_INTR_UE) ? " UE" : "",
 219                 (mask & OHCI_INTR_RD) ? " RD" : "",
 220                 (mask & OHCI_INTR_SF) ? " SF" : "",
 221                 (mask & OHCI_INTR_WDH) ? " WDH" : "",
 222                 (mask & OHCI_INTR_SO) ? " SO" : ""
 223                 );
 224 }
 225
 226 static void maybe_print_eds (char *label, __u32 value)
 227 {
 228         ed_t *edp = (ed_t *)value;
 229
 230         if (value) {
 231                 dbg ("%s %08x", label, value);
 232                 dbg ("%08x", edp->hwINFO);
 233                 dbg ("%08x", edp->hwTailP);
 234                 dbg ("%08x", edp->hwHeadP);
 235                 dbg ("%08x", edp->hwNextED);
 236         }
 237 }
 238
 239 static char * hcfs2string (int state)
 240 {
 241         switch (state) {
 242                 case OHCI_USB_RESET:    return "reset";
 243                 case OHCI_USB_RESUME:   return "resume";
 244                 case OHCI_USB_OPER:     return "operational";
 245                 case OHCI_USB_SUSPEND:  return "suspend";
 246         }
 247         return "?";
 248 }
 249
 250 /* dump control and status registers */
 251 static void ohci_dump_status (ohci_t *controller)
 252 {
 253         struct ohci_regs        *regs = controller->regs;
 254         __u32                   temp;
 255
 256         temp = readl (&regs->revision) & 0xff;
 257         if (temp != 0x10)
 258                 dbg ("spec %d.%d", (temp >> 4), (temp & 0x0f));
 259
 260         temp = readl (&regs->control);
 261         dbg ("control: 0x%08x%s%s%s HCFS=%s%s%s%s%s CBSR=%d", temp,
 262                 (temp & OHCI_CTRL_RWE) ? " RWE" : "",
 263                 (temp & OHCI_CTRL_RWC) ? " RWC" : "",
 264                 (temp & OHCI_CTRL_IR) ? " IR" : "",
 265                 hcfs2string (temp & OHCI_CTRL_HCFS),
 266                 (temp & OHCI_CTRL_BLE) ? " BLE" : "",
 267                 (temp & OHCI_CTRL_CLE) ? " CLE" : "",
 268                 (temp & OHCI_CTRL_IE) ? " IE" : "",
 269                 (temp & OHCI_CTRL_PLE) ? " PLE" : "",
 270                 temp & OHCI_CTRL_CBSR
 271                 );
 272
 273         temp = readl (&regs->cmdstatus);
 274         dbg ("cmdstatus: 0x%08x SOC=%d%s%s%s%s", temp,
 275                 (temp & OHCI_SOC) >> 16,
 276                 (temp & OHCI_OCR) ? " OCR" : "",
 277                 (temp & OHCI_BLF) ? " BLF" : "",
 278                 (temp & OHCI_CLF) ? " CLF" : "",
 279                 (temp & OHCI_HCR) ? " HCR" : ""
 280                 );
 281
 282         ohci_dump_intr_mask ("intrstatus", readl (&regs->intrstatus));
 283         ohci_dump_intr_mask ("intrenable", readl (&regs->intrenable));
 284
 285         maybe_print_eds ("ed_periodcurrent", readl (&regs->ed_periodcurrent));
 286
 287         maybe_print_eds ("ed_controlhead", readl (&regs->ed_controlhead));
 288         maybe_print_eds ("ed_controlcurrent", readl (&regs->ed_controlcurrent));
 289
 290         maybe_print_eds ("ed_bulkhead", readl (&regs->ed_bulkhead));
 291         maybe_print_eds ("ed_bulkcurrent", readl (&regs->ed_bulkcurrent));
 292
 293         maybe_print_eds ("donehead", readl (&regs->donehead));
 294 }
 295
 296 static void ohci_dump_roothub (ohci_t *controller, int verbose)
 297 {
 298         __u32                   temp, ndp, i;
 299
 300         temp = roothub_a (controller);
 301         ndp = (temp & RH_A_NDP);
 302
 303         if (verbose) {
 304                 dbg ("roothub.a: %08x POTPGT=%d%s%s%s%s%s NDP=%d", temp,
 305                         ((temp & RH_A_POTPGT) >> 24) & 0xff,
 306                         (temp & RH_A_NOCP) ? " NOCP" : "",
 307                         (temp & RH_A_OCPM) ? " OCPM" : "",
 308                         (temp & RH_A_DT) ? " DT" : "",
 309                         (temp & RH_A_NPS) ? " NPS" : "",
 310                         (temp & RH_A_PSM) ? " PSM" : "",
 311                         ndp
 312                         );
 313                 temp = roothub_b (controller);
 314                 dbg ("roothub.b: %08x PPCM=%04x DR=%04x",
 315                         temp,
 316                         (temp & RH_B_PPCM) >> 16,
 317                         (temp & RH_B_DR)
 318                         );
 319                 temp = roothub_status (controller);
 320                 dbg ("roothub.status: %08x%s%s%s%s%s%s",
 321                         temp,
 322                         (temp & RH_HS_CRWE) ? " CRWE" : "",
 323                         (temp & RH_HS_OCIC) ? " OCIC" : "",
 324                         (temp & RH_HS_LPSC) ? " LPSC" : "",
 325                         (temp & RH_HS_DRWE) ? " DRWE" : "",
 326                         (temp & RH_HS_OCI) ? " OCI" : "",
 327                         (temp & RH_HS_LPS) ? " LPS" : ""
 328                         );
 329         }
 330
 331         for (i = 0; i < ndp; i++) {
 332                 temp = roothub_portstatus (controller, i);
 333                 dbg ("roothub.portstatus [%d] = 0x%08x%s%s%s%s%s%s%s%s%s%s%s%s",
 334                         i,
 335                         temp,
 336                         (temp & RH_PS_PRSC) ? " PRSC" : "",
 337                         (temp & RH_PS_OCIC) ? " OCIC" : "",
 338                         (temp & RH_PS_PSSC) ? " PSSC" : "",
 339                         (temp & RH_PS_PESC) ? " PESC" : "",
 340                         (temp & RH_PS_CSC) ? " CSC" : "",
 341
 342                         (temp & RH_PS_LSDA) ? " LSDA" : "",
 343                         (temp & RH_PS_PPS) ? " PPS" : "",
 344                         (temp & RH_PS_PRS) ? " PRS" : "",
 345                         (temp & RH_PS_POCI) ? " POCI" : "",
 346                         (temp & RH_PS_PSS) ? " PSS" : "",
 347
 348                         (temp & RH_PS_PES) ? " PES" : "",
 349                         (temp & RH_PS_CCS) ? " CCS" : ""
 350                         );
 351         }
 352 }
 353
 354 static void ohci_dump (ohci_t *controller, int verbose)
 355 {
 356         dbg ("OHCI controller usb-%s state", controller->slot_name);
 357
 358         /* dumps some of the state we know about */
 359         ohci_dump_status (controller);
 360         if (verbose)
 361                 ep_print_int_eds (controller, "hcca");
 362         dbg ("hcca frame #%04x", controller->hcca->frame_no);
 363         ohci_dump_roothub (controller, 1);
 364 }
 365
 366
 367 #endif /* DEBUG */
 368
 369 /*-------------------------------------------------------------------------*
 370  * Interface functions (URB)
 371  *-------------------------------------------------------------------------*/
 372
 373 /* get a transfer request */
 374
 375 int sohci_submit_job(struct usb_device *dev, unsigned long pipe, void *buffer,
 376                 int transfer_len, struct devrequest *setup, int interval)
 377 {
 378         ohci_t *ohci;
 379         ed_t * ed;
 380         urb_priv_t *purb_priv;
 381         int i, size = 0;
 382
 383         ohci = &gohci;
 384
 385         /* when controller's hung, permit only roothub cleanup attempts
 386          * such as powering down ports */
 387         if (ohci->disabled) {
 388                 err("sohci_submit_job: EPIPE");
 389                 return -1;
 390         }
 391
 392         /* every endpoint has a ed, locate and fill it */
 393         if (!(ed = ep_add_ed (dev, pipe))) {
 394                 err("sohci_submit_job: ENOMEM");
 395                 return -1;
 396         }
 397
 398         /* for the private part of the URB we need the number of TDs (size) */
 399         switch (usb_pipetype (pipe)) {
 400                 case PIPE_BULK: /* one TD for every 4096 Byte */
 401                         size = (transfer_len - 1) / 4096 + 1;
 402                         break;
 403                 case PIPE_CONTROL: /* 1 TD for setup, 1 for ACK and 1 for every 4096 B */
 404                         size = (transfer_len == 0)? 2:
 405                                                 (transfer_len - 1) / 4096 + 3;
 406                         break;
 407         }
 408
 409         if (size >= (N_URB_TD - 1)) {
 410                 err("need %d TDs, only have %d", size, N_URB_TD);
 411                 return -1;
 412         }
 413         purb_priv = &urb_priv;
 414         purb_priv->pipe = pipe;
 415
 416         /* fill the private part of the URB */
 417         purb_priv->length = size;
 418         purb_priv->ed = ed;
 419         purb_priv->actual_length = 0;
 420
 421         /* allocate the TDs */
 422         /* note that td[0] was allocated in ep_add_ed */
 423         for (i = 0; i < size; i++) {
 424                 purb_priv->td[i] = td_alloc (dev);
 425                 if (!purb_priv->td[i]) {
 426                         purb_priv->length = i;
 427                         urb_free_priv (purb_priv);
 428                         err("sohci_submit_job: ENOMEM");
 429                         return -1;
 430                 }
 431         }
 432
 433         if (ed->state == ED_NEW || (ed->state & ED_DEL)) {
 434                 urb_free_priv (purb_priv);
 435                 err("sohci_submit_job: EINVAL");
 436                 return -1;
 437         }
 438
 439         /* link the ed into a chain if is not already */
 440         if (ed->state != ED_OPER)
 441                 ep_link (ohci, ed);
 442
 443         /* fill the TDs and link it to the ed */
 444         td_submit_job(dev, pipe, buffer, transfer_len, setup, purb_priv, interval);
 445
 446         return 0;
 447 }
 448
 449 /*-------------------------------------------------------------------------*/
 450
 451 #ifdef DEBUG
 452 /* tell us the current USB frame number */
 453
 454 static int sohci_get_current_frame_number (struct usb_device *usb_dev)
 455 {
 456         ohci_t *ohci = &gohci;
 457
 458         return m16_swap (ohci->hcca->frame_no);
 459 }
 460 #endif
 461
 462 /*-------------------------------------------------------------------------*
 463  * ED handling functions
 464  *-------------------------------------------------------------------------*/
 465
 466 /* link an ed into one of the HC chains */
 467
 468 static int ep_link (ohci_t *ohci, ed_t *edi)
 469 {
 470         volatile ed_t *ed = edi;
 471
 472         ed->state = ED_OPER;
 473
 474         switch (ed->type) {
 475         case PIPE_CONTROL:
 476                 ed->hwNextED = 0;
 477                 if (ohci->ed_controltail == NULL) {
 478                         writel ((long)ed, &ohci->regs->ed_controlhead);
 479                 } else {
 480                         ohci->ed_controltail->hwNextED = m32_swap (ed);
 481                 }
 482                 ed->ed_prev = ohci->ed_controltail;
 483                 if (!ohci->ed_controltail && !ohci->ed_rm_list[0] &&
 484                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 485                         ohci->hc_control |= OHCI_CTRL_CLE;
 486                         writel (ohci->hc_control, &ohci->regs->control);
 487                 }
 488                 ohci->ed_controltail = edi;
 489                 break;
 490
 491         case PIPE_BULK:
 492                 ed->hwNextED = 0;
 493                 if (ohci->ed_bulktail == NULL) {
 494                         writel ((long)ed, &ohci->regs->ed_bulkhead);
 495                 } else {
 496                         ohci->ed_bulktail->hwNextED = m32_swap (ed);
 497                 }
 498                 ed->ed_prev = ohci->ed_bulktail;
 499                 if (!ohci->ed_bulktail && !ohci->ed_rm_list[0] &&
 500                         !ohci->ed_rm_list[1] && !ohci->sleeping) {
 501                         ohci->hc_control |= OHCI_CTRL_BLE;
 502                         writel (ohci->hc_control, &ohci->regs->control);
 503                 }
 504                 ohci->ed_bulktail = edi;
 505                 break;
 506         }
 507         return 0;
 508 }
 509
 510 /*-------------------------------------------------------------------------*/
 511
 512 /* unlink an ed from one of the HC chains.
 513  * just the link to the ed is unlinked.
 514  * the link from the ed still points to another operational ed or 0
 515  * so the HC can eventually finish the processing of the unlinked ed */
 516
 517 static int ep_unlink (ohci_t *ohci, ed_t *ed)
 518 {
 519         ed->hwINFO |= m32_swap (OHCI_ED_SKIP);
 520
 521         switch (ed->type) {
 522         case PIPE_CONTROL:
 523                 if (ed->ed_prev == NULL) {
 524                         if (!ed->hwNextED) {
 525                                 ohci->hc_control &= ~OHCI_CTRL_CLE;
 526                                 writel (ohci->hc_control, &ohci->regs->control);
 527                         }
 528                         writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_controlhead);
 529                 } else {
 530                         ed->ed_prev->hwNextED = ed->hwNextED;
 531                 }
 532                 if (ohci->ed_controltail == ed) {
 533                         ohci->ed_controltail = ed->ed_prev;
 534                 } else {
 535                         ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 536                 }
 537                 break;
 538
 539         case PIPE_BULK:
 540                 if (ed->ed_prev == NULL) {
 541                         if (!ed->hwNextED) {
 542                                 ohci->hc_control &= ~OHCI_CTRL_BLE;
 543                                 writel (ohci->hc_control, &ohci->regs->control);
 544                         }
 545                         writel (m32_swap (*((__u32 *)&ed->hwNextED)), &ohci->regs->ed_bulkhead);
 546                 } else {
 547                         ed->ed_prev->hwNextED = ed->hwNextED;
 548                 }
 549                 if (ohci->ed_bulktail == ed) {
 550                         ohci->ed_bulktail = ed->ed_prev;
 551                 } else {
 552                         ((ed_t *)m32_swap (*((__u32 *)&ed->hwNextED)))->ed_prev = ed->ed_prev;
 553                 }
 554                 break;
 555         }
 556         ed->state = ED_UNLINK;
 557         return 0;
 558 }
 559
 560
 561 /*-------------------------------------------------------------------------*/
 562
 563 /* add/reinit an endpoint; this should be done once at the usb_set_configuration command,
 564  * but the USB stack is a little bit stateless  so we do it at every transaction
 565  * if the state of the ed is ED_NEW then a dummy td is added and the state is changed to ED_UNLINK
 566  * in all other cases the state is left unchanged
 567  * the ed info fields are setted anyway even though most of them should not change */
 568
 569 static ed_t * ep_add_ed (struct usb_device *usb_dev, unsigned long pipe)
 570 {
 571         td_t *td;
 572         ed_t *ed_ret;
 573         volatile ed_t *ed;
 574
 575         ed = ed_ret = &ohci_dev.ed[(usb_pipeendpoint (pipe) << 1) |
 576                         (usb_pipecontrol (pipe)? 0: usb_pipeout (pipe))];
 577
 578         if ((ed->state & ED_DEL) || (ed->state & ED_URB_DEL)) {
 579                 err("ep_add_ed: pending delete");
 580                 /* pending delete request */
 581                 return NULL;
 582         }
 583
 584         if (ed->state == ED_NEW) {
 585                 ed->hwINFO = m32_swap (OHCI_ED_SKIP); /* skip ed */
 586                 /* dummy td; end of td list for ed */
 587                 td = td_alloc (usb_dev);
 588                 ed->hwTailP = m32_swap (td);
 589                 ed->hwHeadP = ed->hwTailP;
 590                 ed->state = ED_UNLINK;
 591                 ed->type = usb_pipetype (pipe);
 592                 ohci_dev.ed_cnt++;
 593         }
 594
 595         ed->hwINFO = m32_swap (usb_pipedevice (pipe)
 596                         | usb_pipeendpoint (pipe) << 7
 597                         | (usb_pipeisoc (pipe)? 0x8000: 0)
 598                         | (usb_pipecontrol (pipe)? 0: (usb_pipeout (pipe)? 0x800: 0x1000))
 599                         | (usb_dev->speed == USB_SPEED_LOW) << 13
 600                         | usb_maxpacket (usb_dev, pipe) << 16);
 601
 602         return ed_ret;
 603 }
 604
 605 /*-------------------------------------------------------------------------*
 606  * TD handling functions
 607  *-------------------------------------------------------------------------*/
 608
 609 /* enqueue next TD for this URB (OHCI spec 5.2.8.2) */
 610
 611 static void td_fill (ohci_t *ohci, unsigned int info,
 612         void *data, int len,
 613         struct usb_device *dev, int index, urb_priv_t *urb_priv)
 614 {
 615         volatile td_t  *td, *td_pt;
 616 #ifdef OHCI_FILL_TRACE
 617         int i;
 618 #endif
 619
 620         if (index > urb_priv->length) {
 621                 err("index > length");
 622                 return;
 623         }
 624         /* use this td as the next dummy */
 625         td_pt = urb_priv->td [index];
 626         td_pt->hwNextTD = 0;
 627
 628         /* fill the old dummy TD */
 629         td = urb_priv->td [index] = (td_t *)(m32_swap (urb_priv->ed->hwTailP) & ~0xf);
 630
 631         td->ed = urb_priv->ed;
 632         td->next_dl_td = NULL;
 633         td->index = index;
 634         td->data = (__u32)data;
 635 #ifdef OHCI_FILL_TRACE
 636         if (1 || (usb_pipebulk(urb_priv->pipe) &&
 637                                 usb_pipeout(urb_priv->pipe))) {
 638                 for (i = 0; i < len; i++)
 639                 printf("td->data[%d] %#2x\n",i, ((unsigned char *)(td->data+0x80000000))[i]);
 640         }
 641 #endif
 642         if (!len)
 643                 data = 0;
 644
 645         td->hwINFO = m32_swap (info);
 646         td->hwCBP = m32_swap (data);
 647         if (data)
 648                 td->hwBE = m32_swap (data + len - 1);
 649         else
 650                 td->hwBE = 0;
 651         td->hwNextTD = m32_swap (td_pt);
 652         td->hwPSW [0] = m16_swap (((__u32)data & 0x0FFF) | 0xE000);
 653
 654         /* append to queue */
 655         td->ed->hwTailP = td->hwNextTD;
 656 }
 657
 658 /*-------------------------------------------------------------------------*/
 659
 660 /* prepare all TDs of a transfer */
 661
 662 #define kseg_to_phys(x)   ((void *)((__u32)(x) - 0x80000000))
 663
 664 static void td_submit_job (struct usb_device *dev, unsigned long pipe, void *buffer,
 665         int transfer_len, struct devrequest *setup, urb_priv_t *urb, int interval)
 666 {
 667         ohci_t *ohci = &gohci;
 668         int data_len = transfer_len;
 669         void *data;
 670         int cnt = 0;
 671         __u32 info = 0;
 672         unsigned int toggle = 0;
 673
 674         /* OHCI handles the DATA-toggles itself, we just use the USB-toggle bits for reseting */
 675         if(usb_gettoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe))) {
 676                 toggle = TD_T_TOGGLE;
 677         } else {
 678                 toggle = TD_T_DATA0;
 679                 usb_settoggle(dev, usb_pipeendpoint(pipe), usb_pipeout(pipe), 1);
 680         }
 681         urb->td_cnt = 0;
 682         if (data_len)
 683                 data = kseg_to_phys(buffer);
 684         else
 685                 data = 0;
 686
 687         switch (usb_pipetype (pipe)) {
 688         case PIPE_BULK:
 689                 info = usb_pipeout (pipe)?
 690                         TD_CC | TD_DP_OUT : TD_CC | TD_DP_IN ;
 691                 while(data_len > 4096) {
 692                         td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, 4096, dev, cnt, urb);
 693                         data += 4096; data_len -= 4096; cnt++;
 694                 }
 695                 info = usb_pipeout (pipe)?
 696                         TD_CC | TD_DP_OUT : TD_CC | TD_R | TD_DP_IN ;
 697                 td_fill (ohci, info | (cnt? TD_T_TOGGLE:toggle), data, data_len, dev, cnt, urb);
 698                 cnt++;
 699
 700                 if (!ohci->sleeping)
 701                         writel (OHCI_BLF, &ohci->regs->cmdstatus); /* start bulk list */
 702                 break;
 703
 704         case PIPE_CONTROL:
 705                 info = TD_CC | TD_DP_SETUP | TD_T_DATA0;
 706                 td_fill (ohci, info, kseg_to_phys(setup), 8, dev, cnt++, urb);
 707                 if (data_len > 0) {
 708                         info = usb_pipeout (pipe)?
 709                                 TD_CC | TD_R | TD_DP_OUT | TD_T_DATA1 : TD_CC | TD_R | TD_DP_IN | TD_T_DATA1;
 710                         /* NOTE:  mishandles transfers >8K, some >4K */
 711                         td_fill (ohci, info, data, data_len, dev, cnt++, urb);
 712                 }
 713                 info = usb_pipeout (pipe)?
 714                         TD_CC | TD_DP_IN | TD_T_DATA1: TD_CC | TD_DP_OUT | TD_T_DATA1;
 715                 td_fill (ohci, info, data, 0, dev, cnt++, urb);
 716                 if (!ohci->sleeping)
 717                         writel (OHCI_CLF, &ohci->regs->cmdstatus); /* start Control list */
 718                 break;
 719         }
 720         if (urb->length != cnt)
 721                 dbg("TD LENGTH %d != CNT %d", urb->length, cnt);
 722 }
 723
 724 /*-------------------------------------------------------------------------*
 725  * Done List handling functions
 726  *-------------------------------------------------------------------------*/
 727
 728
 729 /* calculate the transfer length and update the urb */
 730
 731 static void dl_transfer_length(td_t * td)
 732 {
 733         __u32 tdINFO, tdBE, tdCBP;
 734         urb_priv_t *lurb_priv = &urb_priv;
 735
 736         tdINFO = m32_swap (td->hwINFO);
 737         tdBE   = m32_swap (td->hwBE);
 738         tdCBP  = m32_swap (td->hwCBP);
 739
 740
 741         if (!(usb_pipecontrol(lurb_priv->pipe) &&
 742             ((td->index == 0) || (td->index == lurb_priv->length - 1)))) {
 743                 if (tdBE != 0) {
 744                         if (td->hwCBP == 0)
 745                                 lurb_priv->actual_length += tdBE - td->data + 1;
 746                         else
 747                                 lurb_priv->actual_length += tdCBP - td->data;
 748                 }
 749         }
 750 }
 751
 752 /*-------------------------------------------------------------------------*/
 753
 754 /* replies to the request have to be on a FIFO basis so
 755  * we reverse the reversed done-list */
 756
 757 static td_t * dl_reverse_done_list (ohci_t *ohci)
 758 {
 759         __u32 td_list_hc;
 760         td_t *td_rev = NULL;
 761         td_t *td_list = NULL;
 762         urb_priv_t *lurb_priv = NULL;
 763
 764         td_list_hc = m32_swap (ohci->hcca->done_head) & 0xfffffff0;
 765         ohci->hcca->done_head = 0;
 766
 767         while (td_list_hc) {
 768                 td_list = (td_t *)td_list_hc;
 769
 770                 if (TD_CC_GET (m32_swap (td_list->hwINFO))) {
 771                         lurb_priv = &urb_priv;
 772                         dbg(" USB-error/status: %x : %p",
 773                                         TD_CC_GET (m32_swap (td_list->hwINFO)), td_list);
 774                         if (td_list->ed->hwHeadP & m32_swap (0x1)) {
 775                                 if (lurb_priv && ((td_list->index + 1) < lurb_priv->length)) {
 776                                         td_list->ed->hwHeadP =
 777                                                 (lurb_priv->td[lurb_priv->length - 1]->hwNextTD & m32_swap (0xfffffff0)) |
 778                                                                         (td_list->ed->hwHeadP & m32_swap (0x2));
 779                                         lurb_priv->td_cnt += lurb_priv->length - td_list->index - 1;
 780                                 } else
 781                                         td_list->ed->hwHeadP &= m32_swap (0xfffffff2);
 782                         }
 783                 }
 784
 785                 td_list->next_dl_td = td_rev;
 786                 td_rev = td_list;
 787                 td_list_hc = m32_swap (td_list->hwNextTD) & 0xfffffff0;
 788         }
 789         return td_list;
 790 }
 791
 792 /*-------------------------------------------------------------------------*/
 793
 794 /* td done list */
 795 static int dl_done_list (ohci_t *ohci, td_t *td_list)
 796 {
 797         td_t *td_list_next = NULL;
 798         ed_t *ed;
 799         int cc = 0;
 800         int stat = 0;
 801         /* urb_t *urb; */
 802         urb_priv_t *lurb_priv;
 803         __u32 tdINFO, edHeadP, edTailP;
 804
 805         while (td_list) {
 806                 td_list_next = td_list->next_dl_td;
 807
 808                 lurb_priv = &urb_priv;
 809                 tdINFO = m32_swap (td_list->hwINFO);
 810
 811                 ed = td_list->ed;
 812
 813                 dl_transfer_length(td_list);
 814
 815                 /* error code of transfer */
 816                 cc = TD_CC_GET (tdINFO);
 817                 if (cc != 0) {
 818                         dbg("ConditionCode %#x", cc);
 819                         stat = cc_to_error[cc];
 820                 }
 821
 822                 if (ed->state != ED_NEW) {
 823                         edHeadP = m32_swap (ed->hwHeadP) & 0xfffffff0;
 824                         edTailP = m32_swap (ed->hwTailP);
 825
 826                         /* unlink eds if they are not busy */
 827                         if ((edHeadP == edTailP) && (ed->state == ED_OPER))
 828                                 ep_unlink (ohci, ed);
 829                 }
 830
 831                 td_list = td_list_next;
 832         }
 833         return stat;
 834 }
 835
 836 /*-------------------------------------------------------------------------*
 837  * Virtual Root Hub
 838  *-------------------------------------------------------------------------*/
 839
 840 #include <usbroothubdes.h>
 841
 842 /* Hub class-specific descriptor is constructed dynamically */
 843
 844
 845 /*-------------------------------------------------------------------------*/
 846
 847 #define OK(x)                   len = (x); break
 848 #ifdef DEBUG
 849 #define WR_RH_STAT(x)           {info("WR:status %#8x", (x));writel((x), &gohci.regs->roothub.status);}
 850 #define WR_RH_PORTSTAT(x)       {info("WR:portstatus[%d] %#8x", wIndex-1, (x));writel((x), &gohci.regs->roothub.portstatus[wIndex-1]);}
 851 #else
 852 #define WR_RH_STAT(x)           writel((x), &gohci.regs->roothub.status)
 853 #define WR_RH_PORTSTAT(x)       writel((x), &gohci.regs->roothub.portstatus[wIndex-1])
 854 #endif
 855 #define RD_RH_STAT              roothub_status(&gohci)
 856 #define RD_RH_PORTSTAT          roothub_portstatus(&gohci,wIndex-1)
 857
 858 /* request to virtual root hub */
 859
 860 int rh_check_port_status(ohci_t *controller)
 861 {
 862         __u32 temp, ndp, i;
 863         int res;
 864
 865         res = -1;
 866         temp = roothub_a (controller);
 867         ndp = (temp & RH_A_NDP);
 868         for (i = 0; i < ndp; i++) {
 869                 temp = roothub_portstatus (controller, i);
 870                 /* check for a device disconnect */
 871                 if (((temp & (RH_PS_PESC | RH_PS_CSC)) ==
 872                         (RH_PS_PESC | RH_PS_CSC)) &&
 873                         ((temp & RH_PS_CCS) == 0)) {
 874                         res = i;
 875                         break;
 876                 }
 877         }
 878         return res;
 879 }
 880
 881 static int ohci_submit_rh_msg(struct usb_device *dev, unsigned long pipe,
 882                 void *buffer, int transfer_len, struct devrequest *cmd)
 883 {
 884         void * data = buffer;
 885         int leni = transfer_len;
 886         int len = 0;
 887         int stat = 0;
 888         __u32 datab[4];
 889         __u8 *data_buf = (__u8 *)datab;
 890         __u16 bmRType_bReq;
 891         __u16 wValue;
 892         __u16 wIndex;
 893         __u16 wLength;
 894
 895 #ifdef DEBUG
 896 urb_priv.actual_length = 0;
 897 pkt_print(dev, pipe, buffer, transfer_len, cmd, "SUB(rh)", usb_pipein(pipe));
 898 #else
 899         mdelay(1);
 900 #endif
 901         if (usb_pipeint(pipe)) {
 902                 info("Root-Hub submit IRQ: NOT implemented");
 903                 return 0;
 904         }
 905
 906         bmRType_bReq  = cmd->requesttype | (cmd->request << 8);
 907         wValue        = m16_swap (cmd->value);
 908         wIndex        = m16_swap (cmd->index);
 909         wLength       = m16_swap (cmd->length);
 910
 911         info("Root-Hub: adr: %2x cmd(%1x): %08x %04x %04x %04x",
 912                 dev->devnum, 8, bmRType_bReq, wValue, wIndex, wLength);
 913
 914         switch (bmRType_bReq) {
 915         /* Request Destination:
 916            without flags: Device,
 917            RH_INTERFACE: interface,
 918            RH_ENDPOINT: endpoint,
 919            RH_CLASS means HUB here,
 920            RH_OTHER | RH_CLASS  almost ever means HUB_PORT here
 921         */
 922
 923         case RH_GET_STATUS:
 924                         *(__u16 *) data_buf = m16_swap (1); OK (2);
 925         case RH_GET_STATUS | RH_INTERFACE:
 926                         *(__u16 *) data_buf = m16_swap (0); OK (2);
 927         case RH_GET_STATUS | RH_ENDPOINT:
 928                         *(__u16 *) data_buf = m16_swap (0); OK (2);
 929         case RH_GET_STATUS | RH_CLASS:
 930                         *(__u32 *) data_buf = m32_swap (
 931                                 RD_RH_STAT & ~(RH_HS_CRWE | RH_HS_DRWE));
 932                         OK (4);
 933         case RH_GET_STATUS | RH_OTHER | RH_CLASS:
 934                         *(__u32 *) data_buf = m32_swap (RD_RH_PORTSTAT); OK (4);
 935
 936         case RH_CLEAR_FEATURE | RH_ENDPOINT:
 937                 switch (wValue) {
 938                         case (RH_ENDPOINT_STALL): OK (0);
 939                 }
 940                 break;
 941
 942         case RH_CLEAR_FEATURE | RH_CLASS:
 943                 switch (wValue) {
 944                         case RH_C_HUB_LOCAL_POWER:
 945                                 OK(0);
 946                         case (RH_C_HUB_OVER_CURRENT):
 947                                         WR_RH_STAT(RH_HS_OCIC); OK (0);
 948                 }
 949                 break;
 950
 951         case RH_CLEAR_FEATURE | RH_OTHER | RH_CLASS:
 952                 switch (wValue) {
 953                         case (RH_PORT_ENABLE):
 954                                         WR_RH_PORTSTAT (RH_PS_CCS ); OK (0);
 955                         case (RH_PORT_SUSPEND):
 956                                         WR_RH_PORTSTAT (RH_PS_POCI); OK (0);
 957                         case (RH_PORT_POWER):
 958                                         WR_RH_PORTSTAT (RH_PS_LSDA); OK (0);
 959                         case (RH_C_PORT_CONNECTION):
 960                                         WR_RH_PORTSTAT (RH_PS_CSC ); OK (0);
 961                         case (RH_C_PORT_ENABLE):
 962                                         WR_RH_PORTSTAT (RH_PS_PESC); OK (0);
 963                         case (RH_C_PORT_SUSPEND):
 964                                         WR_RH_PORTSTAT (RH_PS_PSSC); OK (0);
 965                         case (RH_C_PORT_OVER_CURRENT):
 966                                         WR_RH_PORTSTAT (RH_PS_OCIC); OK (0);
 967                         case (RH_C_PORT_RESET):
 968                                         WR_RH_PORTSTAT (RH_PS_PRSC); OK (0);
 969                 }
 970                 break;
 971
 972         case RH_SET_FEATURE | RH_OTHER | RH_CLASS:
 973                 switch (wValue) {
 974                         case (RH_PORT_SUSPEND):
 975                                         WR_RH_PORTSTAT (RH_PS_PSS ); OK (0);
 976                         case (RH_PORT_RESET): /* BUG IN HUP CODE *********/
 977                                         if (RD_RH_PORTSTAT & RH_PS_CCS)
 978                                             WR_RH_PORTSTAT (RH_PS_PRS);
 979                                         OK (0);
 980                         case (RH_PORT_POWER):
 981                                         WR_RH_PORTSTAT (RH_PS_PPS ); OK (0);
 982                         case (RH_PORT_ENABLE): /* BUG IN HUP CODE *********/
 983                                         if (RD_RH_PORTSTAT & RH_PS_CCS)
 984                                             WR_RH_PORTSTAT (RH_PS_PES );
 985                                         OK (0);
 986                 }
 987                 break;
 988
 989         case RH_SET_ADDRESS: gohci.rh.devnum = wValue; OK(0);
 990
 991         case RH_GET_DESCRIPTOR:
 992                 switch ((wValue & 0xff00) >> 8) {
 993                         case (0x01): /* device descriptor */
 994                                 len = min_t(unsigned int,
 995                                           leni,
 996                                           min_t(unsigned int,
 997                                               sizeof (root_hub_dev_des),
 998                                               wLength));
 999                                 data_buf = root_hub_dev_des; OK(len);
1000                         case (0x02): /* configuration descriptor */
1001                                 len = min_t(unsigned int,
1002                                           leni,
1003                                           min_t(unsigned int,
1004                                               sizeof (root_hub_config_des),
1005                                               wLength));
1006                                 data_buf = root_hub_config_des; OK(len);
1007                         case (0x03): /* string descriptors */
1008                                 if(wValue==0x0300) {
1009                                         len = min_t(unsigned int,
1010                                                   leni,
1011                                                   min_t(unsigned int,
1012                                                       sizeof (root_hub_str_index0),
1013                                                       wLength));
1014                                         data_buf = root_hub_str_index0;
1015                                         OK(len);
1016                                 }
1017                                 if(wValue==0x0301) {
1018                                         len = min_t(unsigned int,
1019                                                   leni,
1020                                                   min_t(unsigned int,
1021                                                       sizeof (root_hub_str_index1),
1022                                                       wLength));
1023                                         data_buf = root_hub_str_index1;
1024                                         OK(len);
1025                         }
1026                         default:
1027                                 stat = USB_ST_STALLED;
1028                 }
1029                 break;
1030
1031         case RH_GET_DESCRIPTOR | RH_CLASS:
1032             {
1033                     __u32 temp = roothub_a (&gohci);
1034
1035                     data_buf [0] = 9;           /* min length; */
1036                     data_buf [1] = 0x29;
1037                     data_buf [2] = temp & RH_A_NDP;
1038                     data_buf [3] = 0;
1039                     if (temp & RH_A_PSM)        /* per-port power switching? */
1040                         data_buf [3] |= 0x1;
1041                     if (temp & RH_A_NOCP)       /* no overcurrent reporting? */
1042                         data_buf [3] |= 0x10;
1043                     else if (temp & RH_A_OCPM)  /* per-port overcurrent reporting? */
1044                         data_buf [3] |= 0x8;
1045
1046                     /* corresponds to data_buf[4-7] */
1047                     datab [1] = 0;
1048                     data_buf [5] = (temp & RH_A_POTPGT) >> 24;
1049                     temp = roothub_b (&gohci);
1050                     data_buf [7] = temp & RH_B_DR;
1051                     if (data_buf [2] < 7) {
1052                         data_buf [8] = 0xff;
1053                     } else {
1054                         data_buf [0] += 2;
1055                         data_buf [8] = (temp & RH_B_DR) >> 8;
1056                         data_buf [10] = data_buf [9] = 0xff;
1057                     }
1058
1059                     len = min_t(unsigned int, leni,
1060                               min_t(unsigned int, data_buf [0], wLength));
1061                     OK (len);
1062                 }
1063
1064         case RH_GET_CONFIGURATION:      *(__u8 *) data_buf = 0x01; OK (1);
1065
1066         case RH_SET_CONFIGURATION:      WR_RH_STAT (0x10000); OK (0);
1067
1068         default:
1069                 dbg ("unsupported root hub command");
1070                 stat = USB_ST_STALLED;
1071         }
1072
1073 #ifdef  DEBUG
1074         ohci_dump_roothub (&gohci, 1);
1075 #else
1076         mdelay(1);
1077 #endif
1078
1079         len = min_t(int, len, leni);
1080         if (data != data_buf)
1081             memcpy (data, data_buf, len);
1082         dev->act_len = len;
1083         dev->status = stat;
1084
1085 #ifdef DEBUG
1086         if (transfer_len)
1087                 urb_priv.actual_length = transfer_len;
1088         pkt_print(dev, pipe, buffer, transfer_len, cmd, "RET(rh)", 0/*usb_pipein(pipe)*/);
1089 #else
1090         mdelay(1);
1091 #endif
1092
1093         return stat;
1094 }
1095
1096 /*-------------------------------------------------------------------------*/
1097
1098 /* common code for handling submit messages - used for all but root hub */
1099 /* accesses. */
1100 int submit_common_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1101                 int transfer_len, struct devrequest *setup, int interval)
1102 {
1103         int stat = 0;
1104         int maxsize = usb_maxpacket(dev, pipe);
1105         int timeout;
1106
1107         /* device pulled? Shortcut the action. */
1108         if (devgone == dev) {
1109                 dev->status = USB_ST_CRC_ERR;
1110                 return 0;
1111         }
1112
1113 #ifdef DEBUG
1114         urb_priv.actual_length = 0;
1115         pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1116 #else
1117         mdelay(1);
1118 #endif
1119         if (!maxsize) {
1120                 err("submit_common_message: pipesize for pipe %lx is zero",
1121                         pipe);
1122                 return -1;
1123         }
1124
1125         if (sohci_submit_job(dev, pipe, buffer, transfer_len, setup, interval) < 0) {
1126                 err("sohci_submit_job failed");
1127                 return -1;
1128         }
1129
1130         mdelay(10);
1131         /* ohci_dump_status(&gohci); */
1132
1133         /* allow more time for a BULK device to react - some are slow */
1134 #define BULK_TO  5000   /* timeout in milliseconds */
1135         if (usb_pipebulk(pipe))
1136                 timeout = BULK_TO;
1137         else
1138                 timeout = 100;
1139
1140         timeout *= 4;
1141         /* wait for it to complete */
1142         for (;;) {
1143                 /* check whether the controller is done */
1144                 stat = hc_interrupt();
1145                 if (stat < 0) {
1146                         stat = USB_ST_CRC_ERR;
1147                         break;
1148                 }
1149                 if (stat >= 0 && stat != 0xff) {
1150                         /* 0xff is returned for an SF-interrupt */
1151                         break;
1152                 }
1153                 if (--timeout) {
1154                         udelay(250); /* mdelay(1); */
1155                 } else {
1156                         err("CTL:TIMEOUT ");
1157                         stat = USB_ST_CRC_ERR;
1158                         break;
1159                 }
1160         }
1161         /* we got an Root Hub Status Change interrupt */
1162         if (got_rhsc) {
1163 #ifdef DEBUG
1164                 ohci_dump_roothub (&gohci, 1);
1165 #endif
1166                 got_rhsc = 0;
1167                 /* abuse timeout */
1168                 timeout = rh_check_port_status(&gohci);
1169                 if (timeout >= 0) {
1170 #if 0 /* this does nothing useful, but leave it here in case that changes */
1171                         /* the called routine adds 1 to the passed value */
1172                         usb_hub_port_connect_change(gohci.rh.dev, timeout - 1);
1173 #endif
1174                         /*
1175                          * XXX
1176                          * This is potentially dangerous because it assumes
1177                          * that only one device is ever plugged in!
1178                          */
1179                         devgone = dev;
1180                 }
1181         }
1182
1183         dev->status = stat;
1184         dev->act_len = transfer_len;
1185
1186 #ifdef DEBUG
1187         pkt_print(dev, pipe, buffer, transfer_len, setup, "RET(ctlr)", usb_pipein(pipe));
1188 #else
1189         mdelay(1);
1190 #endif
1191
1192         /* free TDs in urb_priv */
1193         urb_free_priv (&urb_priv);
1194         return 0;
1195 }
1196
1197 /* submit routines called from usb.c */
1198 int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1199                 int transfer_len)
1200 {
1201         info("submit_bulk_msg");
1202         return submit_common_msg(dev, pipe, buffer, transfer_len, NULL, 0);
1203 }
1204
1205 int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1206                 int transfer_len, struct devrequest *setup)
1207 {
1208         int maxsize = usb_maxpacket(dev, pipe);
1209
1210         info("submit_control_msg");
1211 #ifdef DEBUG
1212         urb_priv.actual_length = 0;
1213         pkt_print(dev, pipe, buffer, transfer_len, setup, "SUB", usb_pipein(pipe));
1214 #else
1215         mdelay(1);
1216 #endif
1217         if (!maxsize) {
1218                 err("submit_control_message: pipesize for pipe %lx is zero",
1219                         pipe);
1220                 return -1;
1221         }
1222         if (((pipe >> 8) & 0x7f) == gohci.rh.devnum) {
1223                 gohci.rh.dev = dev;
1224                 /* root hub - redirect */
1225                 return ohci_submit_rh_msg(dev, pipe, buffer, transfer_len,
1226                         setup);
1227         }
1228
1229         return submit_common_msg(dev, pipe, buffer, transfer_len, setup, 0);
1230 }
1231
1232 int submit_int_msg(struct usb_device *dev, unsigned long pipe, void *buffer,
1233                 int transfer_len, int interval)
1234 {
1235         info("submit_int_msg");
1236         return -1;
1237 }
1238
1239 /*-------------------------------------------------------------------------*
1240  * HC functions
1241  *-------------------------------------------------------------------------*/
1242
1243 /* reset the HC and BUS */
1244
1245 static int hc_reset (ohci_t *ohci)
1246 {
1247         int timeout = 30;
1248         int smm_timeout = 50; /* 0,5 sec */
1249
1250         if (readl (&ohci->regs->control) & OHCI_CTRL_IR) { /* SMM owns the HC */
1251                 writel (OHCI_OCR, &ohci->regs->cmdstatus); /* request ownership */
1252                 info("USB HC TakeOver from SMM");
1253                 while (readl (&ohci->regs->control) & OHCI_CTRL_IR) {
1254                         mdelay (10);
1255                         if (--smm_timeout == 0) {
1256                                 err("USB HC TakeOver failed!");
1257                                 return -1;
1258                         }
1259                 }
1260         }
1261
1262         /* Disable HC interrupts */
1263         writel (OHCI_INTR_MIE, &ohci->regs->intrdisable);
1264
1265         dbg("USB HC reset_hc usb-%s: ctrl = 0x%X ;",
1266                 ohci->slot_name,
1267                 readl (&ohci->regs->control));
1268
1269         /* Reset USB (needed by some controllers) */
1270         writel (0, &ohci->regs->control);
1271
1272         /* HC Reset requires max 10 us delay */
1273         writel (OHCI_HCR,  &ohci->regs->cmdstatus);
1274         while ((readl (&ohci->regs->cmdstatus) & OHCI_HCR) != 0) {
1275                 if (--timeout == 0) {
1276                         err("USB HC reset timed out!");
1277                         return -1;
1278                 }
1279                 udelay (1);
1280         }
1281         return 0;
1282 }
1283
1284 /*-------------------------------------------------------------------------*/
1285
1286 /* Start an OHCI controller, set the BUS operational
1287  * enable interrupts
1288  * connect the virtual root hub */
1289
1290 static int hc_start (ohci_t * ohci)
1291 {
1292         __u32 mask;
1293         unsigned int fminterval;
1294
1295         ohci->disabled = 1;
1296
1297         /* Tell the controller where the control and bulk lists are
1298          * The lists are empty now. */
1299
1300         writel (0, &ohci->regs->ed_controlhead);
1301         writel (0, &ohci->regs->ed_bulkhead);
1302
1303         writel ((__u32)ohci->hcca, &ohci->regs->hcca); /* a reset clears this */
1304
1305         fminterval = 0x2edf;
1306         writel ((fminterval * 9) / 10, &ohci->regs->periodicstart);
1307         fminterval |= ((((fminterval - 210) * 6) / 7) << 16);
1308         writel (fminterval, &ohci->regs->fminterval);
1309         writel (0x628, &ohci->regs->lsthresh);
1310
1311         /* start controller operations */
1312         ohci->hc_control = OHCI_CONTROL_INIT | OHCI_USB_OPER;
1313         ohci->disabled = 0;
1314         writel (ohci->hc_control, &ohci->regs->control);
1315
1316         /* disable all interrupts */
1317         mask = (OHCI_INTR_SO | OHCI_INTR_WDH | OHCI_INTR_SF | OHCI_INTR_RD |
1318                         OHCI_INTR_UE | OHCI_INTR_FNO | OHCI_INTR_RHSC |
1319                         OHCI_INTR_OC | OHCI_INTR_MIE);
1320         writel (mask, &ohci->regs->intrdisable);
1321         /* clear all interrupts */
1322         mask &= ~OHCI_INTR_MIE;
1323         writel (mask, &ohci->regs->intrstatus);
1324         /* Choose the interrupts we care about now  - but w/o MIE */
1325         mask = OHCI_INTR_RHSC | OHCI_INTR_UE | OHCI_INTR_WDH | OHCI_INTR_SO;
1326         writel (mask, &ohci->regs->intrenable);
1327
1328 #ifdef  OHCI_USE_NPS
1329         /* required for AMD-756 and some Mac platforms */
1330         writel ((roothub_a (ohci) | RH_A_NPS) & ~RH_A_PSM,
1331                 &ohci->regs->roothub.a);
1332         writel (RH_HS_LPSC, &ohci->regs->roothub.status);
1333 #endif  /* OHCI_USE_NPS */
1334
1335         /* POTPGT delay is bits 24-31, in 2 ms units. */
1336         mdelay ((roothub_a (ohci) >> 23) & 0x1fe);
1337
1338         /* connect the virtual root hub */
1339         ohci->rh.devnum = 0;
1340
1341         return 0;
1342 }
1343
1344 /*-------------------------------------------------------------------------*/
1345
1346 /* an interrupt happens */
1347
1348 static int
1349 hc_interrupt (void)
1350 {
1351         ohci_t *ohci = &gohci;
1352         struct ohci_regs *regs = ohci->regs;
1353         int ints;
1354         int stat = -1;
1355
1356         if ((ohci->hcca->done_head != 0) && !(m32_swap (ohci->hcca->done_head) & 0x01)) {
1357                 ints =  OHCI_INTR_WDH;
1358         } else {
1359                 ints = readl (&regs->intrstatus);
1360         }
1361
1362         /* dbg("Interrupt: %x frame: %x", ints, le16_to_cpu (ohci->hcca->frame_no)); */
1363
1364         if (ints & OHCI_INTR_RHSC) {
1365                 got_rhsc = 1;
1366         }
1367
1368         if (ints & OHCI_INTR_UE) {
1369                 ohci->disabled++;
1370                 err ("OHCI Unrecoverable Error, controller usb-%s disabled",
1371                         ohci->slot_name);
1372                 /* e.g. due to PCI Master/Target Abort */
1373
1374 #ifdef  DEBUG
1375                 ohci_dump (ohci, 1);
1376 #else
1377         mdelay(1);
1378 #endif
1379                 /* FIXME: be optimistic, hope that bug won't repeat often. */
1380                 /* Make some non-interrupt context restart the controller. */
1381                 /* Count and limit the retries though; either hardware or */
1382                 /* software errors can go forever... */
1383                 hc_reset (ohci);
1384                 return -1;
1385         }
1386
1387         if (ints & OHCI_INTR_WDH) {
1388                 mdelay(1);
1389                 writel (OHCI_INTR_WDH, &regs->intrdisable);
1390                 stat = dl_done_list (&gohci, dl_reverse_done_list (&gohci));
1391                 writel (OHCI_INTR_WDH, &regs->intrenable);
1392         }
1393
1394         if (ints & OHCI_INTR_SO) {
1395                 dbg("USB Schedule overrun\n");
1396                 writel (OHCI_INTR_SO, &regs->intrenable);
1397                 stat = -1;
1398         }
1399
1400         /* FIXME:  this assumes SOF (1/ms) interrupts don't get lost... */
1401         if (ints & OHCI_INTR_SF) {
1402                 unsigned int frame = m16_swap (ohci->hcca->frame_no) & 1;
1403                 mdelay(1);
1404                 writel (OHCI_INTR_SF, &regs->intrdisable);
1405                 if (ohci->ed_rm_list[frame] != NULL)
1406                         writel (OHCI_INTR_SF, &regs->intrenable);
1407                 stat = 0xff;
1408         }
1409
1410         writel (ints, &regs->intrstatus);
1411         return stat;
1412 }
1413
1414 /*-------------------------------------------------------------------------*/
1415
1416 /*-------------------------------------------------------------------------*/
1417
1418 /* De-allocate all resources.. */
1419
1420 static void hc_release_ohci (ohci_t *ohci)
1421 {
1422         dbg ("USB HC release ohci usb-%s", ohci->slot_name);
1423
1424         if (!ohci->disabled)
1425                 hc_reset (ohci);
1426 }
1427
1428 /*-------------------------------------------------------------------------*/
1429
1430 #define __read_32bit_c0_register(source, sel)                           \
1431 ({ int __res;                                                           \
1432         if (sel == 0)                                                   \
1433                 __asm__ __volatile__(                                   \
1434                         "mfc0\t%0, " #source "\n\t"                     \
1435                         : "=r" (__res));                                \
1436         else                                                            \
1437                 __asm__ __volatile__(                                   \
1438                         ".set\tmips32\n\t"                              \
1439                         "mfc0\t%0, " #source ", " #sel "\n\t"           \
1440                         ".set\tmips0\n\t"                               \
1441                         : "=r" (__res));                                \
1442         __res;                                                          \
1443 })
1444
1445 #define read_c0_prid()          __read_32bit_c0_register($15, 0)
1446
1447 /*
1448  * low level initalisation routine, called from usb.c
1449  */
1450 static char ohci_inited = 0;
1451
1452 int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
1453 {
1454         u32 pin_func;
1455         u32 sys_freqctrl, sys_clksrc;
1456         u32 prid = read_c0_prid();
1457
1458         dbg("in usb_lowlevel_init\n");
1459
1460         /* zero and disable FREQ2 */
1461         sys_freqctrl = au_readl(SYS_FREQCTRL0);
1462         sys_freqctrl &= ~0xFFF00000;
1463         au_writel(sys_freqctrl, SYS_FREQCTRL0);
1464
1465         /* zero and disable USBH/USBD clocks */
1466         sys_clksrc = au_readl(SYS_CLKSRC);
1467         sys_clksrc &= ~0x00007FE0;
1468         au_writel(sys_clksrc, SYS_CLKSRC);
1469
1470         sys_freqctrl = au_readl(SYS_FREQCTRL0);
1471         sys_freqctrl &= ~0xFFF00000;
1472
1473         sys_clksrc = au_readl(SYS_CLKSRC);
1474         sys_clksrc &= ~0x00007FE0;
1475
1476         switch (prid & 0x000000FF) {
1477         case 0x00: /* DA */
1478         case 0x01: /* HA */
1479         case 0x02: /* HB */
1480                 /* CPU core freq to 48MHz to slow it way down... */
1481                 au_writel(4, SYS_CPUPLL);
1482
1483                 /*
1484                  * Setup 48MHz FREQ2 from CPUPLL for USB Host
1485                  */
1486                 /* FRDIV2=3 -> div by 8 of 384MHz -> 48MHz */
1487                 sys_freqctrl |= ((3<<22) | (1<<21) | (0<<20));
1488                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1489
1490                 /* CPU core freq to 384MHz */
1491                 au_writel(0x20, SYS_CPUPLL);
1492
1493                 printf("Au1000: 48MHz OHCI workaround enabled\n");
1494                 break;
1495
1496         default:  /* HC and newer */
1497                 /* FREQ2 = aux/2 = 48 MHz */
1498                 sys_freqctrl |= ((0<<22) | (1<<21) | (1<<20));
1499                 au_writel(sys_freqctrl, SYS_FREQCTRL0);
1500                 break;
1501         }
1502
1503         /*
1504          * Route 48MHz FREQ2 into USB Host and/or Device
1505          */
1506         sys_clksrc |= ((4<<12) | (0<<11) | (0<<10));
1507         au_writel(sys_clksrc, SYS_CLKSRC);
1508
1509         /* configure pins GPIO[14:9] as GPIO */
1510         pin_func = au_readl(SYS_PINFUNC) & (u32)(~0x8080);
1511
1512         au_writel(pin_func, SYS_PINFUNC);
1513         au_writel(0x2800, SYS_TRIOUTCLR);
1514         au_writel(0x0030, SYS_OUTPUTCLR);
1515
1516         dbg("OHCI board setup complete\n");
1517
1518         /* enable host controller */
1519         au_writel(USBH_ENABLE_CE, USB_HOST_CONFIG);
1520         udelay(1000);
1521         au_writel(USBH_ENABLE_INIT, USB_HOST_CONFIG);
1522         udelay(1000);
1523
1524         /* wait for reset complete (read register twice; see au1500 errata) */
1525         while (au_readl(USB_HOST_CONFIG),
1526                !(au_readl(USB_HOST_CONFIG) & USBH_ENABLE_RD))
1527                 udelay(1000);
1528
1529         dbg("OHCI clock running\n");
1530
1531         memset (&gohci, 0, sizeof (ohci_t));
1532         memset (&urb_priv, 0, sizeof (urb_priv_t));
1533
1534         /* align the storage */
1535         if ((__u32)&ghcca[0] & 0xff) {
1536                 err("HCCA not aligned!!");
1537                 return -1;
1538         }
1539         phcca = &ghcca[0];
1540         info("aligned ghcca %p", phcca);
1541         memset(&ohci_dev, 0, sizeof(struct ohci_device));
1542         if ((__u32)&ohci_dev.ed[0] & 0x7) {
1543                 err("EDs not aligned!!");
1544                 return -1;
1545         }
1546         memset(gtd, 0, sizeof(td_t) * (NUM_TD + 1));
1547         if ((__u32)gtd & 0x7) {
1548                 err("TDs not aligned!!");
1549                 return -1;
1550         }
1551         ptd = gtd;
1552         gohci.hcca = phcca;
1553         memset (phcca, 0, sizeof (struct ohci_hcca));
1554
1555         gohci.disabled = 1;
1556         gohci.sleeping = 0;
1557         gohci.irq = -1;
1558         gohci.regs = (struct ohci_regs *)(USB_OHCI_BASE | 0xA0000000);
1559
1560         gohci.flags = 0;
1561         gohci.slot_name = "au1x00";
1562
1563         dbg("OHCI revision: 0x%08x\n"
1564                "  RH: a: 0x%08x b: 0x%08x\n",
1565                readl(&gohci.regs->revision),
1566                readl(&gohci.regs->roothub.a), readl(&gohci.regs->roothub.b));
1567
1568         if (hc_reset (&gohci) < 0)
1569                 goto errout;
1570
1571         /* FIXME this is a second HC reset; why?? */
1572         writel (gohci.hc_control = OHCI_USB_RESET, &gohci.regs->control);
1573         mdelay (10);
1574
1575         if (hc_start (&gohci) < 0)
1576                 goto errout;
1577
1578 #ifdef  DEBUG
1579         ohci_dump (&gohci, 1);
1580 #else
1581         mdelay(1);
1582 #endif
1583         ohci_inited = 1;
1584         return 0;
1585
1586   errout:
1587         err("OHCI initialization error\n");
1588         hc_release_ohci (&gohci);
1589         /* Initialization failed */
1590         au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1591         return -1;
1592 }
1593
1594 int usb_lowlevel_stop(int index)
1595 {
1596         /* this gets called really early - before the controller has */
1597         /* even been initialized! */
1598         if (!ohci_inited)
1599                 return 0;
1600         /* TODO release any interrupts, etc. */
1601         /* call hc_release_ohci() here ? */
1602         hc_reset (&gohci);
1603         /* may not want to do this */
1604         /* Disable clock */
1605         au_writel(readl(USB_HOST_CONFIG) & ~USBH_ENABLE_CE, USB_HOST_CONFIG);
1606         return 0;
1607 }
1608
1609 #endif /* CONFIG_USB_OHCI */