arch/powerpc/cpu/74xx_7xx/kgdb.S

   1 /*
   2  *  Copyright (C) 2000  Murray Jensen <Murray.Jensen@cmst.csiro.au>
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <config.h>
   8 #include <command.h>
   9 #include <74xx_7xx.h>
  10 #include <version.h>
  11
  12 #include <ppc_asm.tmpl>
  13 #include <ppc_defs.h>
  14
  15 #include <asm/cache.h>
  16 #include <asm/mmu.h>
  17
  18 #if defined(CONFIG_CMD_KGDB)
  19
  20  /*
  21  * cache flushing routines for kgdb
  22  */
  23
  24         .globl  kgdb_flush_cache_all
  25 kgdb_flush_cache_all:
  26         lis     r3,0
  27         addis   r4,r0,0x0040
  28 kgdb_flush_loop:
  29         lwz     r5,0(r3)
  30         addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
  31         cmp     0,0,r3,r4
  32         bne     kgdb_flush_loop
  33         SYNC
  34         mfspr   r3,1008
  35         ori     r3,r3,0x8800
  36         mtspr   1008,r3
  37         sync
  38         blr
  39
  40         .globl  kgdb_flush_cache_range
  41 kgdb_flush_cache_range:
  42         li      r5,CONFIG_SYS_CACHELINE_SIZE-1
  43         andc    r3,r3,r5
  44         subf    r4,r3,r4
  45         add     r4,r4,r5
  46         srwi.   r4,r4,CONFIG_SYS_CACHELINE_SHIFT
  47         beqlr
  48         mtctr   r4
  49         mr      r6,r3
  50 1:      dcbst   0,r3
  51         addi    r3,r3,CONFIG_SYS_CACHELINE_SIZE
  52         bdnz    1b
  53         sync                            /* wait for dcbst's to get to ram */
  54         mtctr   r4
  55 2:      icbi    0,r6
  56         addi    r6,r6,CONFIG_SYS_CACHELINE_SIZE
  57         bdnz    2b
  58         SYNC
  59         blr
  60
  61 #endif