arch/powerpc/cpu/mpc8xxx/ddr/main.c

   1 /*
   2  * Copyright 2008-2012 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 /*
  10  * Generic driver for Freescale DDR/DDR2/DDR3 memory controller.
  11  * Based on code from spd_sdram.c
  12  * Author: James Yang [at freescale.com]
  13  */
  14
  15 #include <common.h>
  16 #include <i2c.h>
  17 #include <asm/fsl_ddr_sdram.h>
  18 #include <asm/fsl_law.h>
  19
  20 #include "ddr.h"
  21
  22 void fsl_ddr_set_lawbar(
  23                 const common_timing_params_t *memctl_common_params,
  24                 unsigned int memctl_interleaved,
  25                 unsigned int ctrl_num);
  26 void fsl_ddr_set_intl3r(const unsigned int granule_size);
  27
  28 #if defined(SPD_EEPROM_ADDRESS) || \
  29     defined(SPD_EEPROM_ADDRESS1) || defined(SPD_EEPROM_ADDRESS2) || \
  30     defined(SPD_EEPROM_ADDRESS3) || defined(SPD_EEPROM_ADDRESS4)
  31 #if (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  32 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  33         [0][0] = SPD_EEPROM_ADDRESS,
  34 };
  35 #elif (CONFIG_NUM_DDR_CONTROLLERS == 1) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  36 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  37         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  38         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  39 };
  40 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  41 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  42         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  43         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  44 };
  45 #elif (CONFIG_NUM_DDR_CONTROLLERS == 2) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  46 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  47         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  48         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  49         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  50         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  51 };
  52 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 1)
  53 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  54         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  55         [1][0] = SPD_EEPROM_ADDRESS2,   /* controller 2 */
  56         [2][0] = SPD_EEPROM_ADDRESS3,   /* controller 3 */
  57 };
  58 #elif (CONFIG_NUM_DDR_CONTROLLERS == 3) && (CONFIG_DIMM_SLOTS_PER_CTLR == 2)
  59 u8 spd_i2c_addr[CONFIG_NUM_DDR_CONTROLLERS][CONFIG_DIMM_SLOTS_PER_CTLR] = {
  60         [0][0] = SPD_EEPROM_ADDRESS1,   /* controller 1 */
  61         [0][1] = SPD_EEPROM_ADDRESS2,   /* controller 1 */
  62         [1][0] = SPD_EEPROM_ADDRESS3,   /* controller 2 */
  63         [1][1] = SPD_EEPROM_ADDRESS4,   /* controller 2 */
  64         [2][0] = SPD_EEPROM_ADDRESS5,   /* controller 3 */
  65         [2][1] = SPD_EEPROM_ADDRESS6,   /* controller 3 */
  66 };
  67
  68 #endif
  69
  70 static void __get_spd(generic_spd_eeprom_t *spd, u8 i2c_address)
  71 {
  72         int ret = i2c_read(i2c_address, 0, 1, (uchar *)spd,
  73                                 sizeof(generic_spd_eeprom_t));
  74
  75         if (ret) {
  76                 if (i2c_address ==
  77 #ifdef SPD_EEPROM_ADDRESS
  78                                 SPD_EEPROM_ADDRESS
  79 #elif defined(SPD_EEPROM_ADDRESS1)
  80                                 SPD_EEPROM_ADDRESS1
  81 #endif
  82                                 ) {
  83                         printf("DDR: failed to read SPD from address %u\n",
  84                                 i2c_address);
  85                 } else {
  86                         debug("DDR: failed to read SPD from address %u\n",
  87                                 i2c_address);
  88                 }
  89                 memset(spd, 0, sizeof(generic_spd_eeprom_t));
  90         }
  91 }
  92
  93 __attribute__((weak, alias("__get_spd")))
  94 void get_spd(generic_spd_eeprom_t *spd, u8 i2c_address);
  95
  96 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
  97                       unsigned int ctrl_num)
  98 {
  99         unsigned int i;
 100         unsigned int i2c_address = 0;
 101
 102         if (ctrl_num >= CONFIG_NUM_DDR_CONTROLLERS) {
 103                 printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num);
 104                 return;
 105         }
 106
 107         for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
 108                 i2c_address = spd_i2c_addr[ctrl_num][i];
 109                 get_spd(&(ctrl_dimms_spd[i]), i2c_address);
 110         }
 111 }
 112 #else
 113 void fsl_ddr_get_spd(generic_spd_eeprom_t *ctrl_dimms_spd,
 114                       unsigned int ctrl_num)
 115 {
 116 }
 117 #endif /* SPD_EEPROM_ADDRESSx */
 118
 119 /*
 120  * ASSUMPTIONS:
 121  *    - Same number of CONFIG_DIMM_SLOTS_PER_CTLR on each controller
 122  *    - Same memory data bus width on all controllers
 123  *
 124  * NOTES:
 125  *
 126  * The memory controller and associated documentation use confusing
 127  * terminology when referring to the orgranization of DRAM.
 128  *
 129  * Here is a terminology translation table:
 130  *
 131  * memory controller/documention  |industry   |this code  |signals
 132  * -------------------------------|-----------|-----------|-----------------
 133  * physical bank/bank             |rank       |rank       |chip select (CS)
 134  * logical bank/sub-bank          |bank       |bank       |bank address (BA)
 135  * page/row                       |row        |page       |row address
 136  * ???                            |column     |column     |column address
 137  *
 138  * The naming confusion is further exacerbated by the descriptions of the
 139  * memory controller interleaving feature, where accesses are interleaved
 140  * _BETWEEN_ two seperate memory controllers.  This is configured only in
 141  * CS0_CONFIG[INTLV_CTL] of each memory controller.
 142  *
 143  * memory controller documentation | number of chip selects
 144  *                                 | per memory controller supported
 145  * --------------------------------|-----------------------------------------
 146  * cache line interleaving         | 1 (CS0 only)
 147  * page interleaving               | 1 (CS0 only)
 148  * bank interleaving               | 1 (CS0 only)
 149  * superbank interleraving         | depends on bank (chip select)
 150  *                                 |   interleraving [rank interleaving]
 151  *                                 |   mode used on every memory controller
 152  *
 153  * Even further confusing is the existence of the interleaving feature
 154  * _WITHIN_ each memory controller.  The feature is referred to in
 155  * documentation as chip select interleaving or bank interleaving,
 156  * although it is configured in the DDR_SDRAM_CFG field.
 157  *
 158  * Name of field                | documentation name    | this code
 159  * -----------------------------|-----------------------|------------------
 160  * DDR_SDRAM_CFG[BA_INTLV_CTL]  | Bank (chip select)    | rank interleaving
 161  *                              |  interleaving
 162  */
 163
 164 const char *step_string_tbl[] = {
 165         "STEP_GET_SPD",
 166         "STEP_COMPUTE_DIMM_PARMS",
 167         "STEP_COMPUTE_COMMON_PARMS",
 168         "STEP_GATHER_OPTS",
 169         "STEP_ASSIGN_ADDRESSES",
 170         "STEP_COMPUTE_REGS",
 171         "STEP_PROGRAM_REGS",
 172         "STEP_ALL"
 173 };
 174
 175 const char * step_to_string(unsigned int step) {
 176
 177         unsigned int s = __ilog2(step);
 178
 179         if ((1 << s) != step)
 180                 return step_string_tbl[7];
 181
 182         return step_string_tbl[s];
 183 }
 184
 185 static unsigned long long __step_assign_addresses(fsl_ddr_info_t *pinfo,
 186                           unsigned int dbw_cap_adj[])
 187 {
 188         int i, j;
 189         unsigned long long total_mem, current_mem_base, total_ctlr_mem;
 190         unsigned long long rank_density, ctlr_density = 0;
 191
 192         /*
 193          * If a reduced data width is requested, but the SPD
 194          * specifies a physically wider device, adjust the
 195          * computed dimm capacities accordingly before
 196          * assigning addresses.
 197          */
 198         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 199                 unsigned int found = 0;
 200
 201                 switch (pinfo->memctl_opts[i].data_bus_width) {
 202                 case 2:
 203                         /* 16-bit */
 204                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 205                                 unsigned int dw;
 206                                 if (!pinfo->dimm_params[i][j].n_ranks)
 207                                         continue;
 208                                 dw = pinfo->dimm_params[i][j].primary_sdram_width;
 209                                 if ((dw == 72 || dw == 64)) {
 210                                         dbw_cap_adj[i] = 2;
 211                                         break;
 212                                 } else if ((dw == 40 || dw == 32)) {
 213                                         dbw_cap_adj[i] = 1;
 214                                         break;
 215                                 }
 216                         }
 217                         break;
 218
 219                 case 1:
 220                         /* 32-bit */
 221                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 222                                 unsigned int dw;
 223                                 dw = pinfo->dimm_params[i][j].data_width;
 224                                 if (pinfo->dimm_params[i][j].n_ranks
 225                                     && (dw == 72 || dw == 64)) {
 226                                         /*
 227                                          * FIXME: can't really do it
 228                                          * like this because this just
 229                                          * further reduces the memory
 230                                          */
 231                                         found = 1;
 232                                         break;
 233                                 }
 234                         }
 235                         if (found) {
 236                                 dbw_cap_adj[i] = 1;
 237                         }
 238                         break;
 239
 240                 case 0:
 241                         /* 64-bit */
 242                         break;
 243
 244                 default:
 245                         printf("unexpected data bus width "
 246                                 "specified controller %u\n", i);
 247                         return 1;
 248                 }
 249                 debug("dbw_cap_adj[%d]=%d\n", i, dbw_cap_adj[i]);
 250         }
 251
 252         current_mem_base = 0ull;
 253         total_mem = 0;
 254         if (pinfo->memctl_opts[0].memctl_interleaving) {
 255                 rank_density = pinfo->dimm_params[0][0].rank_density >>
 256                                         dbw_cap_adj[0];
 257                 switch (pinfo->memctl_opts[0].ba_intlv_ctl &
 258                                         FSL_DDR_CS0_CS1_CS2_CS3) {
 259                 case FSL_DDR_CS0_CS1_CS2_CS3:
 260                         ctlr_density = 4 * rank_density;
 261                         break;
 262                 case FSL_DDR_CS0_CS1:
 263                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 264                         ctlr_density = 2 * rank_density;
 265                         break;
 266                 case FSL_DDR_CS2_CS3:
 267                 default:
 268                         ctlr_density = rank_density;
 269                         break;
 270                 }
 271                 debug("rank density is 0x%llx, ctlr density is 0x%llx\n",
 272                         rank_density, ctlr_density);
 273                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 274                         if (pinfo->memctl_opts[i].memctl_interleaving) {
 275                                 switch (pinfo->memctl_opts[i].memctl_interleaving_mode) {
 276                                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 277                                 case FSL_DDR_PAGE_INTERLEAVING:
 278                                 case FSL_DDR_BANK_INTERLEAVING:
 279                                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 280                                         total_ctlr_mem = 2 * ctlr_density;
 281                                         break;
 282                                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 283                                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 284                                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 285                                         total_ctlr_mem = 3 * ctlr_density;
 286                                         break;
 287                                 case FSL_DDR_4WAY_1KB_INTERLEAVING:
 288                                 case FSL_DDR_4WAY_4KB_INTERLEAVING:
 289                                 case FSL_DDR_4WAY_8KB_INTERLEAVING:
 290                                         total_ctlr_mem = 4 * ctlr_density;
 291                                         break;
 292                                 default:
 293                                         panic("Unknown interleaving mode");
 294                                 }
 295                                 pinfo->common_timing_params[i].base_address =
 296                                                         current_mem_base;
 297                                 pinfo->common_timing_params[i].total_mem =
 298                                                         total_ctlr_mem;
 299                                 total_mem = current_mem_base + total_ctlr_mem;
 300                                 debug("ctrl %d base 0x%llx\n", i, current_mem_base);
 301                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 302                         } else {
 303                                 /* when 3rd controller not interleaved */
 304                                 current_mem_base = total_mem;
 305                                 total_ctlr_mem = 0;
 306                                 pinfo->common_timing_params[i].base_address =
 307                                                         current_mem_base;
 308                                 for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 309                                         unsigned long long cap =
 310                                                 pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 311                                         pinfo->dimm_params[i][j].base_address =
 312                                                 current_mem_base;
 313                                         debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 314                                         current_mem_base += cap;
 315                                         total_ctlr_mem += cap;
 316                                 }
 317                                 debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 318                                 pinfo->common_timing_params[i].total_mem =
 319                                                         total_ctlr_mem;
 320                                 total_mem += total_ctlr_mem;
 321                         }
 322                 }
 323         } else {
 324                 /*
 325                  * Simple linear assignment if memory
 326                  * controllers are not interleaved.
 327                  */
 328                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 329                         total_ctlr_mem = 0;
 330                         pinfo->common_timing_params[i].base_address =
 331                                                 current_mem_base;
 332                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 333                                 /* Compute DIMM base addresses. */
 334                                 unsigned long long cap =
 335                                         pinfo->dimm_params[i][j].capacity >> dbw_cap_adj[i];
 336                                 pinfo->dimm_params[i][j].base_address =
 337                                         current_mem_base;
 338                                 debug("ctrl %d dimm %d base 0x%llx\n", i, j, current_mem_base);
 339                                 current_mem_base += cap;
 340                                 total_ctlr_mem += cap;
 341                         }
 342                         debug("ctrl %d total 0x%llx\n", i, total_ctlr_mem);
 343                         pinfo->common_timing_params[i].total_mem =
 344                                                         total_ctlr_mem;
 345                         total_mem += total_ctlr_mem;
 346                 }
 347         }
 348         debug("Total mem by %s is 0x%llx\n", __func__, total_mem);
 349
 350         return total_mem;
 351 }
 352
 353 /* Use weak function to allow board file to override the address assignment */
 354 __attribute__((weak, alias("__step_assign_addresses")))
 355 unsigned long long step_assign_addresses(fsl_ddr_info_t *pinfo,
 356                           unsigned int dbw_cap_adj[]);
 357
 358 unsigned long long
 359 fsl_ddr_compute(fsl_ddr_info_t *pinfo, unsigned int start_step,
 360                                        unsigned int size_only)
 361 {
 362         unsigned int i, j;
 363         unsigned long long total_mem = 0;
 364         int assert_reset;
 365
 366         fsl_ddr_cfg_regs_t *ddr_reg = pinfo->fsl_ddr_config_reg;
 367         common_timing_params_t *timing_params = pinfo->common_timing_params;
 368         assert_reset = board_need_mem_reset();
 369
 370         /* data bus width capacity adjust shift amount */
 371         unsigned int dbw_capacity_adjust[CONFIG_NUM_DDR_CONTROLLERS];
 372
 373         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 374                 dbw_capacity_adjust[i] = 0;
 375         }
 376
 377         debug("starting at step %u (%s)\n",
 378               start_step, step_to_string(start_step));
 379
 380         switch (start_step) {
 381         case STEP_GET_SPD:
 382 #if defined(CONFIG_DDR_SPD) || defined(CONFIG_SPD_EEPROM)
 383                 /* STEP 1:  Gather all DIMM SPD data */
 384                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 385                         fsl_ddr_get_spd(pinfo->spd_installed_dimms[i], i);
 386                 }
 387
 388         case STEP_COMPUTE_DIMM_PARMS:
 389                 /* STEP 2:  Compute DIMM parameters from SPD data */
 390
 391                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 392                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 393                                 unsigned int retval;
 394                                 generic_spd_eeprom_t *spd =
 395                                         &(pinfo->spd_installed_dimms[i][j]);
 396                                 dimm_params_t *pdimm =
 397                                         &(pinfo->dimm_params[i][j]);
 398
 399                                 retval = compute_dimm_parameters(spd, pdimm, i);
 400 #ifdef CONFIG_SYS_DDR_RAW_TIMING
 401                                 if (!i && !j && retval) {
 402                                         printf("SPD error on controller %d! "
 403                                         "Trying fallback to raw timing "
 404                                         "calculation\n", i);
 405                                         fsl_ddr_get_dimm_params(pdimm, i, j);
 406                                 }
 407 #else
 408                                 if (retval == 2) {
 409                                         printf("Error: compute_dimm_parameters"
 410                                         " non-zero returned FATAL value "
 411                                         "for memctl=%u dimm=%u\n", i, j);
 412                                         return 0;
 413                                 }
 414 #endif
 415                                 if (retval) {
 416                                         debug("Warning: compute_dimm_parameters"
 417                                         " non-zero return value for memctl=%u "
 418                                         "dimm=%u\n", i, j);
 419                                 }
 420                         }
 421                 }
 422
 423 #elif defined(CONFIG_SYS_DDR_RAW_TIMING)
 424         case STEP_COMPUTE_DIMM_PARMS:
 425                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 426                         for (j = 0; j < CONFIG_DIMM_SLOTS_PER_CTLR; j++) {
 427                                 dimm_params_t *pdimm =
 428                                         &(pinfo->dimm_params[i][j]);
 429                                 fsl_ddr_get_dimm_params(pdimm, i, j);
 430                         }
 431                 }
 432                 debug("Filling dimm parameters from board specific file\n");
 433 #endif
 434         case STEP_COMPUTE_COMMON_PARMS:
 435                 /*
 436                  * STEP 3: Compute a common set of timing parameters
 437                  * suitable for all of the DIMMs on each memory controller
 438                  */
 439                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 440                         debug("Computing lowest common DIMM"
 441                                 " parameters for memctl=%u\n", i);
 442                         compute_lowest_common_dimm_parameters(
 443                                 pinfo->dimm_params[i],
 444                                 &timing_params[i],
 445                                 CONFIG_DIMM_SLOTS_PER_CTLR);
 446                 }
 447
 448         case STEP_GATHER_OPTS:
 449                 /* STEP 4:  Gather configuration requirements from user */
 450                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 451                         debug("Reloading memory controller "
 452                                 "configuration options for memctl=%u\n", i);
 453                         /*
 454                          * This "reloads" the memory controller options
 455                          * to defaults.  If the user "edits" an option,
 456                          * next_step points to the step after this,
 457                          * which is currently STEP_ASSIGN_ADDRESSES.
 458                          */
 459                         populate_memctl_options(
 460                                         timing_params[i].all_DIMMs_registered,
 461                                         &pinfo->memctl_opts[i],
 462                                         pinfo->dimm_params[i], i);
 463                         /*
 464                          * For RDIMMs, JEDEC spec requires clocks to be stable
 465                          * before reset signal is deasserted. For the boards
 466                          * using fixed parameters, this function should be
 467                          * be called from board init file.
 468                          */
 469                         if (timing_params[i].all_DIMMs_registered)
 470                                 assert_reset = 1;
 471                 }
 472                 if (assert_reset) {
 473                         debug("Asserting mem reset\n");
 474                         board_assert_mem_reset();
 475                 }
 476
 477         case STEP_ASSIGN_ADDRESSES:
 478                 /* STEP 5:  Assign addresses to chip selects */
 479                 check_interleaving_options(pinfo);
 480                 total_mem = step_assign_addresses(pinfo, dbw_capacity_adjust);
 481
 482         case STEP_COMPUTE_REGS:
 483                 /* STEP 6:  compute controller register values */
 484                 debug("FSL Memory ctrl register computation\n");
 485                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 486                         if (timing_params[i].ndimms_present == 0) {
 487                                 memset(&ddr_reg[i], 0,
 488                                         sizeof(fsl_ddr_cfg_regs_t));
 489                                 continue;
 490                         }
 491
 492                         compute_fsl_memctl_config_regs(
 493                                         &pinfo->memctl_opts[i],
 494                                         &ddr_reg[i], &timing_params[i],
 495                                         pinfo->dimm_params[i],
 496                                         dbw_capacity_adjust[i],
 497                                         size_only);
 498                 }
 499
 500         default:
 501                 break;
 502         }
 503
 504         {
 505                 /*
 506                  * Compute the amount of memory available just by
 507                  * looking for the highest valid CSn_BNDS value.
 508                  * This allows us to also experiment with using
 509                  * only CS0 when using dual-rank DIMMs.
 510                  */
 511                 unsigned int max_end = 0;
 512
 513                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 514                         for (j = 0; j < CONFIG_CHIP_SELECTS_PER_CTRL; j++) {
 515                                 fsl_ddr_cfg_regs_t *reg = &ddr_reg[i];
 516                                 if (reg->cs[j].config & 0x80000000) {
 517                                         unsigned int end;
 518                                         /*
 519                                          * 0xfffffff is a special value we put
 520                                          * for unused bnds
 521                                          */
 522                                         if (reg->cs[j].bnds == 0xffffffff)
 523                                                 continue;
 524                                         end = reg->cs[j].bnds & 0xffff;
 525                                         if (end > max_end) {
 526                                                 max_end = end;
 527                                         }
 528                                 }
 529                         }
 530                 }
 531
 532                 total_mem = 1 + (((unsigned long long)max_end << 24ULL)
 533                                     | 0xFFFFFFULL);
 534         }
 535
 536         return total_mem;
 537 }
 538
 539 /*
 540  * fsl_ddr_sdram() -- this is the main function to be called by
 541  *      initdram() in the board file.
 542  *
 543  * It returns amount of memory configured in bytes.
 544  */
 545 phys_size_t fsl_ddr_sdram(void)
 546 {
 547         unsigned int i;
 548         unsigned int law_memctl = LAW_TRGT_IF_DDR_1;
 549         unsigned long long total_memory;
 550         fsl_ddr_info_t info;
 551         int deassert_reset;
 552
 553         /* Reset info structure. */
 554         memset(&info, 0, sizeof(fsl_ddr_info_t));
 555
 556         /* Compute it once normally. */
 557 #ifdef CONFIG_FSL_DDR_INTERACTIVE
 558         if (tstc() && (getc() == 'd')) {        /* we got a key press of 'd' */
 559                 total_memory = fsl_ddr_interactive(&info, 0);
 560         } else if (fsl_ddr_interactive_env_var_exists()) {
 561                 total_memory = fsl_ddr_interactive(&info, 1);
 562         } else
 563 #endif
 564                 total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 0);
 565
 566         /* setup 3-way interleaving before enabling DDRC */
 567         if (info.memctl_opts[0].memctl_interleaving) {
 568                 switch (info.memctl_opts[0].memctl_interleaving_mode) {
 569                 case FSL_DDR_3WAY_1KB_INTERLEAVING:
 570                 case FSL_DDR_3WAY_4KB_INTERLEAVING:
 571                 case FSL_DDR_3WAY_8KB_INTERLEAVING:
 572                         fsl_ddr_set_intl3r(
 573                                 info.memctl_opts[0].memctl_interleaving_mode);
 574                         break;
 575                 default:
 576                         break;
 577                 }
 578         }
 579
 580         /*
 581          * Program configuration registers.
 582          * JEDEC specs requires clocks to be stable before deasserting reset
 583          * for RDIMMs. Clocks start after chip select is enabled and clock
 584          * control register is set. During step 1, all controllers have their
 585          * registers set but not enabled. Step 2 proceeds after deasserting
 586          * reset through board FPGA or GPIO.
 587          * For non-registered DIMMs, initialization can go through but it is
 588          * also OK to follow the same flow.
 589          */
 590         deassert_reset = board_need_mem_reset();
 591         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 592                 if (info.common_timing_params[i].all_DIMMs_registered)
 593                         deassert_reset = 1;
 594         }
 595         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 596                 debug("Programming controller %u\n", i);
 597                 if (info.common_timing_params[i].ndimms_present == 0) {
 598                         debug("No dimms present on controller %u; "
 599                                         "skipping programming\n", i);
 600                         continue;
 601                 }
 602                 /*
 603                  * The following call with step = 1 returns before enabling
 604                  * the controller. It has to finish with step = 2 later.
 605                  */
 606                 fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]), i,
 607                                         deassert_reset ? 1 : 0);
 608         }
 609         if (deassert_reset) {
 610                 /* Use board FPGA or GPIO to deassert reset signal */
 611                 debug("Deasserting mem reset\n");
 612                 board_deassert_mem_reset();
 613                 for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 614                         /* Call with step = 2 to continue initialization */
 615                         fsl_ddr_set_memctl_regs(&(info.fsl_ddr_config_reg[i]),
 616                                                 i, 2);
 617                 }
 618         }
 619
 620         /* program LAWs */
 621         for (i = 0; i < CONFIG_NUM_DDR_CONTROLLERS; i++) {
 622                 if (info.memctl_opts[i].memctl_interleaving) {
 623                         switch (info.memctl_opts[i].memctl_interleaving_mode) {
 624                         case FSL_DDR_CACHE_LINE_INTERLEAVING:
 625                         case FSL_DDR_PAGE_INTERLEAVING:
 626                         case FSL_DDR_BANK_INTERLEAVING:
 627                         case FSL_DDR_SUPERBANK_INTERLEAVING:
 628                                 if (i == 0) {
 629                                         law_memctl = LAW_TRGT_IF_DDR_INTRLV;
 630                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 631                                                 law_memctl, i);
 632                                 } else if (i == 2) {
 633                                         law_memctl = LAW_TRGT_IF_DDR_INTLV_34;
 634                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 635                                                 law_memctl, i);
 636                                 }
 637                                 break;
 638                         case FSL_DDR_3WAY_1KB_INTERLEAVING:
 639                         case FSL_DDR_3WAY_4KB_INTERLEAVING:
 640                         case FSL_DDR_3WAY_8KB_INTERLEAVING:
 641                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_123;
 642                                 if (i == 0) {
 643                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 644                                                 law_memctl, i);
 645                                 }
 646                                 break;
 647                         case FSL_DDR_4WAY_1KB_INTERLEAVING:
 648                         case FSL_DDR_4WAY_4KB_INTERLEAVING:
 649                         case FSL_DDR_4WAY_8KB_INTERLEAVING:
 650                                 law_memctl = LAW_TRGT_IF_DDR_INTLV_1234;
 651                                 if (i == 0)
 652                                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 653                                                 law_memctl, i);
 654                                 /* place holder for future 4-way interleaving */
 655                                 break;
 656                         default:
 657                                 break;
 658                         }
 659                 } else {
 660                         switch (i) {
 661                         case 0:
 662                                 law_memctl = LAW_TRGT_IF_DDR_1;
 663                                 break;
 664                         case 1:
 665                                 law_memctl = LAW_TRGT_IF_DDR_2;
 666                                 break;
 667                         case 2:
 668                                 law_memctl = LAW_TRGT_IF_DDR_3;
 669                                 break;
 670                         case 3:
 671                                 law_memctl = LAW_TRGT_IF_DDR_4;
 672                                 break;
 673                         default:
 674                                 break;
 675                         }
 676                         fsl_ddr_set_lawbar(&info.common_timing_params[i],
 677                                         law_memctl, i);
 678                 }
 679         }
 680
 681         debug("total_memory by %s = %llu\n", __func__, total_memory);
 682
 683 #if !defined(CONFIG_PHYS_64BIT)
 684         /* Check for 4G or more.  Bad. */
 685         if (total_memory >= (1ull << 32)) {
 686                 puts("Detected ");
 687                 print_size(total_memory, " of memory\n");
 688                 printf("       This U-Boot only supports < 4G of DDR\n");
 689                 printf("       You could rebuild it with CONFIG_PHYS_64BIT\n");
 690                 printf("       "); /* re-align to match init_func_ram print */
 691                 total_memory = CONFIG_MAX_MEM_MAPPED;
 692         }
 693 #endif
 694
 695         return total_memory;
 696 }
 697
 698 /*
 699  * fsl_ddr_sdram_size() - This function only returns the size of the total
 700  * memory without setting ddr control registers.
 701  */
 702 phys_size_t
 703 fsl_ddr_sdram_size(void)
 704 {
 705         fsl_ddr_info_t  info;
 706         unsigned long long total_memory = 0;
 707
 708         memset(&info, 0 , sizeof(fsl_ddr_info_t));
 709
 710         /* Compute it once normally. */
 711         total_memory = fsl_ddr_compute(&info, STEP_GET_SPD, 1);
 712
 713         return total_memory;
 714 }