arch/powerpc/cpu/mpc8xxx/ddr/util.c

   1 /*
   2  * Copyright 2008 Freescale Semiconductor, Inc.
   3  *
   4  * This program is free software; you can redistribute it and/or
   5  * modify it under the terms of the GNU General Public License
   6  * Version 2 as published by the Free Software Foundation.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/fsl_law.h>
  11
  12 #include "ddr.h"
  13
  14 unsigned int fsl_ddr_get_mem_data_rate(void);
  15
  16 /*
  17  * Round mclk_ps to nearest 10 ps in memory controller code.
  18  *
  19  * If an imprecise data rate is too high due to rounding error
  20  * propagation, compute a suitably rounded mclk_ps to compute
  21  * a working memory controller configuration.
  22  */
  23 unsigned int get_memory_clk_period_ps(void)
  24 {
  25         unsigned int mclk_ps;
  26
  27         mclk_ps = 2000000000000ULL / fsl_ddr_get_mem_data_rate();
  28         /* round to nearest 10 ps */
  29         return 10 * ((mclk_ps + 5) / 10);
  30 }
  31
  32 /* Convert picoseconds into DRAM clock cycles (rounding up if needed). */
  33 unsigned int picos_to_mclk(unsigned int picos)
  34 {
  35         const unsigned long long ULL_2e12 = 2000000000000ULL;
  36         const unsigned long long ULL_8Fs = 0xFFFFFFFFULL;
  37         unsigned long long clks;
  38         unsigned long long clks_temp;
  39
  40         if (!picos)
  41                 return 0;
  42
  43         clks = fsl_ddr_get_mem_data_rate() * (unsigned long long) picos;
  44         clks_temp = clks;
  45         clks = clks / ULL_2e12;
  46         if (clks_temp % ULL_2e12) {
  47                 clks++;
  48         }
  49
  50         if (clks > ULL_8Fs) {
  51                 clks = ULL_8Fs;
  52         }
  53
  54         return (unsigned int) clks;
  55 }
  56
  57 unsigned int mclk_to_picos(unsigned int mclk)
  58 {
  59         return get_memory_clk_period_ps() * mclk;
  60 }
  61
  62 void
  63 __fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
  64                            unsigned int memctl_interleaved,
  65                            unsigned int ctrl_num)
  66 {
  67         unsigned long long base = memctl_common_params->base_address;
  68         unsigned long long size = memctl_common_params->total_mem;
  69
  70         /*
  71          * If no DIMMs on this controller, do not proceed any further.
  72          */
  73         if (!memctl_common_params->ndimms_present) {
  74                 return;
  75         }
  76
  77 #if !defined(CONFIG_PHYS_64BIT)
  78         if (base >= CONFIG_MAX_MEM_MAPPED)
  79                 return;
  80         if ((base + size) >= CONFIG_MAX_MEM_MAPPED)
  81                 size = CONFIG_MAX_MEM_MAPPED - base;
  82 #endif
  83
  84         if (ctrl_num == 0) {
  85                 /*
  86                  * Set up LAW for DDR controller 1 space.
  87                  */
  88                 unsigned int lawbar1_target_id = memctl_interleaved
  89                         ? LAW_TRGT_IF_DDR_INTRLV : LAW_TRGT_IF_DDR_1;
  90
  91                 if (set_ddr_laws(base, size, lawbar1_target_id) < 0) {
  92                         printf("%s: ERROR (ctrl #0, intrlv=%d)\n", __func__,
  93                                 memctl_interleaved);
  94                         return ;
  95                 }
  96         } else if (ctrl_num == 1) {
  97                 if (set_ddr_laws(base, size, LAW_TRGT_IF_DDR_2) < 0) {
  98                         printf("%s: ERROR (ctrl #1)\n", __func__);
  99                         return ;
 100                 }
 101         } else {
 102                 printf("%s: unexpected DDR controller number (%u)\n", __func__,
 103                         ctrl_num);
 104         }
 105 }
 106
 107 __attribute__((weak, alias("__fsl_ddr_set_lawbar"))) void
 108 fsl_ddr_set_lawbar(const common_timing_params_t *memctl_common_params,
 109                          unsigned int memctl_interleaved,
 110                          unsigned int ctrl_num);
 111
 112 void board_add_ram_info(int use_default)
 113 {
 114 #if defined(CONFIG_MPC85xx)
 115         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
 116 #elif defined(CONFIG_MPC86xx)
 117         volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC86xx_DDR_ADDR);
 118 #endif
 119 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 120         uint32_t cs0_config = in_be32(&ddr->cs0_config);
 121 #endif
 122         uint32_t sdram_cfg = in_be32(&ddr->sdram_cfg);
 123         int cas_lat;
 124
 125         puts(" (DDR");
 126         switch ((sdram_cfg & SDRAM_CFG_SDRAM_TYPE_MASK) >>
 127                 SDRAM_CFG_SDRAM_TYPE_SHIFT) {
 128         case SDRAM_TYPE_DDR1:
 129                 puts("1");
 130                 break;
 131         case SDRAM_TYPE_DDR2:
 132                 puts("2");
 133                 break;
 134         case SDRAM_TYPE_DDR3:
 135                 puts("3");
 136                 break;
 137         default:
 138                 puts("?");
 139                 break;
 140         }
 141
 142         if (sdram_cfg & SDRAM_CFG_32_BE)
 143                 puts(", 32-bit");
 144         else
 145                 puts(", 64-bit");
 146
 147         /* Calculate CAS latency based on timing cfg values */
 148         cas_lat = ((in_be32(&ddr->timing_cfg_1) >> 16) & 0xf) + 1;
 149         if ((in_be32(&ddr->timing_cfg_3) >> 12) & 1)
 150                 cas_lat += (8 << 1);
 151         printf(", CL=%d", cas_lat >> 1);
 152         if (cas_lat & 0x1)
 153                 puts(".5");
 154
 155         if (sdram_cfg & SDRAM_CFG_ECC_EN)
 156                 puts(", ECC on)");
 157         else
 158                 puts(", ECC off)");
 159
 160 #if (CONFIG_NUM_DDR_CONTROLLERS > 1)
 161         if (cs0_config & 0x20000000) {
 162                 puts("\n");
 163                 puts("       DDR Controller Interleaving Mode: ");
 164
 165                 switch ((cs0_config >> 24) & 0xf) {
 166                 case FSL_DDR_CACHE_LINE_INTERLEAVING:
 167                         puts("cache line");
 168                         break;
 169                 case FSL_DDR_PAGE_INTERLEAVING:
 170                         puts("page");
 171                         break;
 172                 case FSL_DDR_BANK_INTERLEAVING:
 173                         puts("bank");
 174                         break;
 175                 case FSL_DDR_SUPERBANK_INTERLEAVING:
 176                         puts("super-bank");
 177                         break;
 178                 default:
 179                         puts("invalid");
 180                         break;
 181                 }
 182         }
 183 #endif
 184
 185         if ((sdram_cfg >> 8) & 0x7f) {
 186                 puts("\n");
 187                 puts("       DDR Chip-Select Interleaving Mode: ");
 188                 switch(sdram_cfg >> 8 & 0x7f) {
 189                 case FSL_DDR_CS0_CS1_CS2_CS3:
 190                         puts("CS0+CS1+CS2+CS3");
 191                         break;
 192                 case FSL_DDR_CS0_CS1:
 193                         puts("CS0+CS1");
 194                         break;
 195                 case FSL_DDR_CS2_CS3:
 196                         puts("CS2+CS3");
 197                         break;
 198                 case FSL_DDR_CS0_CS1_AND_CS2_CS3:
 199                         puts("CS0+CS1 and CS2+CS3");
 200                         break;
 201                 default:
 202                         puts("invalid");
 203                         break;
 204                 }
 205         }
 206 }