arch/powerpc/cpu/mpc8xxx/law.c

   1 /*
   2  * Copyright 2008-2011 Freescale Semiconductor, Inc.
   3  *
   4  * (C) Copyright 2000
   5  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0+
   8  */
   9
  10 #include <common.h>
  11 #include <linux/compiler.h>
  12 #include <asm/fsl_law.h>
  13 #include <asm/io.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
  18
  19 #ifdef CONFIG_FSL_CORENET
  20 #define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR)
  21 #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar)
  22 #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh)
  23 #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl)
  24 #define LAWBAR_SHIFT 0
  25 #else
  26 #define LAW_BASE (CONFIG_SYS_IMMR + 0xc08)
  27 #define LAWAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x + 2)
  28 #define LAWBAR_ADDR(x) ((u32 *)LAW_BASE + 8 * x)
  29 #define LAWBAR_SHIFT 12
  30 #endif
  31
  32
  33 static inline phys_addr_t get_law_base_addr(int idx)
  34 {
  35 #ifdef CONFIG_FSL_CORENET
  36         return (phys_addr_t)
  37                 ((u64)in_be32(LAWBARH_ADDR(idx)) << 32) |
  38                 in_be32(LAWBARL_ADDR(idx));
  39 #else
  40         return (phys_addr_t)in_be32(LAWBAR_ADDR(idx)) << LAWBAR_SHIFT;
  41 #endif
  42 }
  43
  44 static inline void set_law_base_addr(int idx, phys_addr_t addr)
  45 {
  46 #ifdef CONFIG_FSL_CORENET
  47         out_be32(LAWBARL_ADDR(idx), addr & 0xffffffff);
  48         out_be32(LAWBARH_ADDR(idx), (u64)addr >> 32);
  49 #else
  50         out_be32(LAWBAR_ADDR(idx), addr >> LAWBAR_SHIFT);
  51 #endif
  52 }
  53
  54 void set_law(u8 idx, phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
  55 {
  56         gd->arch.used_laws |= (1 << idx);
  57
  58         out_be32(LAWAR_ADDR(idx), 0);
  59         set_law_base_addr(idx, addr);
  60         out_be32(LAWAR_ADDR(idx), LAW_EN | ((u32)id << 20) | (u32)sz);
  61
  62         /* Read back so that we sync the writes */
  63         in_be32(LAWAR_ADDR(idx));
  64 }
  65
  66 void disable_law(u8 idx)
  67 {
  68         gd->arch.used_laws &= ~(1 << idx);
  69
  70         out_be32(LAWAR_ADDR(idx), 0);
  71         set_law_base_addr(idx, 0);
  72
  73         /* Read back so that we sync the writes */
  74         in_be32(LAWAR_ADDR(idx));
  75
  76         return;
  77 }
  78
  79 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
  80 static int get_law_entry(u8 i, struct law_entry *e)
  81 {
  82         u32 lawar;
  83
  84         lawar = in_be32(LAWAR_ADDR(i));
  85
  86         if (!(lawar & LAW_EN))
  87                 return 0;
  88
  89         e->addr = get_law_base_addr(i);
  90         e->size = lawar & 0x3f;
  91         e->trgt_id = (lawar >> 20) & 0xff;
  92
  93         return 1;
  94 }
  95 #endif
  96
  97 int set_next_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
  98 {
  99         u32 idx = ffz(gd->arch.used_laws);
 100
 101         if (idx >= FSL_HW_NUM_LAWS)
 102                 return -1;
 103
 104         set_law(idx, addr, sz, id);
 105
 106         return idx;
 107 }
 108
 109 #if !defined(CONFIG_NAND_SPL) && !defined(CONFIG_SPL_BUILD)
 110 int set_last_law(phys_addr_t addr, enum law_size sz, enum law_trgt_if id)
 111 {
 112         u32 idx;
 113
 114         /* we have no LAWs free */
 115         if (gd->arch.used_laws == -1)
 116                 return -1;
 117
 118         /* grab the last free law */
 119         idx = __ilog2(~(gd->arch.used_laws));
 120
 121         if (idx >= FSL_HW_NUM_LAWS)
 122                 return -1;
 123
 124         set_law(idx, addr, sz, id);
 125
 126         return idx;
 127 }
 128
 129 struct law_entry find_law(phys_addr_t addr)
 130 {
 131         struct law_entry entry;
 132         int i;
 133
 134         entry.index = -1;
 135         entry.addr = 0;
 136         entry.size = 0;
 137         entry.trgt_id = 0;
 138
 139         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 140                 u64 upper;
 141
 142                 if (!get_law_entry(i, &entry))
 143                         continue;
 144
 145                 upper = entry.addr + (2ull << entry.size);
 146                 if ((addr >= entry.addr) && (addr < upper)) {
 147                         entry.index = i;
 148                         break;
 149                 }
 150         }
 151
 152         return entry;
 153 }
 154
 155 void print_laws(void)
 156 {
 157         int i;
 158         u32 lawar;
 159
 160         printf("\nLocal Access Window Configuration\n");
 161         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 162                 lawar = in_be32(LAWAR_ADDR(i));
 163 #ifdef CONFIG_FSL_CORENET
 164                 printf("LAWBARH%02d: 0x%08x LAWBARL%02d: 0x%08x",
 165                        i, in_be32(LAWBARH_ADDR(i)),
 166                        i, in_be32(LAWBARL_ADDR(i)));
 167 #else
 168                 printf("LAWBAR%02d: 0x%08x", i, in_be32(LAWBAR_ADDR(i)));
 169 #endif
 170                 printf(" LAWAR%02d: 0x%08x\n", i, lawar);
 171                 printf("\t(EN: %d TGT: 0x%02x SIZE: ",
 172                        (lawar & LAW_EN) ? 1 : 0, (lawar >> 20) & 0xff);
 173                 print_size(lawar_size(lawar), ")\n");
 174         }
 175
 176         return;
 177 }
 178
 179 /* use up to 2 LAWs for DDR, used the last available LAWs */
 180 int set_ddr_laws(u64 start, u64 sz, enum law_trgt_if id)
 181 {
 182         u64 start_align, law_sz;
 183         int law_sz_enc;
 184
 185         if (start == 0)
 186                 start_align = 1ull << (LAW_SIZE_32G + 1);
 187         else
 188                 start_align = 1ull << (ffs64(start) - 1);
 189         law_sz = min(start_align, sz);
 190         law_sz_enc = __ilog2_u64(law_sz) - 1;
 191
 192         if (set_last_law(start, law_sz_enc, id) < 0)
 193                 return -1;
 194
 195         /* recalculate size based on what was actually covered by the law */
 196         law_sz = 1ull << __ilog2_u64(law_sz);
 197
 198         /* do we still have anything to map */
 199         sz = sz - law_sz;
 200         if (sz) {
 201                 start += law_sz;
 202
 203                 start_align = 1ull << (ffs64(start) - 1);
 204                 law_sz = min(start_align, sz);
 205                 law_sz_enc = __ilog2_u64(law_sz) - 1;
 206
 207                 if (set_last_law(start, law_sz_enc, id) < 0)
 208                         return -1;
 209         } else {
 210                 return 0;
 211         }
 212
 213         /* do we still have anything to map */
 214         sz = sz - law_sz;
 215         if (sz)
 216                 return 1;
 217
 218         return 0;
 219 }
 220 #endif /* not SPL */
 221
 222 void init_laws(void)
 223 {
 224         int i;
 225
 226 #if FSL_HW_NUM_LAWS < 32
 227         gd->arch.used_laws = ~((1 << FSL_HW_NUM_LAWS) - 1);
 228 #elif FSL_HW_NUM_LAWS == 32
 229         gd->arch.used_laws = 0;
 230 #else
 231 #error FSL_HW_NUM_LAWS can not be greater than 32 w/o code changes
 232 #endif
 233
 234         /*
 235          * Any LAWs that were set up before we booted assume they are meant to
 236          * be around and mark them used.
 237          */
 238         for (i = 0; i < FSL_HW_NUM_LAWS; i++) {
 239                 u32 lawar = in_be32(LAWAR_ADDR(i));
 240
 241                 if (lawar & LAW_EN)
 242                         gd->arch.used_laws |= (1 << i);
 243         }
 244
 245 #if (defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)) || \
 246         (defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD))
 247         /*
 248          * in SPL boot we've already parsed the law_table and setup those LAWs
 249          * so don't do it again.
 250          */
 251         return;
 252 #endif
 253
 254         for (i = 0; i < num_law_entries; i++) {
 255                 if (law_table[i].index == -1)
 256                         set_next_law(law_table[i].addr, law_table[i].size,
 257                                         law_table[i].trgt_id);
 258                 else
 259                         set_law(law_table[i].index, law_table[i].addr,
 260                                 law_table[i].size, law_table[i].trgt_id);
 261         }
 262
 263 #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE
 264         /* check RCW to get which port is used for boot */
 265         ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
 266         u32 bootloc = in_be32(&gur->rcwsr[6]);
 267         /*
 268          * in SRIO or PCIE boot we need to set specail LAWs for
 269          * SRIO or PCIE interfaces.
 270          */
 271         switch ((bootloc & FSL_CORENET_RCWSR6_BOOT_LOC) >> 23) {
 272         case 0x0: /* boot from PCIE1 */
 273                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 274                                 LAW_SIZE_1M,
 275                                 LAW_TRGT_IF_PCIE_1);
 276                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 277                                 LAW_SIZE_1M,
 278                                 LAW_TRGT_IF_PCIE_1);
 279                 break;
 280         case 0x1: /* boot from PCIE2 */
 281                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 282                                 LAW_SIZE_1M,
 283                                 LAW_TRGT_IF_PCIE_2);
 284                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 285                                 LAW_SIZE_1M,
 286                                 LAW_TRGT_IF_PCIE_2);
 287                 break;
 288         case 0x2: /* boot from PCIE3 */
 289                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 290                                 LAW_SIZE_1M,
 291                                 LAW_TRGT_IF_PCIE_3);
 292                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 293                                 LAW_SIZE_1M,
 294                                 LAW_TRGT_IF_PCIE_3);
 295                 break;
 296         case 0x8: /* boot from SRIO1 */
 297                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 298                                 LAW_SIZE_1M,
 299                                 LAW_TRGT_IF_RIO_1);
 300                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 301                                 LAW_SIZE_1M,
 302                                 LAW_TRGT_IF_RIO_1);
 303                 break;
 304         case 0x9: /* boot from SRIO2 */
 305                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS,
 306                                 LAW_SIZE_1M,
 307                                 LAW_TRGT_IF_RIO_2);
 308                 set_next_law(CONFIG_SYS_SRIO_PCIE_BOOT_UCODE_ENV_ADDR_PHYS,
 309                                 LAW_SIZE_1M,
 310                                 LAW_TRGT_IF_RIO_2);
 311                 break;
 312         default:
 313                 break;
 314         }
 315 #endif
 316
 317         return ;
 318 }