arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c

   1 /*
   2  * arch/powerpc/cpu/ppc4xx/44x_spd_ddr2.c
   3  * This SPD SDRAM detection code supports AMCC PPC44x cpu's with a
   4  * DDR2 controller (non Denali Core). Those currently are:
   5  *
   6  * 405:         405EX(r)
   7  * 440/460:     440SP/440SPe/460EX/460GT
   8  *
   9  * Copyright (c) 2008 Nuovation System Designs, LLC
  10  *   Grant Erickson <gerickson@nuovations.com>
  11
  12  * (C) Copyright 2007-2009
  13  * Stefan Roese, DENX Software Engineering, sr@denx.de.
  14  *
  15  * COPYRIGHT   AMCC   CORPORATION 2004
  16  *
  17  * See file CREDITS for list of people who contributed to this
  18  * project.
  19  *
  20  * This program is free software; you can redistribute it and/or
  21  * modify it under the terms of the GNU General Public License as
  22  * published by the Free Software Foundation; either version 2 of
  23  * the License, or (at your option) any later version.
  24  *
  25  * This program is distributed in the hope that it will be useful,
  26  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  27  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  28  * GNU General Public License for more details.
  29  *
  30  * You should have received a copy of the GNU General Public License
  31  * along with this program; if not, write to the Free Software
  32  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  33  * MA 02111-1307 USA
  34  *
  35  */
  36
  37 /* define DEBUG for debugging output (obviously ;-)) */
  38 #if 0
  39 #define DEBUG
  40 #endif
  41
  42 #include <common.h>
  43 #include <command.h>
  44 #include <asm/ppc4xx.h>
  45 #include <i2c.h>
  46 #include <asm/io.h>
  47 #include <asm/processor.h>
  48 #include <asm/mmu.h>
  49 #include <asm/cache.h>
  50
  51 #include "ecc.h"
  52
  53 #define PPC4xx_IBM_DDR2_DUMP_REGISTER(mnemonic)                         \
  54         do {                                                            \
  55                 u32 data;                                               \
  56                 mfsdram(SDRAM_##mnemonic, data);                        \
  57                 printf("%20s[%02x] = 0x%08X\n",                         \
  58                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  59         } while (0)
  60
  61 #define PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(mnemonic)                      \
  62         do {                                                            \
  63                 u32 data;                                               \
  64                 data = mfdcr(SDRAM_##mnemonic);                         \
  65                 printf("%20s[%02x] = 0x%08X\n",                         \
  66                        "SDRAM_" #mnemonic, SDRAM_##mnemonic, data);     \
  67         } while (0)
  68
  69 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
  70 static void update_rdcc(void)
  71 {
  72         u32 val;
  73
  74         /*
  75          * Complete RDSS configuration as mentioned on page 7 of the AMCC
  76          * PowerPC440SP/SPe DDR2 application note:
  77          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
  78          *
  79          * Or item #10 "10. Complete RDSS configuration" in chapter
  80          * "22.2.9 SDRAM Initialization" of AMCC PPC460EX/EXr/GT users
  81          * manual.
  82          */
  83         mfsdram(SDRAM_RTSR, val);
  84         if ((val & SDRAM_RTSR_TRK1SM_MASK) == SDRAM_RTSR_TRK1SM_ATPLS1) {
  85                 mfsdram(SDRAM_RDCC, val);
  86                 if ((val & SDRAM_RDCC_RDSS_MASK) != SDRAM_RDCC_RDSS_T4) {
  87                         val += 0x40000000;
  88                         mtsdram(SDRAM_RDCC, val);
  89                 }
  90         }
  91 }
  92 #endif
  93
  94 #if defined(CONFIG_440)
  95 /*
  96  * This DDR2 setup code can dynamically setup the TLB entries for the DDR2
  97  * memory region. Right now the cache should still be disabled in U-Boot
  98  * because of the EMAC driver, that need its buffer descriptor to be located
  99  * in non cached memory.
 100  *
 101  * If at some time this restriction doesn't apply anymore, just define
 102  * CONFIG_4xx_DCACHE in the board config file and this code should setup
 103  * everything correctly.
 104  */
 105 #ifdef CONFIG_4xx_DCACHE
 106 /* enable caching on SDRAM */
 107 #define MY_TLB_WORD2_I_ENABLE           0
 108 #else
 109 /* disable caching on SDRAM */
 110 #define MY_TLB_WORD2_I_ENABLE           TLB_WORD2_I_ENABLE
 111 #endif /* CONFIG_4xx_DCACHE */
 112
 113 void dcbz_area(u32 start_address, u32 num_bytes);
 114 #endif /* CONFIG_440 */
 115
 116 #define MAXRANKS        4
 117 #define MAXBXCF         4
 118
 119 #define MULDIV64(m1, m2, d)     (u32)(((u64)(m1) * (u64)(m2)) / (u64)(d))
 120
 121 #if !defined(CONFIG_NAND_SPL)
 122 /*-----------------------------------------------------------------------------+
 123  * sdram_memsize
 124  *-----------------------------------------------------------------------------*/
 125 phys_size_t sdram_memsize(void)
 126 {
 127         phys_size_t mem_size;
 128         unsigned long mcopt2;
 129         unsigned long mcstat;
 130         unsigned long mb0cf;
 131         unsigned long sdsz;
 132         unsigned long i;
 133
 134         mem_size = 0;
 135
 136         mfsdram(SDRAM_MCOPT2, mcopt2);
 137         mfsdram(SDRAM_MCSTAT, mcstat);
 138
 139         /* DDR controller must be enabled and not in self-refresh. */
 140         /* Otherwise memsize is zero. */
 141         if (((mcopt2 & SDRAM_MCOPT2_DCEN_MASK) == SDRAM_MCOPT2_DCEN_ENABLE)
 142             && ((mcopt2 & SDRAM_MCOPT2_SREN_MASK) == SDRAM_MCOPT2_SREN_EXIT)
 143             && ((mcstat & (SDRAM_MCSTAT_MIC_MASK | SDRAM_MCSTAT_SRMS_MASK))
 144                 == (SDRAM_MCSTAT_MIC_COMP | SDRAM_MCSTAT_SRMS_NOT_SF))) {
 145                 for (i = 0; i < MAXBXCF; i++) {
 146                         mfsdram(SDRAM_MB0CF + (i << 2), mb0cf);
 147                         /* Banks enabled */
 148                         if ((mb0cf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
 149 #if defined(CONFIG_440)
 150                                 sdsz = mfdcr_any(SDRAM_R0BAS + i) & SDRAM_RXBAS_SDSZ_MASK;
 151 #else
 152                                 sdsz = mb0cf & SDRAM_RXBAS_SDSZ_MASK;
 153 #endif
 154                                 switch(sdsz) {
 155                                 case SDRAM_RXBAS_SDSZ_8:
 156                                         mem_size+=8;
 157                                         break;
 158                                 case SDRAM_RXBAS_SDSZ_16:
 159                                         mem_size+=16;
 160                                         break;
 161                                 case SDRAM_RXBAS_SDSZ_32:
 162                                         mem_size+=32;
 163                                         break;
 164                                 case SDRAM_RXBAS_SDSZ_64:
 165                                         mem_size+=64;
 166                                         break;
 167                                 case SDRAM_RXBAS_SDSZ_128:
 168                                         mem_size+=128;
 169                                         break;
 170                                 case SDRAM_RXBAS_SDSZ_256:
 171                                         mem_size+=256;
 172                                         break;
 173                                 case SDRAM_RXBAS_SDSZ_512:
 174                                         mem_size+=512;
 175                                         break;
 176                                 case SDRAM_RXBAS_SDSZ_1024:
 177                                         mem_size+=1024;
 178                                         break;
 179                                 case SDRAM_RXBAS_SDSZ_2048:
 180                                         mem_size+=2048;
 181                                         break;
 182                                 case SDRAM_RXBAS_SDSZ_4096:
 183                                         mem_size+=4096;
 184                                         break;
 185                                 default:
 186                                         printf("WARNING: Unsupported bank size (SDSZ=0x%lx)!\n"
 187                                                , sdsz);
 188                                         mem_size=0;
 189                                         break;
 190                                 }
 191                         }
 192                 }
 193         }
 194
 195         return mem_size << 20;
 196 }
 197
 198 /*-----------------------------------------------------------------------------+
 199  * is_ecc_enabled
 200  *-----------------------------------------------------------------------------*/
 201 static unsigned long is_ecc_enabled(void)
 202 {
 203         unsigned long val;
 204
 205         mfsdram(SDRAM_MCOPT1, val);
 206
 207         return SDRAM_MCOPT1_MCHK_CHK_DECODE(val);
 208 }
 209
 210 /*-----------------------------------------------------------------------------+
 211  * board_add_ram_info
 212  *-----------------------------------------------------------------------------*/
 213 void board_add_ram_info(int use_default)
 214 {
 215         PPC4xx_SYS_INFO board_cfg;
 216         u32 val;
 217
 218         if (is_ecc_enabled())
 219                 puts(" (ECC");
 220         else
 221                 puts(" (ECC not");
 222
 223         get_sys_info(&board_cfg);
 224
 225 #if defined(CONFIG_405EX)
 226         val = board_cfg.freqPLB;
 227 #else
 228         mfsdr(SDR0_DDR0, val);
 229         val = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(val), 1);
 230 #endif
 231         printf(" enabled, %d MHz", (val * 2) / 1000000);
 232
 233         mfsdram(SDRAM_MMODE, val);
 234         val = (val & SDRAM_MMODE_DCL_MASK) >> 4;
 235         printf(", CL%d)", val);
 236 }
 237 #endif /* !CONFIG_NAND_SPL */
 238
 239 #if defined(CONFIG_SPD_EEPROM)
 240
 241 /*-----------------------------------------------------------------------------+
 242  * Defines
 243  *-----------------------------------------------------------------------------*/
 244 #define SDRAM_DDR1      1
 245 #define SDRAM_DDR2      2
 246 #define SDRAM_NONE      0
 247
 248 #define MAXDIMMS        2
 249 #define MAX_SPD_BYTES   256   /* Max number of bytes on the DIMM's SPD EEPROM */
 250
 251 #define ONE_BILLION     1000000000
 252
 253 #define CMD_NOP         (7 << 19)
 254 #define CMD_PRECHARGE   (2 << 19)
 255 #define CMD_REFRESH     (1 << 19)
 256 #define CMD_EMR         (0 << 19)
 257 #define CMD_READ        (5 << 19)
 258 #define CMD_WRITE       (4 << 19)
 259
 260 #define SELECT_MR       (0 << 16)
 261 #define SELECT_EMR      (1 << 16)
 262 #define SELECT_EMR2     (2 << 16)
 263 #define SELECT_EMR3     (3 << 16)
 264
 265 /* MR */
 266 #define DLL_RESET       0x00000100
 267
 268 #define WRITE_RECOV_2   (1 << 9)
 269 #define WRITE_RECOV_3   (2 << 9)
 270 #define WRITE_RECOV_4   (3 << 9)
 271 #define WRITE_RECOV_5   (4 << 9)
 272 #define WRITE_RECOV_6   (5 << 9)
 273
 274 #define BURST_LEN_4     0x00000002
 275
 276 /* EMR */
 277 #define ODT_0_OHM       0x00000000
 278 #define ODT_50_OHM      0x00000044
 279 #define ODT_75_OHM      0x00000004
 280 #define ODT_150_OHM     0x00000040
 281
 282 #define ODS_FULL        0x00000000
 283 #define ODS_REDUCED     0x00000002
 284 #define OCD_CALIB_DEF   0x00000380
 285
 286 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */
 287 #define ODT_EB0R        (0x80000000 >> 8)
 288 #define ODT_EB0W        (0x80000000 >> 7)
 289 #define CALC_ODT_R(n)   (ODT_EB0R << (n << 1))
 290 #define CALC_ODT_W(n)   (ODT_EB0W << (n << 1))
 291 #define CALC_ODT_RW(n)  (CALC_ODT_R(n) | CALC_ODT_W(n))
 292
 293 /* Defines for the Read Cycle Delay test */
 294 #define NUMMEMTESTS     8
 295 #define NUMMEMWORDS     8
 296 #define NUMLOOPS        64              /* memory test loops */
 297
 298 /*
 299  * Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM.
 300  * To support such configurations, we "only" map the first 2GB via the TLB's. We
 301  * need some free virtual address space for the remaining peripherals like, SoC
 302  * devices, FLASH etc.
 303  *
 304  * Note that ECC is currently not supported on configurations with more than 2GB
 305  * SDRAM. This is because we only map the first 2GB on such systems, and therefore
 306  * the ECC parity byte of the remaining area can't be written.
 307  */
 308
 309 /*
 310  * Board-specific Platform code can reimplement spd_ddr_init_hang () if needed
 311  */
 312 void __spd_ddr_init_hang (void)
 313 {
 314         hang ();
 315 }
 316 void spd_ddr_init_hang (void) __attribute__((weak, alias("__spd_ddr_init_hang")));
 317
 318 /*
 319  * To provide an interface for board specific config values in this common
 320  * DDR setup code, we implement he "weak" default functions here. They return
 321  * the default value back to the caller.
 322  *
 323  * Please see include/configs/yucca.h for an example fora board specific
 324  * implementation.
 325  */
 326 u32 __ddr_wrdtr(u32 default_val)
 327 {
 328         return default_val;
 329 }
 330 u32 ddr_wrdtr(u32) __attribute__((weak, alias("__ddr_wrdtr")));
 331
 332 u32 __ddr_clktr(u32 default_val)
 333 {
 334         return default_val;
 335 }
 336 u32 ddr_clktr(u32) __attribute__((weak, alias("__ddr_clktr")));
 337
 338
 339 /* Private Structure Definitions */
 340
 341 /* enum only to ease code for cas latency setting */
 342 typedef enum ddr_cas_id {
 343         DDR_CAS_2      = 20,
 344         DDR_CAS_2_5    = 25,
 345         DDR_CAS_3      = 30,
 346         DDR_CAS_4      = 40,
 347         DDR_CAS_5      = 50
 348 } ddr_cas_id_t;
 349
 350 /*-----------------------------------------------------------------------------+
 351  * Prototypes
 352  *-----------------------------------------------------------------------------*/
 353 static void get_spd_info(unsigned long *dimm_populated,
 354                          unsigned char *iic0_dimm_addr,
 355                          unsigned long num_dimm_banks);
 356 static void check_mem_type(unsigned long *dimm_populated,
 357                            unsigned char *iic0_dimm_addr,
 358                            unsigned long num_dimm_banks);
 359 static void check_frequency(unsigned long *dimm_populated,
 360                             unsigned char *iic0_dimm_addr,
 361                             unsigned long num_dimm_banks);
 362 static void check_rank_number(unsigned long *dimm_populated,
 363                               unsigned char *iic0_dimm_addr,
 364                               unsigned long num_dimm_banks);
 365 static void check_voltage_type(unsigned long *dimm_populated,
 366                                unsigned char *iic0_dimm_addr,
 367                                unsigned long num_dimm_banks);
 368 static void program_memory_queue(unsigned long *dimm_populated,
 369                                  unsigned char *iic0_dimm_addr,
 370                                  unsigned long num_dimm_banks);
 371 static void program_codt(unsigned long *dimm_populated,
 372                          unsigned char *iic0_dimm_addr,
 373                          unsigned long num_dimm_banks);
 374 static void program_mode(unsigned long *dimm_populated,
 375                          unsigned char *iic0_dimm_addr,
 376                          unsigned long num_dimm_banks,
 377                          ddr_cas_id_t *selected_cas,
 378                          int *write_recovery);
 379 static void program_tr(unsigned long *dimm_populated,
 380                        unsigned char *iic0_dimm_addr,
 381                        unsigned long num_dimm_banks);
 382 static void program_rtr(unsigned long *dimm_populated,
 383                         unsigned char *iic0_dimm_addr,
 384                         unsigned long num_dimm_banks);
 385 static void program_bxcf(unsigned long *dimm_populated,
 386                          unsigned char *iic0_dimm_addr,
 387                          unsigned long num_dimm_banks);
 388 static void program_copt1(unsigned long *dimm_populated,
 389                           unsigned char *iic0_dimm_addr,
 390                           unsigned long num_dimm_banks);
 391 static void program_initplr(unsigned long *dimm_populated,
 392                             unsigned char *iic0_dimm_addr,
 393                             unsigned long num_dimm_banks,
 394                             ddr_cas_id_t selected_cas,
 395                             int write_recovery);
 396 #ifdef CONFIG_DDR_ECC
 397 static void program_ecc(unsigned long *dimm_populated,
 398                         unsigned char *iic0_dimm_addr,
 399                         unsigned long num_dimm_banks,
 400                         unsigned long tlb_word2_i_value);
 401 #endif
 402 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 403 static void program_DQS_calibration(unsigned long *dimm_populated,
 404                                 unsigned char *iic0_dimm_addr,
 405                                 unsigned long num_dimm_banks);
 406 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
 407 static void     test(void);
 408 #else
 409 static void     DQS_calibration_process(void);
 410 #endif
 411 #endif
 412
 413 static unsigned char spd_read(uchar chip, uint addr)
 414 {
 415         unsigned char data[2];
 416
 417         if (i2c_probe(chip) == 0)
 418                 if (i2c_read(chip, addr, 1, data, 1) == 0)
 419                         return data[0];
 420
 421         return 0;
 422 }
 423
 424 /*-----------------------------------------------------------------------------+
 425  * initdram.  Initializes the 440SP Memory Queue and DDR SDRAM controller.
 426  * Note: This routine runs from flash with a stack set up in the chip's
 427  * sram space.  It is important that the routine does not require .sbss, .bss or
 428  * .data sections.  It also cannot call routines that require these sections.
 429  *-----------------------------------------------------------------------------*/
 430 /*-----------------------------------------------------------------------------
 431  * Function:     initdram
 432  * Description:  Configures SDRAM memory banks for DDR operation.
 433  *               Auto Memory Configuration option reads the DDR SDRAM EEPROMs
 434  *               via the IIC bus and then configures the DDR SDRAM memory
 435  *               banks appropriately. If Auto Memory Configuration is
 436  *               not used, it is assumed that no DIMM is plugged
 437  *-----------------------------------------------------------------------------*/
 438 phys_size_t initdram(int board_type)
 439 {
 440         unsigned char iic0_dimm_addr[] = SPD_EEPROM_ADDRESS;
 441         unsigned long dimm_populated[MAXDIMMS] = {SDRAM_NONE, SDRAM_NONE};
 442         unsigned long num_dimm_banks;           /* on board dimm banks */
 443         unsigned long val;
 444         ddr_cas_id_t selected_cas = DDR_CAS_5;  /* preset to silence compiler */
 445         int write_recovery;
 446         phys_size_t dram_size = 0;
 447
 448         num_dimm_banks = sizeof(iic0_dimm_addr);
 449
 450         /*------------------------------------------------------------------
 451          * Reset the DDR-SDRAM controller.
 452          *-----------------------------------------------------------------*/
 453         mtsdr(SDR0_SRST, SDR0_SRST0_DMC);
 454         mtsdr(SDR0_SRST, 0x00000000);
 455
 456         /*
 457          * Make sure I2C controller is initialized
 458          * before continuing.
 459          */
 460
 461         /* switch to correct I2C bus */
 462         I2C_SET_BUS(CONFIG_SYS_SPD_BUS_NUM);
 463         i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
 464
 465         /*------------------------------------------------------------------
 466          * Clear out the serial presence detect buffers.
 467          * Perform IIC reads from the dimm.  Fill in the spds.
 468          * Check to see if the dimm slots are populated
 469          *-----------------------------------------------------------------*/
 470         get_spd_info(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 471
 472         /*------------------------------------------------------------------
 473          * Check the memory type for the dimms plugged.
 474          *-----------------------------------------------------------------*/
 475         check_mem_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 476
 477         /*------------------------------------------------------------------
 478          * Check the frequency supported for the dimms plugged.
 479          *-----------------------------------------------------------------*/
 480         check_frequency(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 481
 482         /*------------------------------------------------------------------
 483          * Check the total rank number.
 484          *-----------------------------------------------------------------*/
 485         check_rank_number(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 486
 487         /*------------------------------------------------------------------
 488          * Check the voltage type for the dimms plugged.
 489          *-----------------------------------------------------------------*/
 490         check_voltage_type(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 491
 492         /*------------------------------------------------------------------
 493          * Program SDRAM controller options 2 register
 494          * Except Enabling of the memory controller.
 495          *-----------------------------------------------------------------*/
 496         mfsdram(SDRAM_MCOPT2, val);
 497         mtsdram(SDRAM_MCOPT2,
 498                 (val &
 499                  ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_PMEN_MASK |
 500                    SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_XSRP_MASK |
 501                    SDRAM_MCOPT2_ISIE_MASK))
 502                 | (SDRAM_MCOPT2_SREN_ENTER | SDRAM_MCOPT2_PMEN_DISABLE |
 503                    SDRAM_MCOPT2_IPTR_IDLE | SDRAM_MCOPT2_XSRP_ALLOW |
 504                    SDRAM_MCOPT2_ISIE_ENABLE));
 505
 506         /*------------------------------------------------------------------
 507          * Program SDRAM controller options 1 register
 508          * Note: Does not enable the memory controller.
 509          *-----------------------------------------------------------------*/
 510         program_copt1(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 511
 512         /*------------------------------------------------------------------
 513          * Set the SDRAM Controller On Die Termination Register
 514          *-----------------------------------------------------------------*/
 515         program_codt(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 516
 517         /*------------------------------------------------------------------
 518          * Program SDRAM refresh register.
 519          *-----------------------------------------------------------------*/
 520         program_rtr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 521
 522         /*------------------------------------------------------------------
 523          * Program SDRAM mode register.
 524          *-----------------------------------------------------------------*/
 525         program_mode(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 526                      &selected_cas, &write_recovery);
 527
 528         /*------------------------------------------------------------------
 529          * Set the SDRAM Write Data/DM/DQS Clock Timing Reg
 530          *-----------------------------------------------------------------*/
 531         mfsdram(SDRAM_WRDTR, val);
 532         mtsdram(SDRAM_WRDTR, (val & ~(SDRAM_WRDTR_LLWP_MASK | SDRAM_WRDTR_WTR_MASK)) |
 533                 ddr_wrdtr(SDRAM_WRDTR_LLWP_1_CYC | SDRAM_WRDTR_WTR_90_DEG_ADV));
 534
 535         /*------------------------------------------------------------------
 536          * Set the SDRAM Clock Timing Register
 537          *-----------------------------------------------------------------*/
 538         mfsdram(SDRAM_CLKTR, val);
 539         mtsdram(SDRAM_CLKTR, (val & ~SDRAM_CLKTR_CLKP_MASK) |
 540                 ddr_clktr(SDRAM_CLKTR_CLKP_0_DEG));
 541
 542         /*------------------------------------------------------------------
 543          * Program the BxCF registers.
 544          *-----------------------------------------------------------------*/
 545         program_bxcf(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 546
 547         /*------------------------------------------------------------------
 548          * Program SDRAM timing registers.
 549          *-----------------------------------------------------------------*/
 550         program_tr(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 551
 552         /*------------------------------------------------------------------
 553          * Set the Extended Mode register
 554          *-----------------------------------------------------------------*/
 555         mfsdram(SDRAM_MEMODE, val);
 556         mtsdram(SDRAM_MEMODE,
 557                 (val & ~(SDRAM_MEMODE_DIC_MASK  | SDRAM_MEMODE_DLL_MASK |
 558                          SDRAM_MEMODE_RTT_MASK | SDRAM_MEMODE_DQS_MASK)) |
 559                 (SDRAM_MEMODE_DIC_NORMAL | SDRAM_MEMODE_DLL_ENABLE
 560                  | SDRAM_MEMODE_RTT_150OHM | SDRAM_MEMODE_DQS_ENABLE));
 561
 562         /*------------------------------------------------------------------
 563          * Program Initialization preload registers.
 564          *-----------------------------------------------------------------*/
 565         program_initplr(dimm_populated, iic0_dimm_addr, num_dimm_banks,
 566                         selected_cas, write_recovery);
 567
 568         /*------------------------------------------------------------------
 569          * Delay to ensure 200usec have elapsed since reset.
 570          *-----------------------------------------------------------------*/
 571         udelay(400);
 572
 573         /*------------------------------------------------------------------
 574          * Set the memory queue core base addr.
 575          *-----------------------------------------------------------------*/
 576         program_memory_queue(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 577
 578         /*------------------------------------------------------------------
 579          * Program SDRAM controller options 2 register
 580          * Enable the memory controller.
 581          *-----------------------------------------------------------------*/
 582         mfsdram(SDRAM_MCOPT2, val);
 583         mtsdram(SDRAM_MCOPT2,
 584                 (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK |
 585                          SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) |
 586                          SDRAM_MCOPT2_IPTR_EXECUTE);
 587
 588         /*------------------------------------------------------------------
 589          * Wait for IPTR_EXECUTE init sequence to complete.
 590          *-----------------------------------------------------------------*/
 591         do {
 592                 mfsdram(SDRAM_MCSTAT, val);
 593         } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP);
 594
 595         /* enable the controller only after init sequence completes */
 596         mfsdram(SDRAM_MCOPT2, val);
 597         mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE));
 598
 599         /* Make sure delay-line calibration is done before proceeding */
 600         do {
 601                 mfsdram(SDRAM_DLCR, val);
 602         } while (!(val & SDRAM_DLCR_DLCS_COMPLETE));
 603
 604         /* get installed memory size */
 605         dram_size = sdram_memsize();
 606
 607         /*
 608          * Limit size to 2GB
 609          */
 610         if (dram_size > CONFIG_MAX_MEM_MAPPED)
 611                 dram_size = CONFIG_MAX_MEM_MAPPED;
 612
 613         /* and program tlb entries for this size (dynamic) */
 614
 615         /*
 616          * Program TLB entries with caches enabled, for best performace
 617          * while auto-calibrating and ECC generation
 618          */
 619         program_tlb(0, 0, dram_size, 0);
 620
 621         /*------------------------------------------------------------------
 622          * DQS calibration.
 623          *-----------------------------------------------------------------*/
 624 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
 625         DQS_autocalibration();
 626 #else
 627         program_DQS_calibration(dimm_populated, iic0_dimm_addr, num_dimm_banks);
 628 #endif
 629         /*
 630          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
 631          * PowerPC440SP/SPe DDR2 application note:
 632          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
 633          */
 634         update_rdcc();
 635
 636 #ifdef CONFIG_DDR_ECC
 637         /*------------------------------------------------------------------
 638          * If ecc is enabled, initialize the parity bits.
 639          *-----------------------------------------------------------------*/
 640         program_ecc(dimm_populated, iic0_dimm_addr, num_dimm_banks, 0);
 641 #endif
 642
 643         /*
 644          * Flush the dcache before removing the TLB with caches
 645          * enabled. Otherwise this might lead to problems later on,
 646          * e.g. while booting Linux (as seen on ICON-440SPe).
 647          */
 648         flush_dcache();
 649
 650         /*
 651          * Now after initialization (auto-calibration and ECC generation)
 652          * remove the TLB entries with caches enabled and program again with
 653          * desired cache functionality
 654          */
 655         remove_tlb(0, dram_size);
 656         program_tlb(0, 0, dram_size, MY_TLB_WORD2_I_ENABLE);
 657
 658         ppc4xx_ibm_ddr2_register_dump();
 659
 660         /*
 661          * Clear potential errors resulting from auto-calibration.
 662          * If not done, then we could get an interrupt later on when
 663          * exceptions are enabled.
 664          */
 665         set_mcsr(get_mcsr());
 666
 667         return sdram_memsize();
 668 }
 669
 670 static void get_spd_info(unsigned long *dimm_populated,
 671                          unsigned char *iic0_dimm_addr,
 672                          unsigned long num_dimm_banks)
 673 {
 674         unsigned long dimm_num;
 675         unsigned long dimm_found;
 676         unsigned char num_of_bytes;
 677         unsigned char total_size;
 678
 679         dimm_found = false;
 680         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 681                 num_of_bytes = 0;
 682                 total_size = 0;
 683
 684                 num_of_bytes = spd_read(iic0_dimm_addr[dimm_num], 0);
 685                 debug("\nspd_read(0x%x) returned %d\n",
 686                       iic0_dimm_addr[dimm_num], num_of_bytes);
 687                 total_size = spd_read(iic0_dimm_addr[dimm_num], 1);
 688                 debug("spd_read(0x%x) returned %d\n",
 689                       iic0_dimm_addr[dimm_num], total_size);
 690
 691                 if ((num_of_bytes != 0) && (total_size != 0)) {
 692                         dimm_populated[dimm_num] = true;
 693                         dimm_found = true;
 694                         debug("DIMM slot %lu: populated\n", dimm_num);
 695                 } else {
 696                         dimm_populated[dimm_num] = false;
 697                         debug("DIMM slot %lu: Not populated\n", dimm_num);
 698                 }
 699         }
 700
 701         if (dimm_found == false) {
 702                 printf("ERROR - No memory installed. Install a DDR-SDRAM DIMM.\n\n");
 703                 spd_ddr_init_hang ();
 704         }
 705 }
 706
 707
 708 /*------------------------------------------------------------------
 709  * For the memory DIMMs installed, this routine verifies that they
 710  * really are DDR specific DIMMs.
 711  *-----------------------------------------------------------------*/
 712 static void check_mem_type(unsigned long *dimm_populated,
 713                            unsigned char *iic0_dimm_addr,
 714                            unsigned long num_dimm_banks)
 715 {
 716         unsigned long dimm_num;
 717         unsigned long dimm_type;
 718
 719         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 720                 if (dimm_populated[dimm_num] == true) {
 721                         dimm_type = spd_read(iic0_dimm_addr[dimm_num], 2);
 722                         switch (dimm_type) {
 723                         case 1:
 724                                 printf("ERROR: Standard Fast Page Mode DRAM DIMM detected in "
 725                                        "slot %d.\n", (unsigned int)dimm_num);
 726                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 727                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 728                                 spd_ddr_init_hang ();
 729                                 break;
 730                         case 2:
 731                                 printf("ERROR: EDO DIMM detected in slot %d.\n",
 732                                        (unsigned int)dimm_num);
 733                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 734                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 735                                 spd_ddr_init_hang ();
 736                                 break;
 737                         case 3:
 738                                 printf("ERROR: Pipelined Nibble DIMM detected in slot %d.\n",
 739                                        (unsigned int)dimm_num);
 740                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 741                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 742                                 spd_ddr_init_hang ();
 743                                 break;
 744                         case 4:
 745                                 printf("ERROR: SDRAM DIMM detected in slot %d.\n",
 746                                        (unsigned int)dimm_num);
 747                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 748                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 749                                 spd_ddr_init_hang ();
 750                                 break;
 751                         case 5:
 752                                 printf("ERROR: Multiplexed ROM DIMM detected in slot %d.\n",
 753                                        (unsigned int)dimm_num);
 754                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 755                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 756                                 spd_ddr_init_hang ();
 757                                 break;
 758                         case 6:
 759                                 printf("ERROR: SGRAM DIMM detected in slot %d.\n",
 760                                        (unsigned int)dimm_num);
 761                                 printf("Only DDR and DDR2 SDRAM DIMMs are supported.\n");
 762                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 763                                 spd_ddr_init_hang ();
 764                                 break;
 765                         case 7:
 766                                 debug("DIMM slot %lu: DDR1 SDRAM detected\n", dimm_num);
 767                                 dimm_populated[dimm_num] = SDRAM_DDR1;
 768                                 break;
 769                         case 8:
 770                                 debug("DIMM slot %lu: DDR2 SDRAM detected\n", dimm_num);
 771                                 dimm_populated[dimm_num] = SDRAM_DDR2;
 772                                 break;
 773                         default:
 774                                 printf("ERROR: Unknown DIMM detected in slot %d.\n",
 775                                        (unsigned int)dimm_num);
 776                                 printf("Only DDR1 and DDR2 SDRAM DIMMs are supported.\n");
 777                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 778                                 spd_ddr_init_hang ();
 779                                 break;
 780                         }
 781                 }
 782         }
 783         for (dimm_num = 1; dimm_num < num_dimm_banks; dimm_num++) {
 784                 if ((dimm_populated[dimm_num-1] != SDRAM_NONE)
 785                     && (dimm_populated[dimm_num]   != SDRAM_NONE)
 786                     && (dimm_populated[dimm_num-1] != dimm_populated[dimm_num])) {
 787                         printf("ERROR: DIMM's DDR1 and DDR2 type can not be mixed.\n");
 788                         spd_ddr_init_hang ();
 789                 }
 790         }
 791 }
 792
 793 /*------------------------------------------------------------------
 794  * For the memory DIMMs installed, this routine verifies that
 795  * frequency previously calculated is supported.
 796  *-----------------------------------------------------------------*/
 797 static void check_frequency(unsigned long *dimm_populated,
 798                             unsigned char *iic0_dimm_addr,
 799                             unsigned long num_dimm_banks)
 800 {
 801         unsigned long dimm_num;
 802         unsigned long tcyc_reg;
 803         unsigned long cycle_time;
 804         unsigned long calc_cycle_time;
 805         unsigned long sdram_freq;
 806         unsigned long sdr_ddrpll;
 807         PPC4xx_SYS_INFO board_cfg;
 808
 809         /*------------------------------------------------------------------
 810          * Get the board configuration info.
 811          *-----------------------------------------------------------------*/
 812         get_sys_info(&board_cfg);
 813
 814         mfsdr(SDR0_DDR0, sdr_ddrpll);
 815         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
 816
 817         /*
 818          * calc_cycle_time is calculated from DDR frequency set by board/chip
 819          * and is expressed in multiple of 10 picoseconds
 820          * to match the way DIMM cycle time is calculated below.
 821          */
 822         calc_cycle_time = MULDIV64(ONE_BILLION, 100, sdram_freq);
 823
 824         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 825                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 826                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
 827                         /*
 828                          * Byte 9, Cycle time for CAS Latency=X, is split into two nibbles:
 829                          * the higher order nibble (bits 4-7) designates the cycle time
 830                          * to a granularity of 1ns;
 831                          * the value presented by the lower order nibble (bits 0-3)
 832                          * has a granularity of .1ns and is added to the value designated
 833                          * by the higher nibble. In addition, four lines of the lower order
 834                          * nibble are assigned to support +.25,+.33, +.66 and +.75.
 835                          */
 836                          /* Convert from hex to decimal */
 837                         if ((tcyc_reg & 0x0F) == 0x0D)
 838                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
 839                         else if ((tcyc_reg & 0x0F) == 0x0C)
 840                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 66;
 841                         else if ((tcyc_reg & 0x0F) == 0x0B)
 842                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 33;
 843                         else if ((tcyc_reg & 0x0F) == 0x0A)
 844                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) + 25;
 845                         else
 846                                 cycle_time = (((tcyc_reg & 0xF0) >> 4) * 100) +
 847                                         ((tcyc_reg & 0x0F)*10);
 848                         debug("cycle_time=%lu [10 picoseconds]\n", cycle_time);
 849
 850                         if  (cycle_time > (calc_cycle_time + 10)) {
 851                                 /*
 852                                  * the provided sdram cycle_time is too small
 853                                  * for the available DIMM cycle_time.
 854                                  * The additionnal 100ps is here to accept a small incertainty.
 855                                  */
 856                                 printf("ERROR: DRAM DIMM detected with cycle_time %d ps in "
 857                                        "slot %d \n while calculated cycle time is %d ps.\n",
 858                                        (unsigned int)(cycle_time*10),
 859                                        (unsigned int)dimm_num,
 860                                        (unsigned int)(calc_cycle_time*10));
 861                                 printf("Replace the DIMM, or change DDR frequency via "
 862                                        "strapping bits.\n\n");
 863                                 spd_ddr_init_hang ();
 864                         }
 865                 }
 866         }
 867 }
 868
 869 /*------------------------------------------------------------------
 870  * For the memory DIMMs installed, this routine verifies two
 871  * ranks/banks maximum are availables.
 872  *-----------------------------------------------------------------*/
 873 static void check_rank_number(unsigned long *dimm_populated,
 874                               unsigned char *iic0_dimm_addr,
 875                               unsigned long num_dimm_banks)
 876 {
 877         unsigned long dimm_num;
 878         unsigned long dimm_rank;
 879         unsigned long total_rank = 0;
 880
 881         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 882                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 883                         dimm_rank = spd_read(iic0_dimm_addr[dimm_num], 5);
 884                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
 885                                 dimm_rank = (dimm_rank & 0x0F) +1;
 886                         else
 887                                 dimm_rank = dimm_rank & 0x0F;
 888
 889
 890                         if (dimm_rank > MAXRANKS) {
 891                                 printf("ERROR: DRAM DIMM detected with %lu ranks in "
 892                                        "slot %lu is not supported.\n", dimm_rank, dimm_num);
 893                                 printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 894                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
 895                                 spd_ddr_init_hang ();
 896                         } else
 897                                 total_rank += dimm_rank;
 898                 }
 899                 if (total_rank > MAXRANKS) {
 900                         printf("ERROR: DRAM DIMM detected with a total of %d ranks "
 901                                "for all slots.\n", (unsigned int)total_rank);
 902                         printf("Only %d ranks are supported for all DIMM.\n", MAXRANKS);
 903                         printf("Remove one of the DIMM modules.\n\n");
 904                         spd_ddr_init_hang ();
 905                 }
 906         }
 907 }
 908
 909 /*------------------------------------------------------------------
 910  * only support 2.5V modules.
 911  * This routine verifies this.
 912  *-----------------------------------------------------------------*/
 913 static void check_voltage_type(unsigned long *dimm_populated,
 914                                unsigned char *iic0_dimm_addr,
 915                                unsigned long num_dimm_banks)
 916 {
 917         unsigned long dimm_num;
 918         unsigned long voltage_type;
 919
 920         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
 921                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
 922                         voltage_type = spd_read(iic0_dimm_addr[dimm_num], 8);
 923                         switch (voltage_type) {
 924                         case 0x00:
 925                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 926                                 printf("This DIMM is 5.0 Volt/TTL.\n");
 927                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 928                                        (unsigned int)dimm_num);
 929                                 spd_ddr_init_hang ();
 930                                 break;
 931                         case 0x01:
 932                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 933                                 printf("This DIMM is LVTTL.\n");
 934                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 935                                        (unsigned int)dimm_num);
 936                                 spd_ddr_init_hang ();
 937                                 break;
 938                         case 0x02:
 939                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 940                                 printf("This DIMM is 1.5 Volt.\n");
 941                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 942                                        (unsigned int)dimm_num);
 943                                 spd_ddr_init_hang ();
 944                                 break;
 945                         case 0x03:
 946                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 947                                 printf("This DIMM is 3.3 Volt/TTL.\n");
 948                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 949                                        (unsigned int)dimm_num);
 950                                 spd_ddr_init_hang ();
 951                                 break;
 952                         case 0x04:
 953                                 /* 2.5 Voltage only for DDR1 */
 954                                 break;
 955                         case 0x05:
 956                                 /* 1.8 Voltage only for DDR2 */
 957                                 break;
 958                         default:
 959                                 printf("ERROR: Only DIMMs DDR 2.5V or DDR2 1.8V are supported.\n");
 960                                 printf("Replace the DIMM module in slot %d with a supported DIMM.\n\n",
 961                                        (unsigned int)dimm_num);
 962                                 spd_ddr_init_hang ();
 963                                 break;
 964                         }
 965                 }
 966         }
 967 }
 968
 969 /*-----------------------------------------------------------------------------+
 970  * program_copt1.
 971  *-----------------------------------------------------------------------------*/
 972 static void program_copt1(unsigned long *dimm_populated,
 973                           unsigned char *iic0_dimm_addr,
 974                           unsigned long num_dimm_banks)
 975 {
 976         unsigned long dimm_num;
 977         unsigned long mcopt1;
 978         unsigned long ecc_enabled;
 979         unsigned long ecc = 0;
 980         unsigned long data_width = 0;
 981         unsigned long dimm_32bit;
 982         unsigned long dimm_64bit;
 983         unsigned long registered = 0;
 984         unsigned long attribute = 0;
 985         unsigned long buf0, buf1; /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
 986         unsigned long bankcount;
 987         unsigned long val;
 988
 989 #ifdef CONFIG_DDR_ECC
 990         ecc_enabled = true;
 991 #else
 992         ecc_enabled = false;
 993 #endif
 994         dimm_32bit = false;
 995         dimm_64bit = false;
 996         buf0 = false;
 997         buf1 = false;
 998
 999         /*------------------------------------------------------------------
1000          * Set memory controller options reg 1, SDRAM_MCOPT1.
1001          *-----------------------------------------------------------------*/
1002         mfsdram(SDRAM_MCOPT1, val);
1003         mcopt1 = val & ~(SDRAM_MCOPT1_MCHK_MASK | SDRAM_MCOPT1_RDEN_MASK |
1004                          SDRAM_MCOPT1_PMU_MASK  | SDRAM_MCOPT1_DMWD_MASK |
1005                          SDRAM_MCOPT1_UIOS_MASK | SDRAM_MCOPT1_BCNT_MASK |
1006                          SDRAM_MCOPT1_DDR_TYPE_MASK | SDRAM_MCOPT1_RWOO_MASK |
1007                          SDRAM_MCOPT1_WOOO_MASK | SDRAM_MCOPT1_DCOO_MASK |
1008                          SDRAM_MCOPT1_DREF_MASK);
1009
1010         mcopt1 |= SDRAM_MCOPT1_QDEP;
1011         mcopt1 |= SDRAM_MCOPT1_PMU_OPEN;
1012         mcopt1 |= SDRAM_MCOPT1_RWOO_DISABLED;
1013         mcopt1 |= SDRAM_MCOPT1_WOOO_DISABLED;
1014         mcopt1 |= SDRAM_MCOPT1_DCOO_DISABLED;
1015         mcopt1 |= SDRAM_MCOPT1_DREF_NORMAL;
1016
1017         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1018                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1019                         /* test ecc support */
1020                         ecc = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 11);
1021                         if (ecc != 0x02) /* ecc not supported */
1022                                 ecc_enabled = false;
1023
1024                         /* test bank count */
1025                         bankcount = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 17);
1026                         if (bankcount == 0x04) /* bank count = 4 */
1027                                 mcopt1 |= SDRAM_MCOPT1_4_BANKS;
1028                         else /* bank count = 8 */
1029                                 mcopt1 |= SDRAM_MCOPT1_8_BANKS;
1030
1031                         /* test for buffered/unbuffered, registered, differential clocks */
1032                         registered = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 20);
1033                         attribute = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 21);
1034
1035                         /* TODO: code to be changed for IOP1.6 to support 4 DIMMs */
1036                         if (dimm_num == 0) {
1037                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1038                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1039                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1040                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1041                                 if (registered == 1) { /* DDR2 always buffered */
1042                                         /* TODO: what about above  comments ? */
1043                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1044                                         buf0 = true;
1045                                 } else {
1046                                         /* TODO: the mask 0x02 doesn't match Samsung def for byte 21. */
1047                                         if ((attribute & 0x02) == 0x00) {
1048                                                 /* buffered not supported */
1049                                                 buf0 = false;
1050                                         } else {
1051                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1052                                                 buf0 = true;
1053                                         }
1054                                 }
1055                         }
1056                         else if (dimm_num == 1) {
1057                                 if (dimm_populated[dimm_num] == SDRAM_DDR1) /* DDR1 type */
1058                                         mcopt1 |= SDRAM_MCOPT1_DDR1_TYPE;
1059                                 if (dimm_populated[dimm_num] == SDRAM_DDR2) /* DDR2 type */
1060                                         mcopt1 |= SDRAM_MCOPT1_DDR2_TYPE;
1061                                 if (registered == 1) {
1062                                         /* DDR2 always buffered */
1063                                         mcopt1 |= SDRAM_MCOPT1_RDEN;
1064                                         buf1 = true;
1065                                 } else {
1066                                         if ((attribute & 0x02) == 0x00) {
1067                                                 /* buffered not supported */
1068                                                 buf1 = false;
1069                                         } else {
1070                                                 mcopt1 |= SDRAM_MCOPT1_RDEN;
1071                                                 buf1 = true;
1072                                         }
1073                                 }
1074                         }
1075
1076                         /* Note that for DDR2 the byte 7 is reserved, but OK to keep code as is. */
1077                         data_width = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 6) +
1078                                 (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 7)) << 8);
1079
1080                         switch (data_width) {
1081                         case 72:
1082                         case 64:
1083                                 dimm_64bit = true;
1084                                 break;
1085                         case 40:
1086                         case 32:
1087                                 dimm_32bit = true;
1088                                 break;
1089                         default:
1090                                 printf("WARNING: Detected a DIMM with a data width of %lu bits.\n",
1091                                        data_width);
1092                                 printf("Only DIMMs with 32 or 64 bit DDR-SDRAM widths are supported.\n");
1093                                 break;
1094                         }
1095                 }
1096         }
1097
1098         /* verify matching properties */
1099         if ((dimm_populated[0] != SDRAM_NONE) && (dimm_populated[1] != SDRAM_NONE)) {
1100                 if (buf0 != buf1) {
1101                         printf("ERROR: DIMM's buffered/unbuffered, registered, clocking don't match.\n");
1102                         spd_ddr_init_hang ();
1103                 }
1104         }
1105
1106         if ((dimm_64bit == true) && (dimm_32bit == true)) {
1107                 printf("ERROR: Cannot mix 32 bit and 64 bit DDR-SDRAM DIMMs together.\n");
1108                 spd_ddr_init_hang ();
1109         } else if ((dimm_64bit == true) && (dimm_32bit == false)) {
1110                 mcopt1 |= SDRAM_MCOPT1_DMWD_64;
1111         } else if ((dimm_64bit == false) && (dimm_32bit == true)) {
1112                 mcopt1 |= SDRAM_MCOPT1_DMWD_32;
1113         } else {
1114                 printf("ERROR: Please install only 32 or 64 bit DDR-SDRAM DIMMs.\n\n");
1115                 spd_ddr_init_hang ();
1116         }
1117
1118         if (ecc_enabled == true)
1119                 mcopt1 |= SDRAM_MCOPT1_MCHK_GEN;
1120         else
1121                 mcopt1 |= SDRAM_MCOPT1_MCHK_NON;
1122
1123         mtsdram(SDRAM_MCOPT1, mcopt1);
1124 }
1125
1126 /*-----------------------------------------------------------------------------+
1127  * program_codt.
1128  *-----------------------------------------------------------------------------*/
1129 static void program_codt(unsigned long *dimm_populated,
1130                          unsigned char *iic0_dimm_addr,
1131                          unsigned long num_dimm_banks)
1132 {
1133         unsigned long codt;
1134         unsigned long modt0 = 0;
1135         unsigned long modt1 = 0;
1136         unsigned long modt2 = 0;
1137         unsigned long modt3 = 0;
1138         unsigned char dimm_num;
1139         unsigned char dimm_rank;
1140         unsigned char total_rank = 0;
1141         unsigned char total_dimm = 0;
1142         unsigned char dimm_type = 0;
1143         unsigned char firstSlot = 0;
1144
1145         /*------------------------------------------------------------------
1146          * Set the SDRAM Controller On Die Termination Register
1147          *-----------------------------------------------------------------*/
1148         mfsdram(SDRAM_CODT, codt);
1149         codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END);
1150         codt |= SDRAM_CODT_IO_NMODE;
1151
1152         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1153                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1154                         dimm_rank = (unsigned long)spd_read(iic0_dimm_addr[dimm_num], 5);
1155                         if (((unsigned long)spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08) {
1156                                 dimm_rank = (dimm_rank & 0x0F) + 1;
1157                                 dimm_type = SDRAM_DDR2;
1158                         } else {
1159                                 dimm_rank = dimm_rank & 0x0F;
1160                                 dimm_type = SDRAM_DDR1;
1161                         }
1162
1163                         total_rank += dimm_rank;
1164                         total_dimm++;
1165                         if ((dimm_num == 0) && (total_dimm == 1))
1166                                 firstSlot = true;
1167                         else
1168                                 firstSlot = false;
1169                 }
1170         }
1171         if (dimm_type == SDRAM_DDR2) {
1172                 codt |= SDRAM_CODT_DQS_1_8_V_DDR2;
1173                 if ((total_dimm == 1) && (firstSlot == true)) {
1174                         if (total_rank == 1) {  /* PUUU */
1175                                 codt |= CALC_ODT_R(0);
1176                                 modt0 = CALC_ODT_W(0);
1177                                 modt1 = 0x00000000;
1178                                 modt2 = 0x00000000;
1179                                 modt3 = 0x00000000;
1180                         }
1181                         if (total_rank == 2) {  /* PPUU */
1182                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1);
1183                                 modt0 = CALC_ODT_W(0) | CALC_ODT_W(1);
1184                                 modt1 = 0x00000000;
1185                                 modt2 = 0x00000000;
1186                                 modt3 = 0x00000000;
1187                         }
1188                 } else if ((total_dimm == 1) && (firstSlot != true)) {
1189                         if (total_rank == 1) {  /* UUPU */
1190                                 codt |= CALC_ODT_R(2);
1191                                 modt0 = 0x00000000;
1192                                 modt1 = 0x00000000;
1193                                 modt2 = CALC_ODT_W(2);
1194                                 modt3 = 0x00000000;
1195                         }
1196                         if (total_rank == 2) {  /* UUPP */
1197                                 codt |= CALC_ODT_R(2) | CALC_ODT_R(3);
1198                                 modt0 = 0x00000000;
1199                                 modt1 = 0x00000000;
1200                                 modt2 = CALC_ODT_W(2) | CALC_ODT_W(3);
1201                                 modt3 = 0x00000000;
1202                         }
1203                 }
1204                 if (total_dimm == 2) {
1205                         if (total_rank == 2) {  /* PUPU */
1206                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(2);
1207                                 modt0 = CALC_ODT_RW(2);
1208                                 modt1 = 0x00000000;
1209                                 modt2 = CALC_ODT_RW(0);
1210                                 modt3 = 0x00000000;
1211                         }
1212                         if (total_rank == 4) {  /* PPPP */
1213                                 codt |= CALC_ODT_R(0) | CALC_ODT_R(1) |
1214                                         CALC_ODT_R(2) | CALC_ODT_R(3);
1215                                 modt0 = CALC_ODT_RW(2) | CALC_ODT_RW(3);
1216                                 modt1 = 0x00000000;
1217                                 modt2 = CALC_ODT_RW(0) | CALC_ODT_RW(1);
1218                                 modt3 = 0x00000000;
1219                         }
1220                 }
1221         } else {
1222                 codt |= SDRAM_CODT_DQS_2_5_V_DDR1;
1223                 modt0 = 0x00000000;
1224                 modt1 = 0x00000000;
1225                 modt2 = 0x00000000;
1226                 modt3 = 0x00000000;
1227
1228                 if (total_dimm == 1) {
1229                         if (total_rank == 1)
1230                                 codt |= 0x00800000;
1231                         if (total_rank == 2)
1232                                 codt |= 0x02800000;
1233                 }
1234                 if (total_dimm == 2) {
1235                         if (total_rank == 2)
1236                                 codt |= 0x08800000;
1237                         if (total_rank == 4)
1238                                 codt |= 0x2a800000;
1239                 }
1240         }
1241
1242         debug("nb of dimm %d\n", total_dimm);
1243         debug("nb of rank %d\n", total_rank);
1244         if (total_dimm == 1)
1245                 debug("dimm in slot %d\n", firstSlot);
1246
1247         mtsdram(SDRAM_CODT, codt);
1248         mtsdram(SDRAM_MODT0, modt0);
1249         mtsdram(SDRAM_MODT1, modt1);
1250         mtsdram(SDRAM_MODT2, modt2);
1251         mtsdram(SDRAM_MODT3, modt3);
1252 }
1253
1254 /*-----------------------------------------------------------------------------+
1255  * program_initplr.
1256  *-----------------------------------------------------------------------------*/
1257 static void program_initplr(unsigned long *dimm_populated,
1258                             unsigned char *iic0_dimm_addr,
1259                             unsigned long num_dimm_banks,
1260                             ddr_cas_id_t selected_cas,
1261                             int write_recovery)
1262 {
1263         u32 cas = 0;
1264         u32 odt = 0;
1265         u32 ods = 0;
1266         u32 mr;
1267         u32 wr;
1268         u32 emr;
1269         u32 emr2;
1270         u32 emr3;
1271         int dimm_num;
1272         int total_dimm = 0;
1273
1274         /******************************************************
1275          ** Assumption: if more than one DIMM, all DIMMs are the same
1276          **             as already checked in check_memory_type
1277          ******************************************************/
1278
1279         if ((dimm_populated[0] == SDRAM_DDR1) || (dimm_populated[1] == SDRAM_DDR1)) {
1280                 mtsdram(SDRAM_INITPLR0, 0x81B80000);
1281                 mtsdram(SDRAM_INITPLR1, 0x81900400);
1282                 mtsdram(SDRAM_INITPLR2, 0x81810000);
1283                 mtsdram(SDRAM_INITPLR3, 0xff800162);
1284                 mtsdram(SDRAM_INITPLR4, 0x81900400);
1285                 mtsdram(SDRAM_INITPLR5, 0x86080000);
1286                 mtsdram(SDRAM_INITPLR6, 0x86080000);
1287                 mtsdram(SDRAM_INITPLR7, 0x81000062);
1288         } else if ((dimm_populated[0] == SDRAM_DDR2) || (dimm_populated[1] == SDRAM_DDR2)) {
1289                 switch (selected_cas) {
1290                 case DDR_CAS_3:
1291                         cas = 3 << 4;
1292                         break;
1293                 case DDR_CAS_4:
1294                         cas = 4 << 4;
1295                         break;
1296                 case DDR_CAS_5:
1297                         cas = 5 << 4;
1298                         break;
1299                 default:
1300                         printf("ERROR: ucode error on selected_cas value %d", selected_cas);
1301                         spd_ddr_init_hang ();
1302                         break;
1303                 }
1304
1305 #if 0
1306                 /*
1307                  * ToDo - Still a problem with the write recovery:
1308                  * On the Corsair CM2X512-5400C4 module, setting write recovery
1309                  * in the INITPLR reg to the value calculated in program_mode()
1310                  * results in not correctly working DDR2 memory (crash after
1311                  * relocation).
1312                  *
1313                  * So for now, set the write recovery to 3. This seems to work
1314                  * on the Corair module too.
1315                  *
1316                  * 2007-03-01, sr
1317                  */
1318                 switch (write_recovery) {
1319                 case 3:
1320                         wr = WRITE_RECOV_3;
1321                         break;
1322                 case 4:
1323                         wr = WRITE_RECOV_4;
1324                         break;
1325                 case 5:
1326                         wr = WRITE_RECOV_5;
1327                         break;
1328                 case 6:
1329                         wr = WRITE_RECOV_6;
1330                         break;
1331                 default:
1332                         printf("ERROR: write recovery not support (%d)", write_recovery);
1333                         spd_ddr_init_hang ();
1334                         break;
1335                 }
1336 #else
1337                 wr = WRITE_RECOV_3; /* test-only, see description above */
1338 #endif
1339
1340                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++)
1341                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1342                                 total_dimm++;
1343                 if (total_dimm == 1) {
1344                         odt = ODT_150_OHM;
1345                         ods = ODS_FULL;
1346                 } else if (total_dimm == 2) {
1347                         odt = ODT_75_OHM;
1348                         ods = ODS_REDUCED;
1349                 } else {
1350                         printf("ERROR: Unsupported number of DIMM's (%d)", total_dimm);
1351                         spd_ddr_init_hang ();
1352                 }
1353
1354                 mr = CMD_EMR | SELECT_MR | BURST_LEN_4 | wr | cas;
1355                 emr = CMD_EMR | SELECT_EMR | odt | ods;
1356                 emr2 = CMD_EMR | SELECT_EMR2;
1357                 emr3 = CMD_EMR | SELECT_EMR3;
1358                 /* NOP - Wait 106 MemClk cycles */
1359                 mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP |
1360                                         SDRAM_INITPLR_IMWT_ENCODE(106));
1361                 udelay(1000);
1362                 /* precharge 4 MemClk cycles */
1363                 mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1364                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1365                 /* EMR2 - Wait tMRD (2 MemClk cycles) */
1366                 mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 |
1367                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1368                 /* EMR3 - Wait tMRD (2 MemClk cycles) */
1369                 mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 |
1370                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1371                 /* EMR DLL ENABLE - Wait tMRD (2 MemClk cycles) */
1372                 mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr |
1373                                         SDRAM_INITPLR_IMWT_ENCODE(2));
1374                 /* MR w/ DLL reset - 200 cycle wait for DLL reset */
1375                 mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET |
1376                                         SDRAM_INITPLR_IMWT_ENCODE(200));
1377                 udelay(1000);
1378                 /* precharge 4 MemClk cycles */
1379                 mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE |
1380                                         SDRAM_INITPLR_IMWT_ENCODE(4));
1381                 /* Refresh 25 MemClk cycles */
1382                 mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1383                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1384                 /* Refresh 25 MemClk cycles */
1385                 mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1386                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1387                 /* Refresh 25 MemClk cycles */
1388                 mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1389                                         SDRAM_INITPLR_IMWT_ENCODE(25));
1390                 /* Refresh 25 MemClk cycles */
1391                 mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH |
1392                                          SDRAM_INITPLR_IMWT_ENCODE(25));
1393                 /* MR w/o DLL reset - Wait tMRD (2 MemClk cycles) */
1394                 mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr |
1395                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1396                 /* EMR OCD Default - Wait tMRD (2 MemClk cycles) */
1397                 mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF |
1398                                          SDRAM_INITPLR_IMWT_ENCODE(2) | emr);
1399                 /* EMR OCD Exit */
1400                 mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr |
1401                                          SDRAM_INITPLR_IMWT_ENCODE(2));
1402         } else {
1403                 printf("ERROR: ucode error as unknown DDR type in program_initplr");
1404                 spd_ddr_init_hang ();
1405         }
1406 }
1407
1408 /*------------------------------------------------------------------
1409  * This routine programs the SDRAM_MMODE register.
1410  * the selected_cas is an output parameter, that will be passed
1411  * by caller to call the above program_initplr( )
1412  *-----------------------------------------------------------------*/
1413 static void program_mode(unsigned long *dimm_populated,
1414                          unsigned char *iic0_dimm_addr,
1415                          unsigned long num_dimm_banks,
1416                          ddr_cas_id_t *selected_cas,
1417                          int *write_recovery)
1418 {
1419         unsigned long dimm_num;
1420         unsigned long sdram_ddr1;
1421         unsigned long t_wr_ns;
1422         unsigned long t_wr_clk;
1423         unsigned long cas_bit;
1424         unsigned long cas_index;
1425         unsigned long sdram_freq;
1426         unsigned long ddr_check;
1427         unsigned long mmode;
1428         unsigned long tcyc_reg;
1429         unsigned long cycle_2_0_clk;
1430         unsigned long cycle_2_5_clk;
1431         unsigned long cycle_3_0_clk;
1432         unsigned long cycle_4_0_clk;
1433         unsigned long cycle_5_0_clk;
1434         unsigned long max_2_0_tcyc_ns_x_100;
1435         unsigned long max_2_5_tcyc_ns_x_100;
1436         unsigned long max_3_0_tcyc_ns_x_100;
1437         unsigned long max_4_0_tcyc_ns_x_100;
1438         unsigned long max_5_0_tcyc_ns_x_100;
1439         unsigned long cycle_time_ns_x_100[3];
1440         PPC4xx_SYS_INFO board_cfg;
1441         unsigned char cas_2_0_available;
1442         unsigned char cas_2_5_available;
1443         unsigned char cas_3_0_available;
1444         unsigned char cas_4_0_available;
1445         unsigned char cas_5_0_available;
1446         unsigned long sdr_ddrpll;
1447
1448         /*------------------------------------------------------------------
1449          * Get the board configuration info.
1450          *-----------------------------------------------------------------*/
1451         get_sys_info(&board_cfg);
1452
1453         mfsdr(SDR0_DDR0, sdr_ddrpll);
1454         sdram_freq = MULDIV64((board_cfg.freqPLB), SDR0_DDR0_DDRM_DECODE(sdr_ddrpll), 1);
1455         debug("sdram_freq=%lu\n", sdram_freq);
1456
1457         /*------------------------------------------------------------------
1458          * Handle the timing.  We need to find the worst case timing of all
1459          * the dimm modules installed.
1460          *-----------------------------------------------------------------*/
1461         t_wr_ns = 0;
1462         cas_2_0_available = true;
1463         cas_2_5_available = true;
1464         cas_3_0_available = true;
1465         cas_4_0_available = true;
1466         cas_5_0_available = true;
1467         max_2_0_tcyc_ns_x_100 = 10;
1468         max_2_5_tcyc_ns_x_100 = 10;
1469         max_3_0_tcyc_ns_x_100 = 10;
1470         max_4_0_tcyc_ns_x_100 = 10;
1471         max_5_0_tcyc_ns_x_100 = 10;
1472         sdram_ddr1 = true;
1473
1474         /* loop through all the DIMM slots on the board */
1475         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1476                 /* If a dimm is installed in a particular slot ... */
1477                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1478                         if (dimm_populated[dimm_num] == SDRAM_DDR1)
1479                                 sdram_ddr1 = true;
1480                         else
1481                                 sdram_ddr1 = false;
1482
1483                         cas_bit = spd_read(iic0_dimm_addr[dimm_num], 18);
1484                         debug("cas_bit[SPD byte 18]=%02lx\n", cas_bit);
1485
1486                         /* For a particular DIMM, grab the three CAS values it supports */
1487                         for (cas_index = 0; cas_index < 3; cas_index++) {
1488                                 switch (cas_index) {
1489                                 case 0:
1490                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 9);
1491                                         break;
1492                                 case 1:
1493                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 23);
1494                                         break;
1495                                 default:
1496                                         tcyc_reg = spd_read(iic0_dimm_addr[dimm_num], 25);
1497                                         break;
1498                                 }
1499
1500                                 if ((tcyc_reg & 0x0F) >= 10) {
1501                                         if ((tcyc_reg & 0x0F) == 0x0D) {
1502                                                 /* Convert from hex to decimal */
1503                                                 cycle_time_ns_x_100[cas_index] =
1504                                                         (((tcyc_reg & 0xF0) >> 4) * 100) + 75;
1505                                         } else {
1506                                                 printf("ERROR: SPD reported Tcyc is incorrect for DIMM "
1507                                                        "in slot %d\n", (unsigned int)dimm_num);
1508                                                 spd_ddr_init_hang ();
1509                                         }
1510                                 } else {
1511                                         /* Convert from hex to decimal */
1512                                         cycle_time_ns_x_100[cas_index] =
1513                                                 (((tcyc_reg & 0xF0) >> 4) * 100) +
1514                                                 ((tcyc_reg & 0x0F)*10);
1515                                 }
1516                                 debug("cas_index=%lu: cycle_time_ns_x_100=%lu\n", cas_index,
1517                                       cycle_time_ns_x_100[cas_index]);
1518                         }
1519
1520                         /* The rest of this routine determines if CAS 2.0, 2.5, 3.0, 4.0 and 5.0 are */
1521                         /* supported for a particular DIMM. */
1522                         cas_index = 0;
1523
1524                         if (sdram_ddr1) {
1525                                 /*
1526                                  * DDR devices use the following bitmask for CAS latency:
1527                                  *  Bit   7    6    5    4    3    2    1    0
1528                                  *       TBD  4.0  3.5  3.0  2.5  2.0  1.5  1.0
1529                                  */
1530                                 if (((cas_bit & 0x40) == 0x40) && (cas_index < 3) &&
1531                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1532                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1533                                                                     cycle_time_ns_x_100[cas_index]);
1534                                         cas_index++;
1535                                 } else {
1536                                         if (cas_index != 0)
1537                                                 cas_index++;
1538                                         cas_4_0_available = false;
1539                                 }
1540
1541                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1542                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1543                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1544                                                                     cycle_time_ns_x_100[cas_index]);
1545                                         cas_index++;
1546                                 } else {
1547                                         if (cas_index != 0)
1548                                                 cas_index++;
1549                                         cas_3_0_available = false;
1550                                 }
1551
1552                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1553                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1554                                         max_2_5_tcyc_ns_x_100 = max(max_2_5_tcyc_ns_x_100,
1555                                                                     cycle_time_ns_x_100[cas_index]);
1556                                         cas_index++;
1557                                 } else {
1558                                         if (cas_index != 0)
1559                                                 cas_index++;
1560                                         cas_2_5_available = false;
1561                                 }
1562
1563                                 if (((cas_bit & 0x04) == 0x04) && (cas_index < 3) &&
1564                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1565                                         max_2_0_tcyc_ns_x_100 = max(max_2_0_tcyc_ns_x_100,
1566                                                                     cycle_time_ns_x_100[cas_index]);
1567                                         cas_index++;
1568                                 } else {
1569                                         if (cas_index != 0)
1570                                                 cas_index++;
1571                                         cas_2_0_available = false;
1572                                 }
1573                         } else {
1574                                 /*
1575                                  * DDR2 devices use the following bitmask for CAS latency:
1576                                  *  Bit   7    6    5    4    3    2    1    0
1577                                  *       TBD  6.0  5.0  4.0  3.0  2.0  TBD  TBD
1578                                  */
1579                                 if (((cas_bit & 0x20) == 0x20) && (cas_index < 3) &&
1580                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1581                                         max_5_0_tcyc_ns_x_100 = max(max_5_0_tcyc_ns_x_100,
1582                                                                     cycle_time_ns_x_100[cas_index]);
1583                                         cas_index++;
1584                                 } else {
1585                                         if (cas_index != 0)
1586                                                 cas_index++;
1587                                         cas_5_0_available = false;
1588                                 }
1589
1590                                 if (((cas_bit & 0x10) == 0x10) && (cas_index < 3) &&
1591                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1592                                         max_4_0_tcyc_ns_x_100 = max(max_4_0_tcyc_ns_x_100,
1593                                                                     cycle_time_ns_x_100[cas_index]);
1594                                         cas_index++;
1595                                 } else {
1596                                         if (cas_index != 0)
1597                                                 cas_index++;
1598                                         cas_4_0_available = false;
1599                                 }
1600
1601                                 if (((cas_bit & 0x08) == 0x08) && (cas_index < 3) &&
1602                                     (cycle_time_ns_x_100[cas_index] != 0)) {
1603                                         max_3_0_tcyc_ns_x_100 = max(max_3_0_tcyc_ns_x_100,
1604                                                                     cycle_time_ns_x_100[cas_index]);
1605                                         cas_index++;
1606                                 } else {
1607                                         if (cas_index != 0)
1608                                                 cas_index++;
1609                                         cas_3_0_available = false;
1610                                 }
1611                         }
1612                 }
1613         }
1614
1615         /*------------------------------------------------------------------
1616          * Set the SDRAM mode, SDRAM_MMODE
1617          *-----------------------------------------------------------------*/
1618         mfsdram(SDRAM_MMODE, mmode);
1619         mmode = mmode & ~(SDRAM_MMODE_WR_MASK | SDRAM_MMODE_DCL_MASK);
1620
1621         /* add 10 here because of rounding problems */
1622         cycle_2_0_clk = MULDIV64(ONE_BILLION, 100, max_2_0_tcyc_ns_x_100) + 10;
1623         cycle_2_5_clk = MULDIV64(ONE_BILLION, 100, max_2_5_tcyc_ns_x_100) + 10;
1624         cycle_3_0_clk = MULDIV64(ONE_BILLION, 100, max_3_0_tcyc_ns_x_100) + 10;
1625         cycle_4_0_clk = MULDIV64(ONE_BILLION, 100, max_4_0_tcyc_ns_x_100) + 10;
1626         cycle_5_0_clk = MULDIV64(ONE_BILLION, 100, max_5_0_tcyc_ns_x_100) + 10;
1627         debug("cycle_3_0_clk=%lu\n", cycle_3_0_clk);
1628         debug("cycle_4_0_clk=%lu\n", cycle_4_0_clk);
1629         debug("cycle_5_0_clk=%lu\n", cycle_5_0_clk);
1630
1631         if (sdram_ddr1 == true) { /* DDR1 */
1632                 if ((cas_2_0_available == true) &&
1633                         (sdram_freq <= cycle_2_0_clk)) {
1634                         mmode |= SDRAM_MMODE_DCL_DDR1_2_0_CLK;
1635                         *selected_cas = DDR_CAS_2;
1636                 } else if ((cas_2_5_available == true) &&
1637                         (sdram_freq <= cycle_2_5_clk)) {
1638                         mmode |= SDRAM_MMODE_DCL_DDR1_2_5_CLK;
1639                         *selected_cas = DDR_CAS_2_5;
1640                 } else if ((cas_3_0_available == true) &&
1641                         (sdram_freq <= cycle_3_0_clk)) {
1642                         mmode |= SDRAM_MMODE_DCL_DDR1_3_0_CLK;
1643                         *selected_cas = DDR_CAS_3;
1644                 } else {
1645                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1646                         printf("Only DIMMs DDR1 with CAS latencies of 2.0, 2.5, and 3.0 are supported.\n");
1647                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n\n");
1648                         spd_ddr_init_hang ();
1649                 }
1650         } else { /* DDR2 */
1651                 debug("cas_3_0_available=%d\n", cas_3_0_available);
1652                 debug("cas_4_0_available=%d\n", cas_4_0_available);
1653                 debug("cas_5_0_available=%d\n", cas_5_0_available);
1654                 if ((cas_3_0_available == true) &&
1655                         (sdram_freq <= cycle_3_0_clk)) {
1656                         mmode |= SDRAM_MMODE_DCL_DDR2_3_0_CLK;
1657                         *selected_cas = DDR_CAS_3;
1658                 } else if ((cas_4_0_available == true) &&
1659                         (sdram_freq <= cycle_4_0_clk)) {
1660                         mmode |= SDRAM_MMODE_DCL_DDR2_4_0_CLK;
1661                         *selected_cas = DDR_CAS_4;
1662                 } else if ((cas_5_0_available == true) &&
1663                         (sdram_freq <= cycle_5_0_clk)) {
1664                         mmode |= SDRAM_MMODE_DCL_DDR2_5_0_CLK;
1665                         *selected_cas = DDR_CAS_5;
1666                 } else {
1667                         printf("ERROR: Cannot find a supported CAS latency with the installed DIMMs.\n");
1668                         printf("Only DIMMs DDR2 with CAS latencies of 3.0, 4.0, and 5.0 are supported.\n");
1669                         printf("Make sure the PLB speed is within the supported range of the DIMMs.\n");
1670                         printf("cas3=%d cas4=%d cas5=%d\n",
1671                                cas_3_0_available, cas_4_0_available, cas_5_0_available);
1672                         printf("sdram_freq=%lu cycle3=%lu cycle4=%lu cycle5=%lu\n\n",
1673                                sdram_freq, cycle_3_0_clk, cycle_4_0_clk, cycle_5_0_clk);
1674                         spd_ddr_init_hang ();
1675                 }
1676         }
1677
1678         if (sdram_ddr1 == true)
1679                 mmode |= SDRAM_MMODE_WR_DDR1;
1680         else {
1681
1682                 /* loop through all the DIMM slots on the board */
1683                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1684                         /* If a dimm is installed in a particular slot ... */
1685                         if (dimm_populated[dimm_num] != SDRAM_NONE)
1686                                 t_wr_ns = max(t_wr_ns,
1687                                               spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1688                 }
1689
1690                 /*
1691                  * convert from nanoseconds to ddr clocks
1692                  * round up if necessary
1693                  */
1694                 t_wr_clk = MULDIV64(sdram_freq, t_wr_ns, ONE_BILLION);
1695                 ddr_check = MULDIV64(ONE_BILLION, t_wr_clk, t_wr_ns);
1696                 if (sdram_freq != ddr_check)
1697                         t_wr_clk++;
1698
1699                 switch (t_wr_clk) {
1700                 case 0:
1701                 case 1:
1702                 case 2:
1703                 case 3:
1704                         mmode |= SDRAM_MMODE_WR_DDR2_3_CYC;
1705                         break;
1706                 case 4:
1707                         mmode |= SDRAM_MMODE_WR_DDR2_4_CYC;
1708                         break;
1709                 case 5:
1710                         mmode |= SDRAM_MMODE_WR_DDR2_5_CYC;
1711                         break;
1712                 default:
1713                         mmode |= SDRAM_MMODE_WR_DDR2_6_CYC;
1714                         break;
1715                 }
1716                 *write_recovery = t_wr_clk;
1717         }
1718
1719         debug("CAS latency = %d\n", *selected_cas);
1720         debug("Write recovery = %d\n", *write_recovery);
1721
1722         mtsdram(SDRAM_MMODE, mmode);
1723 }
1724
1725 /*-----------------------------------------------------------------------------+
1726  * program_rtr.
1727  *-----------------------------------------------------------------------------*/
1728 static void program_rtr(unsigned long *dimm_populated,
1729                         unsigned char *iic0_dimm_addr,
1730                         unsigned long num_dimm_banks)
1731 {
1732         PPC4xx_SYS_INFO board_cfg;
1733         unsigned long max_refresh_rate;
1734         unsigned long dimm_num;
1735         unsigned long refresh_rate_type;
1736         unsigned long refresh_rate;
1737         unsigned long rint;
1738         unsigned long sdram_freq;
1739         unsigned long sdr_ddrpll;
1740         unsigned long val;
1741
1742         /*------------------------------------------------------------------
1743          * Get the board configuration info.
1744          *-----------------------------------------------------------------*/
1745         get_sys_info(&board_cfg);
1746
1747         /*------------------------------------------------------------------
1748          * Set the SDRAM Refresh Timing Register, SDRAM_RTR
1749          *-----------------------------------------------------------------*/
1750         mfsdr(SDR0_DDR0, sdr_ddrpll);
1751         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1752
1753         max_refresh_rate = 0;
1754         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1755                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1756
1757                         refresh_rate_type = spd_read(iic0_dimm_addr[dimm_num], 12);
1758                         refresh_rate_type &= 0x7F;
1759                         switch (refresh_rate_type) {
1760                         case 0:
1761                                 refresh_rate =  15625;
1762                                 break;
1763                         case 1:
1764                                 refresh_rate =   3906;
1765                                 break;
1766                         case 2:
1767                                 refresh_rate =   7812;
1768                                 break;
1769                         case 3:
1770                                 refresh_rate =  31250;
1771                                 break;
1772                         case 4:
1773                                 refresh_rate =  62500;
1774                                 break;
1775                         case 5:
1776                                 refresh_rate = 125000;
1777                                 break;
1778                         default:
1779                                 refresh_rate = 0;
1780                                 printf("ERROR: DIMM %d unsupported refresh rate/type.\n",
1781                                        (unsigned int)dimm_num);
1782                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
1783                                 spd_ddr_init_hang ();
1784                                 break;
1785                         }
1786
1787                         max_refresh_rate = max(max_refresh_rate, refresh_rate);
1788                 }
1789         }
1790
1791         rint = MULDIV64(sdram_freq, max_refresh_rate, ONE_BILLION);
1792         mfsdram(SDRAM_RTR, val);
1793         mtsdram(SDRAM_RTR, (val & ~SDRAM_RTR_RINT_MASK) |
1794                 (SDRAM_RTR_RINT_ENCODE(rint)));
1795 }
1796
1797 /*------------------------------------------------------------------
1798  * This routine programs the SDRAM_TRx registers.
1799  *-----------------------------------------------------------------*/
1800 static void program_tr(unsigned long *dimm_populated,
1801                        unsigned char *iic0_dimm_addr,
1802                        unsigned long num_dimm_banks)
1803 {
1804         unsigned long dimm_num;
1805         unsigned long sdram_ddr1;
1806         unsigned long t_rp_ns;
1807         unsigned long t_rcd_ns;
1808         unsigned long t_rrd_ns;
1809         unsigned long t_ras_ns;
1810         unsigned long t_rc_ns;
1811         unsigned long t_rfc_ns;
1812         unsigned long t_wpc_ns;
1813         unsigned long t_wtr_ns;
1814         unsigned long t_rpc_ns;
1815         unsigned long t_rp_clk;
1816         unsigned long t_rcd_clk;
1817         unsigned long t_rrd_clk;
1818         unsigned long t_ras_clk;
1819         unsigned long t_rc_clk;
1820         unsigned long t_rfc_clk;
1821         unsigned long t_wpc_clk;
1822         unsigned long t_wtr_clk;
1823         unsigned long t_rpc_clk;
1824         unsigned long sdtr1, sdtr2, sdtr3;
1825         unsigned long ddr_check;
1826         unsigned long sdram_freq;
1827         unsigned long sdr_ddrpll;
1828
1829         PPC4xx_SYS_INFO board_cfg;
1830
1831         /*------------------------------------------------------------------
1832          * Get the board configuration info.
1833          *-----------------------------------------------------------------*/
1834         get_sys_info(&board_cfg);
1835
1836         mfsdr(SDR0_DDR0, sdr_ddrpll);
1837         sdram_freq = ((board_cfg.freqPLB) * SDR0_DDR0_DDRM_DECODE(sdr_ddrpll));
1838
1839         /*------------------------------------------------------------------
1840          * Handle the timing.  We need to find the worst case timing of all
1841          * the dimm modules installed.
1842          *-----------------------------------------------------------------*/
1843         t_rp_ns = 0;
1844         t_rrd_ns = 0;
1845         t_rcd_ns = 0;
1846         t_ras_ns = 0;
1847         t_rc_ns = 0;
1848         t_rfc_ns = 0;
1849         t_wpc_ns = 0;
1850         t_wtr_ns = 0;
1851         t_rpc_ns = 0;
1852         sdram_ddr1 = true;
1853
1854         /* loop through all the DIMM slots on the board */
1855         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1856                 /* If a dimm is installed in a particular slot ... */
1857                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
1858                         if (dimm_populated[dimm_num] == SDRAM_DDR2)
1859                                 sdram_ddr1 = true;
1860                         else
1861                                 sdram_ddr1 = false;
1862
1863                         t_rcd_ns = max(t_rcd_ns, spd_read(iic0_dimm_addr[dimm_num], 29) >> 2);
1864                         t_rrd_ns = max(t_rrd_ns, spd_read(iic0_dimm_addr[dimm_num], 28) >> 2);
1865                         t_rp_ns  = max(t_rp_ns,  spd_read(iic0_dimm_addr[dimm_num], 27) >> 2);
1866                         t_ras_ns = max(t_ras_ns, spd_read(iic0_dimm_addr[dimm_num], 30));
1867                         t_rc_ns  = max(t_rc_ns,  spd_read(iic0_dimm_addr[dimm_num], 41));
1868                         t_rfc_ns = max(t_rfc_ns, spd_read(iic0_dimm_addr[dimm_num], 42));
1869                 }
1870         }
1871
1872         /*------------------------------------------------------------------
1873          * Set the SDRAM Timing Reg 1, SDRAM_TR1
1874          *-----------------------------------------------------------------*/
1875         mfsdram(SDRAM_SDTR1, sdtr1);
1876         sdtr1 &= ~(SDRAM_SDTR1_LDOF_MASK | SDRAM_SDTR1_RTW_MASK |
1877                    SDRAM_SDTR1_WTWO_MASK | SDRAM_SDTR1_RTRO_MASK);
1878
1879         /* default values */
1880         sdtr1 |= SDRAM_SDTR1_LDOF_2_CLK;
1881         sdtr1 |= SDRAM_SDTR1_RTW_2_CLK;
1882
1883         /* normal operations */
1884         sdtr1 |= SDRAM_SDTR1_WTWO_0_CLK;
1885         sdtr1 |= SDRAM_SDTR1_RTRO_1_CLK;
1886
1887         mtsdram(SDRAM_SDTR1, sdtr1);
1888
1889         /*------------------------------------------------------------------
1890          * Set the SDRAM Timing Reg 2, SDRAM_TR2
1891          *-----------------------------------------------------------------*/
1892         mfsdram(SDRAM_SDTR2, sdtr2);
1893         sdtr2 &= ~(SDRAM_SDTR2_RCD_MASK  | SDRAM_SDTR2_WTR_MASK |
1894                    SDRAM_SDTR2_XSNR_MASK | SDRAM_SDTR2_WPC_MASK |
1895                    SDRAM_SDTR2_RPC_MASK  | SDRAM_SDTR2_RP_MASK  |
1896                    SDRAM_SDTR2_RRD_MASK);
1897
1898         /*
1899          * convert t_rcd from nanoseconds to ddr clocks
1900          * round up if necessary
1901          */
1902         t_rcd_clk = MULDIV64(sdram_freq, t_rcd_ns, ONE_BILLION);
1903         ddr_check = MULDIV64(ONE_BILLION, t_rcd_clk, t_rcd_ns);
1904         if (sdram_freq != ddr_check)
1905                 t_rcd_clk++;
1906
1907         switch (t_rcd_clk) {
1908         case 0:
1909         case 1:
1910                 sdtr2 |= SDRAM_SDTR2_RCD_1_CLK;
1911                 break;
1912         case 2:
1913                 sdtr2 |= SDRAM_SDTR2_RCD_2_CLK;
1914                 break;
1915         case 3:
1916                 sdtr2 |= SDRAM_SDTR2_RCD_3_CLK;
1917                 break;
1918         case 4:
1919                 sdtr2 |= SDRAM_SDTR2_RCD_4_CLK;
1920                 break;
1921         default:
1922                 sdtr2 |= SDRAM_SDTR2_RCD_5_CLK;
1923                 break;
1924         }
1925
1926         if (sdram_ddr1 == true) { /* DDR1 */
1927                 if (sdram_freq < 200000000) {
1928                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1929                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1930                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1931                 } else {
1932                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1933                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1934                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
1935                 }
1936         } else { /* DDR2 */
1937                 /* loop through all the DIMM slots on the board */
1938                 for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
1939                         /* If a dimm is installed in a particular slot ... */
1940                         if (dimm_populated[dimm_num] != SDRAM_NONE) {
1941                                 t_wpc_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 36) >> 2);
1942                                 t_wtr_ns = max(t_wtr_ns, spd_read(iic0_dimm_addr[dimm_num], 37) >> 2);
1943                                 t_rpc_ns = max(t_rpc_ns, spd_read(iic0_dimm_addr[dimm_num], 38) >> 2);
1944                         }
1945                 }
1946
1947                 /*
1948                  * convert from nanoseconds to ddr clocks
1949                  * round up if necessary
1950                  */
1951                 t_wpc_clk = MULDIV64(sdram_freq, t_wpc_ns, ONE_BILLION);
1952                 ddr_check = MULDIV64(ONE_BILLION, t_wpc_clk, t_wpc_ns);
1953                 if (sdram_freq != ddr_check)
1954                         t_wpc_clk++;
1955
1956                 switch (t_wpc_clk) {
1957                 case 0:
1958                 case 1:
1959                 case 2:
1960                         sdtr2 |= SDRAM_SDTR2_WPC_2_CLK;
1961                         break;
1962                 case 3:
1963                         sdtr2 |= SDRAM_SDTR2_WPC_3_CLK;
1964                         break;
1965                 case 4:
1966                         sdtr2 |= SDRAM_SDTR2_WPC_4_CLK;
1967                         break;
1968                 case 5:
1969                         sdtr2 |= SDRAM_SDTR2_WPC_5_CLK;
1970                         break;
1971                 default:
1972                         sdtr2 |= SDRAM_SDTR2_WPC_6_CLK;
1973                         break;
1974                 }
1975
1976                 /*
1977                  * convert from nanoseconds to ddr clocks
1978                  * round up if necessary
1979                  */
1980                 t_wtr_clk = MULDIV64(sdram_freq, t_wtr_ns, ONE_BILLION);
1981                 ddr_check = MULDIV64(ONE_BILLION, t_wtr_clk, t_wtr_ns);
1982                 if (sdram_freq != ddr_check)
1983                         t_wtr_clk++;
1984
1985                 switch (t_wtr_clk) {
1986                 case 0:
1987                 case 1:
1988                         sdtr2 |= SDRAM_SDTR2_WTR_1_CLK;
1989                         break;
1990                 case 2:
1991                         sdtr2 |= SDRAM_SDTR2_WTR_2_CLK;
1992                         break;
1993                 case 3:
1994                         sdtr2 |= SDRAM_SDTR2_WTR_3_CLK;
1995                         break;
1996                 default:
1997                         sdtr2 |= SDRAM_SDTR2_WTR_4_CLK;
1998                         break;
1999                 }
2000
2001                 /*
2002                  * convert from nanoseconds to ddr clocks
2003                  * round up if necessary
2004                  */
2005                 t_rpc_clk = MULDIV64(sdram_freq, t_rpc_ns, ONE_BILLION);
2006                 ddr_check = MULDIV64(ONE_BILLION, t_rpc_clk, t_rpc_ns);
2007                 if (sdram_freq != ddr_check)
2008                         t_rpc_clk++;
2009
2010                 switch (t_rpc_clk) {
2011                 case 0:
2012                 case 1:
2013                 case 2:
2014                         sdtr2 |= SDRAM_SDTR2_RPC_2_CLK;
2015                         break;
2016                 case 3:
2017                         sdtr2 |= SDRAM_SDTR2_RPC_3_CLK;
2018                         break;
2019                 default:
2020                         sdtr2 |= SDRAM_SDTR2_RPC_4_CLK;
2021                         break;
2022                 }
2023         }
2024
2025         /* default value */
2026         sdtr2 |= SDRAM_SDTR2_XSNR_16_CLK;
2027
2028         /*
2029          * convert t_rrd from nanoseconds to ddr clocks
2030          * round up if necessary
2031          */
2032         t_rrd_clk = MULDIV64(sdram_freq, t_rrd_ns, ONE_BILLION);
2033         ddr_check = MULDIV64(ONE_BILLION, t_rrd_clk, t_rrd_ns);
2034         if (sdram_freq != ddr_check)
2035                 t_rrd_clk++;
2036
2037         if (t_rrd_clk == 3)
2038                 sdtr2 |= SDRAM_SDTR2_RRD_3_CLK;
2039         else
2040                 sdtr2 |= SDRAM_SDTR2_RRD_2_CLK;
2041
2042         /*
2043          * convert t_rp from nanoseconds to ddr clocks
2044          * round up if necessary
2045          */
2046         t_rp_clk = MULDIV64(sdram_freq, t_rp_ns, ONE_BILLION);
2047         ddr_check = MULDIV64(ONE_BILLION, t_rp_clk, t_rp_ns);
2048         if (sdram_freq != ddr_check)
2049                 t_rp_clk++;
2050
2051         switch (t_rp_clk) {
2052         case 0:
2053         case 1:
2054         case 2:
2055         case 3:
2056                 sdtr2 |= SDRAM_SDTR2_RP_3_CLK;
2057                 break;
2058         case 4:
2059                 sdtr2 |= SDRAM_SDTR2_RP_4_CLK;
2060                 break;
2061         case 5:
2062                 sdtr2 |= SDRAM_SDTR2_RP_5_CLK;
2063                 break;
2064         case 6:
2065                 sdtr2 |= SDRAM_SDTR2_RP_6_CLK;
2066                 break;
2067         default:
2068                 sdtr2 |= SDRAM_SDTR2_RP_7_CLK;
2069                 break;
2070         }
2071
2072         mtsdram(SDRAM_SDTR2, sdtr2);
2073
2074         /*------------------------------------------------------------------
2075          * Set the SDRAM Timing Reg 3, SDRAM_TR3
2076          *-----------------------------------------------------------------*/
2077         mfsdram(SDRAM_SDTR3, sdtr3);
2078         sdtr3 &= ~(SDRAM_SDTR3_RAS_MASK  | SDRAM_SDTR3_RC_MASK |
2079                    SDRAM_SDTR3_XCS_MASK | SDRAM_SDTR3_RFC_MASK);
2080
2081         /*
2082          * convert t_ras from nanoseconds to ddr clocks
2083          * round up if necessary
2084          */
2085         t_ras_clk = MULDIV64(sdram_freq, t_ras_ns, ONE_BILLION);
2086         ddr_check = MULDIV64(ONE_BILLION, t_ras_clk, t_ras_ns);
2087         if (sdram_freq != ddr_check)
2088                 t_ras_clk++;
2089
2090         sdtr3 |= SDRAM_SDTR3_RAS_ENCODE(t_ras_clk);
2091
2092         /*
2093          * convert t_rc from nanoseconds to ddr clocks
2094          * round up if necessary
2095          */
2096         t_rc_clk = MULDIV64(sdram_freq, t_rc_ns, ONE_BILLION);
2097         ddr_check = MULDIV64(ONE_BILLION, t_rc_clk, t_rc_ns);
2098         if (sdram_freq != ddr_check)
2099                 t_rc_clk++;
2100
2101         sdtr3 |= SDRAM_SDTR3_RC_ENCODE(t_rc_clk);
2102
2103         /* default xcs value */
2104         sdtr3 |= SDRAM_SDTR3_XCS;
2105
2106         /*
2107          * convert t_rfc from nanoseconds to ddr clocks
2108          * round up if necessary
2109          */
2110         t_rfc_clk = MULDIV64(sdram_freq, t_rfc_ns, ONE_BILLION);
2111         ddr_check = MULDIV64(ONE_BILLION, t_rfc_clk, t_rfc_ns);
2112         if (sdram_freq != ddr_check)
2113                 t_rfc_clk++;
2114
2115         sdtr3 |= SDRAM_SDTR3_RFC_ENCODE(t_rfc_clk);
2116
2117         mtsdram(SDRAM_SDTR3, sdtr3);
2118 }
2119
2120 /*-----------------------------------------------------------------------------+
2121  * program_bxcf.
2122  *-----------------------------------------------------------------------------*/
2123 static void program_bxcf(unsigned long *dimm_populated,
2124                          unsigned char *iic0_dimm_addr,
2125                          unsigned long num_dimm_banks)
2126 {
2127         unsigned long dimm_num;
2128         unsigned long num_col_addr;
2129         unsigned long num_ranks;
2130         unsigned long num_banks;
2131         unsigned long mode;
2132         unsigned long ind_rank;
2133         unsigned long ind;
2134         unsigned long ind_bank;
2135         unsigned long bank_0_populated;
2136
2137         /*------------------------------------------------------------------
2138          * Set the BxCF regs.  First, wipe out the bank config registers.
2139          *-----------------------------------------------------------------*/
2140         mtsdram(SDRAM_MB0CF, 0x00000000);
2141         mtsdram(SDRAM_MB1CF, 0x00000000);
2142         mtsdram(SDRAM_MB2CF, 0x00000000);
2143         mtsdram(SDRAM_MB3CF, 0x00000000);
2144
2145         mode = SDRAM_BXCF_M_BE_ENABLE;
2146
2147         bank_0_populated = 0;
2148
2149         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2150                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2151                         num_col_addr = spd_read(iic0_dimm_addr[dimm_num], 4);
2152                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2153                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2154                                 num_ranks = (num_ranks & 0x0F) +1;
2155                         else
2156                                 num_ranks = num_ranks & 0x0F;
2157
2158                         num_banks = spd_read(iic0_dimm_addr[dimm_num], 17);
2159
2160                         for (ind_bank = 0; ind_bank < 2; ind_bank++) {
2161                                 if (num_banks == 4)
2162                                         ind = 0;
2163                                 else
2164                                         ind = 5 << 8;
2165                                 switch (num_col_addr) {
2166                                 case 0x08:
2167                                         mode |= (SDRAM_BXCF_M_AM_0 + ind);
2168                                         break;
2169                                 case 0x09:
2170                                         mode |= (SDRAM_BXCF_M_AM_1 + ind);
2171                                         break;
2172                                 case 0x0A:
2173                                         mode |= (SDRAM_BXCF_M_AM_2 + ind);
2174                                         break;
2175                                 case 0x0B:
2176                                         mode |= (SDRAM_BXCF_M_AM_3 + ind);
2177                                         break;
2178                                 case 0x0C:
2179                                         mode |= (SDRAM_BXCF_M_AM_4 + ind);
2180                                         break;
2181                                 default:
2182                                         printf("DDR-SDRAM: DIMM %d BxCF configuration.\n",
2183                                                (unsigned int)dimm_num);
2184                                         printf("ERROR: Unsupported value for number of "
2185                                                "column addresses: %d.\n", (unsigned int)num_col_addr);
2186                                         printf("Replace the DIMM module with a supported DIMM.\n\n");
2187                                         spd_ddr_init_hang ();
2188                                 }
2189                         }
2190
2191                         if ((dimm_populated[dimm_num] != SDRAM_NONE)&& (dimm_num ==1))
2192                                 bank_0_populated = 1;
2193
2194                         for (ind_rank = 0; ind_rank < num_ranks; ind_rank++) {
2195                                 mtsdram(SDRAM_MB0CF +
2196                                         ((dimm_num + bank_0_populated + ind_rank) << 2),
2197                                         mode);
2198                         }
2199                 }
2200         }
2201 }
2202
2203 /*------------------------------------------------------------------
2204  * program memory queue.
2205  *-----------------------------------------------------------------*/
2206 static void program_memory_queue(unsigned long *dimm_populated,
2207                                  unsigned char *iic0_dimm_addr,
2208                                  unsigned long num_dimm_banks)
2209 {
2210         unsigned long dimm_num;
2211         phys_size_t rank_base_addr;
2212         unsigned long rank_reg;
2213         phys_size_t rank_size_bytes;
2214         unsigned long rank_size_id;
2215         unsigned long num_ranks;
2216         unsigned long baseadd_size;
2217         unsigned long i;
2218         unsigned long bank_0_populated = 0;
2219         phys_size_t total_size = 0;
2220
2221         /*------------------------------------------------------------------
2222          * Reset the rank_base_address.
2223          *-----------------------------------------------------------------*/
2224         rank_reg   = SDRAM_R0BAS;
2225
2226         rank_base_addr = 0x00000000;
2227
2228         for (dimm_num = 0; dimm_num < num_dimm_banks; dimm_num++) {
2229                 if (dimm_populated[dimm_num] != SDRAM_NONE) {
2230                         num_ranks = spd_read(iic0_dimm_addr[dimm_num], 5);
2231                         if ((spd_read(iic0_dimm_addr[dimm_num], 2)) == 0x08)
2232                                 num_ranks = (num_ranks & 0x0F) + 1;
2233                         else
2234                                 num_ranks = num_ranks & 0x0F;
2235
2236                         rank_size_id = spd_read(iic0_dimm_addr[dimm_num], 31);
2237
2238                         /*------------------------------------------------------------------
2239                          * Set the sizes
2240                          *-----------------------------------------------------------------*/
2241                         baseadd_size = 0;
2242                         switch (rank_size_id) {
2243                         case 0x01:
2244                                 baseadd_size |= SDRAM_RXBAS_SDSZ_1024;
2245                                 total_size = 1024;
2246                                 break;
2247                         case 0x02:
2248                                 baseadd_size |= SDRAM_RXBAS_SDSZ_2048;
2249                                 total_size = 2048;
2250                                 break;
2251                         case 0x04:
2252                                 baseadd_size |= SDRAM_RXBAS_SDSZ_4096;
2253                                 total_size = 4096;
2254                                 break;
2255                         case 0x08:
2256                                 baseadd_size |= SDRAM_RXBAS_SDSZ_32;
2257                                 total_size = 32;
2258                                 break;
2259                         case 0x10:
2260                                 baseadd_size |= SDRAM_RXBAS_SDSZ_64;
2261                                 total_size = 64;
2262                                 break;
2263                         case 0x20:
2264                                 baseadd_size |= SDRAM_RXBAS_SDSZ_128;
2265                                 total_size = 128;
2266                                 break;
2267                         case 0x40:
2268                                 baseadd_size |= SDRAM_RXBAS_SDSZ_256;
2269                                 total_size = 256;
2270                                 break;
2271                         case 0x80:
2272                                 baseadd_size |= SDRAM_RXBAS_SDSZ_512;
2273                                 total_size = 512;
2274                                 break;
2275                         default:
2276                                 printf("DDR-SDRAM: DIMM %d memory queue configuration.\n",
2277                                        (unsigned int)dimm_num);
2278                                 printf("ERROR: Unsupported value for the banksize: %d.\n",
2279                                        (unsigned int)rank_size_id);
2280                                 printf("Replace the DIMM module with a supported DIMM.\n\n");
2281                                 spd_ddr_init_hang ();
2282                         }
2283                         rank_size_bytes = total_size << 20;
2284
2285                         if ((dimm_populated[dimm_num] != SDRAM_NONE) && (dimm_num == 1))
2286                                 bank_0_populated = 1;
2287
2288                         for (i = 0; i < num_ranks; i++) {
2289                                 mtdcr_any(rank_reg+i+dimm_num+bank_0_populated,
2290                                           (SDRAM_RXBAS_SDBA_ENCODE(rank_base_addr) |
2291                                            baseadd_size));
2292                                 rank_base_addr += rank_size_bytes;
2293                         }
2294                 }
2295         }
2296
2297 #if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
2298     defined(CONFIG_460EX) || defined(CONFIG_460GT) || \
2299     defined(CONFIG_460SX)
2300         /*
2301          * Enable high bandwidth access
2302          * This is currently not used, but with this setup
2303          * it is possible to use it later on in e.g. the Linux
2304          * EMAC driver for performance gain.
2305          */
2306         mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */
2307         mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */
2308
2309         /*
2310          * Set optimal value for Memory Queue HB/LL Configuration registers
2311          */
2312         mtdcr(SDRAM_CONF1HB, (mfdcr(SDRAM_CONF1HB) & ~SDRAM_CONF1HB_MASK) |
2313               SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE |
2314               SDRAM_CONF1HB_RPLM | SDRAM_CONF1HB_WRCL);
2315         mtdcr(SDRAM_CONF1LL, (mfdcr(SDRAM_CONF1LL) & ~SDRAM_CONF1LL_MASK) |
2316               SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE |
2317               SDRAM_CONF1LL_RPLM);
2318         mtdcr(SDRAM_CONFPATHB, mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN);
2319 #endif
2320 }
2321
2322 #ifdef CONFIG_DDR_ECC
2323 /*-----------------------------------------------------------------------------+
2324  * program_ecc.
2325  *-----------------------------------------------------------------------------*/
2326 static void program_ecc(unsigned long *dimm_populated,
2327                         unsigned char *iic0_dimm_addr,
2328                         unsigned long num_dimm_banks,
2329                         unsigned long tlb_word2_i_value)
2330 {
2331         unsigned long dimm_num;
2332         unsigned long ecc;
2333
2334         ecc = 0;
2335         /* loop through all the DIMM slots on the board */
2336         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2337                 /* If a dimm is installed in a particular slot ... */
2338                 if (dimm_populated[dimm_num] != SDRAM_NONE)
2339                         ecc = max(ecc, spd_read(iic0_dimm_addr[dimm_num], 11));
2340         }
2341         if (ecc == 0)
2342                 return;
2343
2344         do_program_ecc(tlb_word2_i_value);
2345 }
2346 #endif
2347
2348 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2349 /*-----------------------------------------------------------------------------+
2350  * program_DQS_calibration.
2351  *-----------------------------------------------------------------------------*/
2352 static void program_DQS_calibration(unsigned long *dimm_populated,
2353                                     unsigned char *iic0_dimm_addr,
2354                                     unsigned long num_dimm_banks)
2355 {
2356         unsigned long val;
2357
2358 #ifdef HARD_CODED_DQS /* calibration test with hardvalues */
2359         mtsdram(SDRAM_RQDC, 0x80000037);
2360         mtsdram(SDRAM_RDCC, 0x40000000);
2361         mtsdram(SDRAM_RFDC, 0x000001DF);
2362
2363         test();
2364 #else
2365         /*------------------------------------------------------------------
2366          * Program RDCC register
2367          * Read sample cycle auto-update enable
2368          *-----------------------------------------------------------------*/
2369
2370         mfsdram(SDRAM_RDCC, val);
2371         mtsdram(SDRAM_RDCC,
2372                 (val & ~(SDRAM_RDCC_RDSS_MASK | SDRAM_RDCC_RSAE_MASK))
2373                 | SDRAM_RDCC_RSAE_ENABLE);
2374
2375         /*------------------------------------------------------------------
2376          * Program RQDC register
2377          * Internal DQS delay mechanism enable
2378          *-----------------------------------------------------------------*/
2379         mtsdram(SDRAM_RQDC, (SDRAM_RQDC_RQDE_ENABLE|SDRAM_RQDC_RQFD_ENCODE(0x38)));
2380
2381         /*------------------------------------------------------------------
2382          * Program RFDC register
2383          * Set Feedback Fractional Oversample
2384          * Auto-detect read sample cycle enable
2385          * Set RFOS to 1/4 of memclk cycle (0x3f)
2386          *-----------------------------------------------------------------*/
2387         mfsdram(SDRAM_RFDC, val);
2388         mtsdram(SDRAM_RFDC,
2389                 (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK |
2390                          SDRAM_RFDC_RFFD_MASK))
2391                 | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) |
2392                    SDRAM_RFDC_RFFD_ENCODE(0)));
2393
2394         DQS_calibration_process();
2395 #endif
2396 }
2397
2398 static int short_mem_test(void)
2399 {
2400         u32 *membase;
2401         u32 bxcr_num;
2402         u32 bxcf;
2403         int i;
2404         int j;
2405         phys_size_t base_addr;
2406         u32 test[NUMMEMTESTS][NUMMEMWORDS] = {
2407                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2408                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2409                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2410                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2411                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2412                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2413                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2414                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2415                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2416                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2417                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2418                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2419                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2420                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2421                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2422                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2423         int l;
2424
2425         for (bxcr_num = 0; bxcr_num < MAXBXCF; bxcr_num++) {
2426                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf);
2427
2428                 /* Banks enabled */
2429                 if ((bxcf & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2430                         /* Bank is enabled */
2431
2432                         /*
2433                          * Only run test on accessable memory (below 2GB)
2434                          */
2435                         base_addr = SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+bxcr_num));
2436                         if (base_addr >= CONFIG_MAX_MEM_MAPPED)
2437                                 continue;
2438
2439                         /*------------------------------------------------------------------
2440                          * Run the short memory test.
2441                          *-----------------------------------------------------------------*/
2442                         membase = (u32 *)(u32)base_addr;
2443
2444                         for (i = 0; i < NUMMEMTESTS; i++) {
2445                                 for (j = 0; j < NUMMEMWORDS; j++) {
2446                                         membase[j] = test[i][j];
2447                                         ppcDcbf((u32)&(membase[j]));
2448                                 }
2449                                 sync();
2450                                 for (l=0; l<NUMLOOPS; l++) {
2451                                         for (j = 0; j < NUMMEMWORDS; j++) {
2452                                                 if (membase[j] != test[i][j]) {
2453                                                         ppcDcbf((u32)&(membase[j]));
2454                                                         return 0;
2455                                                 }
2456                                                 ppcDcbf((u32)&(membase[j]));
2457                                         }
2458                                         sync();
2459                                 }
2460                         }
2461                 }       /* if bank enabled */
2462         }               /* for bxcf_num */
2463
2464         return 1;
2465 }
2466
2467 #ifndef HARD_CODED_DQS
2468 /*-----------------------------------------------------------------------------+
2469  * DQS_calibration_process.
2470  *-----------------------------------------------------------------------------*/
2471 static void DQS_calibration_process(void)
2472 {
2473         unsigned long rfdc_reg;
2474         unsigned long rffd;
2475         unsigned long val;
2476         long rffd_average;
2477         long max_start;
2478         unsigned long dlycal;
2479         unsigned long dly_val;
2480         unsigned long max_pass_length;
2481         unsigned long current_pass_length;
2482         unsigned long current_fail_length;
2483         unsigned long current_start;
2484         long max_end;
2485         unsigned char fail_found;
2486         unsigned char pass_found;
2487 #if !defined(CONFIG_DDR_RQDC_FIXED)
2488         int window_found;
2489         u32 rqdc_reg;
2490         u32 rqfd;
2491         u32 rqfd_start;
2492         u32 rqfd_average;
2493         int loopi = 0;
2494         char str[] = "Auto calibration -";
2495         char slash[] = "\\|/-\\|/-";
2496
2497         /*------------------------------------------------------------------
2498          * Test to determine the best read clock delay tuning bits.
2499          *
2500          * Before the DDR controller can be used, the read clock delay needs to be
2501          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2502          * This value cannot be hardcoded into the program because it changes
2503          * depending on the board's setup and environment.
2504          * To do this, all delay values are tested to see if they
2505          * work or not.  By doing this, you get groups of fails with groups of
2506          * passing values.  The idea is to find the start and end of a passing
2507          * window and take the center of it to use as the read clock delay.
2508          *
2509          * A failure has to be seen first so that when we hit a pass, we know
2510          * that it is truely the start of the window.  If we get passing values
2511          * to start off with, we don't know if we are at the start of the window.
2512          *
2513          * The code assumes that a failure will always be found.
2514          * If a failure is not found, there is no easy way to get the middle
2515          * of the passing window.  I guess we can pretty much pick any value
2516          * but some values will be better than others.  Since the lowest speed
2517          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2518          * from experimentation it is safe to say you will always have a failure.
2519          *-----------------------------------------------------------------*/
2520
2521         /* first fix RQDC[RQFD] to an average of 80 degre phase shift to find RFDC[RFFD] */
2522         rqfd_start = 64; /* test-only: don't know if this is the _best_ start value */
2523
2524         puts(str);
2525
2526 calibration_loop:
2527         mfsdram(SDRAM_RQDC, rqdc_reg);
2528         mtsdram(SDRAM_RQDC, (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2529                 SDRAM_RQDC_RQFD_ENCODE(rqfd_start));
2530 #else /* CONFIG_DDR_RQDC_FIXED */
2531         /*
2532          * On Katmai the complete auto-calibration somehow doesn't seem to
2533          * produce the best results, meaning optimal values for RQFD/RFFD.
2534          * This was discovered by GDA using a high bandwidth scope,
2535          * analyzing the DDR2 signals. GDA provided a fixed value for RQFD,
2536          * so now on Katmai "only" RFFD is auto-calibrated.
2537          */
2538         mtsdram(SDRAM_RQDC, CONFIG_DDR_RQDC_FIXED);
2539 #endif /* CONFIG_DDR_RQDC_FIXED */
2540
2541         max_start = 0;
2542
2543         max_pass_length = 0;
2544         max_start = 0;
2545         max_end = 0;
2546         current_pass_length = 0;
2547         current_fail_length = 0;
2548         current_start = 0;
2549         fail_found = false;
2550         pass_found = false;
2551
2552         /*
2553          * get the delay line calibration register value
2554          */
2555         mfsdram(SDRAM_DLCR, dlycal);
2556         dly_val = SDRAM_DLYCAL_DLCV_DECODE(dlycal) << 2;
2557
2558         for (rffd = 0; rffd <= SDRAM_RFDC_RFFD_MAX; rffd++) {
2559                 mfsdram(SDRAM_RFDC, rfdc_reg);
2560                 rfdc_reg &= ~(SDRAM_RFDC_RFFD_MASK);
2561
2562                 /*------------------------------------------------------------------
2563                  * Set the timing reg for the test.
2564                  *-----------------------------------------------------------------*/
2565                 mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd));
2566
2567                 /*------------------------------------------------------------------
2568                  * See if the rffd value passed.
2569                  *-----------------------------------------------------------------*/
2570                 if (short_mem_test()) {
2571                         if (fail_found == true) {
2572                                 pass_found = true;
2573                                 if (current_pass_length == 0)
2574                                         current_start = rffd;
2575
2576                                 current_fail_length = 0;
2577                                 current_pass_length++;
2578
2579                                 if (current_pass_length > max_pass_length) {
2580                                         max_pass_length = current_pass_length;
2581                                         max_start = current_start;
2582                                         max_end = rffd;
2583                                 }
2584                         }
2585                 } else {
2586                         current_pass_length = 0;
2587                         current_fail_length++;
2588
2589                         if (current_fail_length >= (dly_val >> 2)) {
2590                                 if (fail_found == false)
2591                                         fail_found = true;
2592                                 else if (pass_found == true)
2593                                         break;
2594                         }
2595                 }
2596         }               /* for rffd */
2597
2598         /*------------------------------------------------------------------
2599          * Set the average RFFD value
2600          *-----------------------------------------------------------------*/
2601         rffd_average = ((max_start + max_end) >> 1);
2602
2603         if (rffd_average < 0)
2604                 rffd_average = 0;
2605
2606         if (rffd_average > SDRAM_RFDC_RFFD_MAX)
2607                 rffd_average = SDRAM_RFDC_RFFD_MAX;
2608         /* now fix RFDC[RFFD] found and find RQDC[RQFD] */
2609         mtsdram(SDRAM_RFDC, rfdc_reg | SDRAM_RFDC_RFFD_ENCODE(rffd_average));
2610
2611 #if !defined(CONFIG_DDR_RQDC_FIXED)
2612         max_pass_length = 0;
2613         max_start = 0;
2614         max_end = 0;
2615         current_pass_length = 0;
2616         current_fail_length = 0;
2617         current_start = 0;
2618         window_found = false;
2619         fail_found = false;
2620         pass_found = false;
2621
2622         for (rqfd = 0; rqfd <= SDRAM_RQDC_RQFD_MAX; rqfd++) {
2623                 mfsdram(SDRAM_RQDC, rqdc_reg);
2624                 rqdc_reg &= ~(SDRAM_RQDC_RQFD_MASK);
2625
2626                 /*------------------------------------------------------------------
2627                  * Set the timing reg for the test.
2628                  *-----------------------------------------------------------------*/
2629                 mtsdram(SDRAM_RQDC, rqdc_reg | SDRAM_RQDC_RQFD_ENCODE(rqfd));
2630
2631                 /*------------------------------------------------------------------
2632                  * See if the rffd value passed.
2633                  *-----------------------------------------------------------------*/
2634                 if (short_mem_test()) {
2635                         if (fail_found == true) {
2636                                 pass_found = true;
2637                                 if (current_pass_length == 0)
2638                                         current_start = rqfd;
2639
2640                                 current_fail_length = 0;
2641                                 current_pass_length++;
2642
2643                                 if (current_pass_length > max_pass_length) {
2644                                         max_pass_length = current_pass_length;
2645                                         max_start = current_start;
2646                                         max_end = rqfd;
2647                                 }
2648                         }
2649                 } else {
2650                         current_pass_length = 0;
2651                         current_fail_length++;
2652
2653                         if (fail_found == false) {
2654                                 fail_found = true;
2655                         } else if (pass_found == true) {
2656                                 window_found = true;
2657                                 break;
2658                         }
2659                 }
2660         }
2661
2662         rqfd_average = ((max_start + max_end) >> 1);
2663
2664         /*------------------------------------------------------------------
2665          * Make sure we found the valid read passing window.  Halt if not
2666          *-----------------------------------------------------------------*/
2667         if (window_found == false) {
2668                 if (rqfd_start < SDRAM_RQDC_RQFD_MAX) {
2669                         putc('\b');
2670                         putc(slash[loopi++ % 8]);
2671
2672                         /* try again from with a different RQFD start value */
2673                         rqfd_start++;
2674                         goto calibration_loop;
2675                 }
2676
2677                 printf("\nERROR: Cannot determine a common read delay for the "
2678                        "DIMM(s) installed.\n");
2679                 debug("%s[%d] ERROR : \n", __FUNCTION__,__LINE__);
2680                 ppc4xx_ibm_ddr2_register_dump();
2681                 spd_ddr_init_hang ();
2682         }
2683
2684         if (rqfd_average < 0)
2685                 rqfd_average = 0;
2686
2687         if (rqfd_average > SDRAM_RQDC_RQFD_MAX)
2688                 rqfd_average = SDRAM_RQDC_RQFD_MAX;
2689
2690         mtsdram(SDRAM_RQDC,
2691                 (rqdc_reg & ~SDRAM_RQDC_RQFD_MASK) |
2692                 SDRAM_RQDC_RQFD_ENCODE(rqfd_average));
2693
2694         blank_string(strlen(str));
2695 #endif /* CONFIG_DDR_RQDC_FIXED */
2696
2697         mfsdram(SDRAM_DLCR, val);
2698         debug("%s[%d] DLCR: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2699         mfsdram(SDRAM_RQDC, val);
2700         debug("%s[%d] RQDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2701         mfsdram(SDRAM_RFDC, val);
2702         debug("%s[%d] RFDC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2703         mfsdram(SDRAM_RDCC, val);
2704         debug("%s[%d] RDCC: 0x%08lX\n", __FUNCTION__, __LINE__, val);
2705 }
2706 #else /* calibration test with hardvalues */
2707 /*-----------------------------------------------------------------------------+
2708  * DQS_calibration_process.
2709  *-----------------------------------------------------------------------------*/
2710 static void test(void)
2711 {
2712         unsigned long dimm_num;
2713         unsigned long ecc_temp;
2714         unsigned long i, j;
2715         unsigned long *membase;
2716         unsigned long bxcf[MAXRANKS];
2717         unsigned long val;
2718         char window_found;
2719         char begin_found[MAXDIMMS];
2720         char end_found[MAXDIMMS];
2721         char search_end[MAXDIMMS];
2722         unsigned long test[NUMMEMTESTS][NUMMEMWORDS] = {
2723                 {0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF,
2724                  0x00000000, 0x00000000, 0xFFFFFFFF, 0xFFFFFFFF},
2725                 {0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000,
2726                  0xFFFFFFFF, 0xFFFFFFFF, 0x00000000, 0x00000000},
2727                 {0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555,
2728                  0xAAAAAAAA, 0xAAAAAAAA, 0x55555555, 0x55555555},
2729                 {0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA,
2730                  0x55555555, 0x55555555, 0xAAAAAAAA, 0xAAAAAAAA},
2731                 {0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A,
2732                  0xA5A5A5A5, 0xA5A5A5A5, 0x5A5A5A5A, 0x5A5A5A5A},
2733                 {0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5,
2734                  0x5A5A5A5A, 0x5A5A5A5A, 0xA5A5A5A5, 0xA5A5A5A5},
2735                 {0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA,
2736                  0xAA55AA55, 0xAA55AA55, 0x55AA55AA, 0x55AA55AA},
2737                 {0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55,
2738                  0x55AA55AA, 0x55AA55AA, 0xAA55AA55, 0xAA55AA55} };
2739
2740         /*------------------------------------------------------------------
2741          * Test to determine the best read clock delay tuning bits.
2742          *
2743          * Before the DDR controller can be used, the read clock delay needs to be
2744          * set.  This is SDRAM_RQDC[RQFD] and SDRAM_RFDC[RFFD].
2745          * This value cannot be hardcoded into the program because it changes
2746          * depending on the board's setup and environment.
2747          * To do this, all delay values are tested to see if they
2748          * work or not.  By doing this, you get groups of fails with groups of
2749          * passing values.  The idea is to find the start and end of a passing
2750          * window and take the center of it to use as the read clock delay.
2751          *
2752          * A failure has to be seen first so that when we hit a pass, we know
2753          * that it is truely the start of the window.  If we get passing values
2754          * to start off with, we don't know if we are at the start of the window.
2755          *
2756          * The code assumes that a failure will always be found.
2757          * If a failure is not found, there is no easy way to get the middle
2758          * of the passing window.  I guess we can pretty much pick any value
2759          * but some values will be better than others.  Since the lowest speed
2760          * we can clock the DDR interface at is 200 MHz (2x 100 MHz PLB speed),
2761          * from experimentation it is safe to say you will always have a failure.
2762          *-----------------------------------------------------------------*/
2763         mfsdram(SDRAM_MCOPT1, ecc_temp);
2764         ecc_temp &= SDRAM_MCOPT1_MCHK_MASK;
2765         mfsdram(SDRAM_MCOPT1, val);
2766         mtsdram(SDRAM_MCOPT1, (val & ~SDRAM_MCOPT1_MCHK_MASK) |
2767                 SDRAM_MCOPT1_MCHK_NON);
2768
2769         window_found = false;
2770         begin_found[0] = false;
2771         end_found[0] = false;
2772         search_end[0] = false;
2773         begin_found[1] = false;
2774         end_found[1] = false;
2775         search_end[1] = false;
2776
2777         for (dimm_num = 0; dimm_num < MAXDIMMS; dimm_num++) {
2778                 mfsdram(SDRAM_MB0CF + (bxcr_num << 2), bxcf[bxcr_num]);
2779
2780                 /* Banks enabled */
2781                 if ((bxcf[dimm_num] & SDRAM_BXCF_M_BE_MASK) == SDRAM_BXCF_M_BE_ENABLE) {
2782
2783                         /* Bank is enabled */
2784                         membase =
2785                                 (unsigned long*)(SDRAM_RXBAS_SDBA_DECODE(mfdcr_any(SDRAM_R0BAS+dimm_num)));
2786
2787                         /*------------------------------------------------------------------
2788                          * Run the short memory test.
2789                          *-----------------------------------------------------------------*/
2790                         for (i = 0; i < NUMMEMTESTS; i++) {
2791                                 for (j = 0; j < NUMMEMWORDS; j++) {
2792                                         membase[j] = test[i][j];
2793                                         ppcDcbf((u32)&(membase[j]));
2794                                 }
2795                                 sync();
2796                                 for (j = 0; j < NUMMEMWORDS; j++) {
2797                                         if (membase[j] != test[i][j]) {
2798                                                 ppcDcbf((u32)&(membase[j]));
2799                                                 break;
2800                                         }
2801                                         ppcDcbf((u32)&(membase[j]));
2802                                 }
2803                                 sync();
2804                                 if (j < NUMMEMWORDS)
2805                                         break;
2806                         }
2807
2808                         /*------------------------------------------------------------------
2809                          * See if the rffd value passed.
2810                          *-----------------------------------------------------------------*/
2811                         if (i < NUMMEMTESTS) {
2812                                 if ((end_found[dimm_num] == false) &&
2813                                     (search_end[dimm_num] == true)) {
2814                                         end_found[dimm_num] = true;
2815                                 }
2816                                 if ((end_found[0] == true) &&
2817                                     (end_found[1] == true))
2818                                         break;
2819                         } else {
2820                                 if (begin_found[dimm_num] == false) {
2821                                         begin_found[dimm_num] = true;
2822                                         search_end[dimm_num] = true;
2823                                 }
2824                         }
2825                 } else {
2826                         begin_found[dimm_num] = true;
2827                         end_found[dimm_num] = true;
2828                 }
2829         }
2830
2831         if ((begin_found[0] == true) && (begin_found[1] == true))
2832                 window_found = true;
2833
2834         /*------------------------------------------------------------------
2835          * Make sure we found the valid read passing window.  Halt if not
2836          *-----------------------------------------------------------------*/
2837         if (window_found == false) {
2838                 printf("ERROR: Cannot determine a common read delay for the "
2839                        "DIMM(s) installed.\n");
2840                 spd_ddr_init_hang ();
2841         }
2842
2843         /*------------------------------------------------------------------
2844          * Restore the ECC variable to what it originally was
2845          *-----------------------------------------------------------------*/
2846         mtsdram(SDRAM_MCOPT1,
2847                 (ppcMfdcr_sdram(SDRAM_MCOPT1) & ~SDRAM_MCOPT1_MCHK_MASK)
2848                 | ecc_temp);
2849 }
2850 #endif /* !HARD_CODED_DQS */
2851 #endif /* !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION) */
2852
2853 #else /* CONFIG_SPD_EEPROM */
2854
2855 /*-----------------------------------------------------------------------------
2856  * Function:    initdram
2857  * Description: Configures the PPC4xx IBM DDR1/DDR2 SDRAM memory controller.
2858  *              The configuration is performed using static, compile-
2859  *              time parameters.
2860  *              Configures the PPC405EX(r) and PPC460EX/GT
2861  *---------------------------------------------------------------------------*/
2862 phys_size_t initdram(int board_type)
2863 {
2864         /*
2865          * Only run this SDRAM init code once. For NAND booting
2866          * targets like Kilauea, we call initdram() early from the
2867          * 4k NAND booting image (CONFIG_NAND_SPL) from nand_boot().
2868          * Later on the NAND U-Boot image runs (CONFIG_NAND_U_BOOT)
2869          * which calls initdram() again. This time the controller
2870          * mustn't be reconfigured again since we're already running
2871          * from SDRAM.
2872          */
2873 #if !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL)
2874         unsigned long val;
2875
2876 #if defined(CONFIG_440)
2877         mtdcr(SDRAM_R0BAS,      CONFIG_SYS_SDRAM_R0BAS);
2878         mtdcr(SDRAM_R1BAS,      CONFIG_SYS_SDRAM_R1BAS);
2879         mtdcr(SDRAM_R2BAS,      CONFIG_SYS_SDRAM_R2BAS);
2880         mtdcr(SDRAM_R3BAS,      CONFIG_SYS_SDRAM_R3BAS);
2881         mtdcr(SDRAM_PLBADDULL,  CONFIG_SYS_SDRAM_PLBADDULL);    /* MQ0_BAUL */
2882         mtdcr(SDRAM_PLBADDUHB,  CONFIG_SYS_SDRAM_PLBADDUHB);    /* MQ0_BAUH */
2883         mtdcr(SDRAM_CONF1LL,    CONFIG_SYS_SDRAM_CONF1LL);
2884         mtdcr(SDRAM_CONF1HB,    CONFIG_SYS_SDRAM_CONF1HB);
2885         mtdcr(SDRAM_CONFPATHB,  CONFIG_SYS_SDRAM_CONFPATHB);
2886 #endif
2887
2888         /* Set Memory Bank Configuration Registers */
2889
2890         mtsdram(SDRAM_MB0CF, CONFIG_SYS_SDRAM0_MB0CF);
2891         mtsdram(SDRAM_MB1CF, CONFIG_SYS_SDRAM0_MB1CF);
2892         mtsdram(SDRAM_MB2CF, CONFIG_SYS_SDRAM0_MB2CF);
2893         mtsdram(SDRAM_MB3CF, CONFIG_SYS_SDRAM0_MB3CF);
2894
2895         /* Set Memory Clock Timing Register */
2896
2897         mtsdram(SDRAM_CLKTR, CONFIG_SYS_SDRAM0_CLKTR);
2898
2899         /* Set Refresh Time Register */
2900
2901         mtsdram(SDRAM_RTR, CONFIG_SYS_SDRAM0_RTR);
2902
2903         /* Set SDRAM Timing Registers */
2904
2905         mtsdram(SDRAM_SDTR1, CONFIG_SYS_SDRAM0_SDTR1);
2906         mtsdram(SDRAM_SDTR2, CONFIG_SYS_SDRAM0_SDTR2);
2907         mtsdram(SDRAM_SDTR3, CONFIG_SYS_SDRAM0_SDTR3);
2908
2909         /* Set Mode and Extended Mode Registers */
2910
2911         mtsdram(SDRAM_MMODE, CONFIG_SYS_SDRAM0_MMODE);
2912         mtsdram(SDRAM_MEMODE, CONFIG_SYS_SDRAM0_MEMODE);
2913
2914         /* Set Memory Controller Options 1 Register */
2915
2916         mtsdram(SDRAM_MCOPT1, CONFIG_SYS_SDRAM0_MCOPT1);
2917
2918         /* Set Manual Initialization Control Registers */
2919
2920         mtsdram(SDRAM_INITPLR0, CONFIG_SYS_SDRAM0_INITPLR0);
2921         mtsdram(SDRAM_INITPLR1, CONFIG_SYS_SDRAM0_INITPLR1);
2922         mtsdram(SDRAM_INITPLR2, CONFIG_SYS_SDRAM0_INITPLR2);
2923         mtsdram(SDRAM_INITPLR3, CONFIG_SYS_SDRAM0_INITPLR3);
2924         mtsdram(SDRAM_INITPLR4, CONFIG_SYS_SDRAM0_INITPLR4);
2925         mtsdram(SDRAM_INITPLR5, CONFIG_SYS_SDRAM0_INITPLR5);
2926         mtsdram(SDRAM_INITPLR6, CONFIG_SYS_SDRAM0_INITPLR6);
2927         mtsdram(SDRAM_INITPLR7, CONFIG_SYS_SDRAM0_INITPLR7);
2928         mtsdram(SDRAM_INITPLR8, CONFIG_SYS_SDRAM0_INITPLR8);
2929         mtsdram(SDRAM_INITPLR9, CONFIG_SYS_SDRAM0_INITPLR9);
2930         mtsdram(SDRAM_INITPLR10, CONFIG_SYS_SDRAM0_INITPLR10);
2931         mtsdram(SDRAM_INITPLR11, CONFIG_SYS_SDRAM0_INITPLR11);
2932         mtsdram(SDRAM_INITPLR12, CONFIG_SYS_SDRAM0_INITPLR12);
2933         mtsdram(SDRAM_INITPLR13, CONFIG_SYS_SDRAM0_INITPLR13);
2934         mtsdram(SDRAM_INITPLR14, CONFIG_SYS_SDRAM0_INITPLR14);
2935         mtsdram(SDRAM_INITPLR15, CONFIG_SYS_SDRAM0_INITPLR15);
2936
2937         /* Set On-Die Termination Registers */
2938
2939         mtsdram(SDRAM_CODT, CONFIG_SYS_SDRAM0_CODT);
2940         mtsdram(SDRAM_MODT0, CONFIG_SYS_SDRAM0_MODT0);
2941         mtsdram(SDRAM_MODT1, CONFIG_SYS_SDRAM0_MODT1);
2942
2943         /* Set Write Timing Register */
2944
2945         mtsdram(SDRAM_WRDTR, CONFIG_SYS_SDRAM0_WRDTR);
2946
2947         /*
2948          * Start Initialization by SDRAM0_MCOPT2[SREN] = 0 and
2949          * SDRAM0_MCOPT2[IPTR] = 1
2950          */
2951
2952         mtsdram(SDRAM_MCOPT2, (SDRAM_MCOPT2_SREN_EXIT |
2953                                SDRAM_MCOPT2_IPTR_EXECUTE));
2954
2955         /*
2956          * Poll SDRAM0_MCSTAT[MIC] for assertion to indicate the
2957          * completion of initialization.
2958          */
2959
2960         do {
2961                 mfsdram(SDRAM_MCSTAT, val);
2962         } while ((val & SDRAM_MCSTAT_MIC_MASK) != SDRAM_MCSTAT_MIC_COMP);
2963
2964         /* Set Delay Control Registers */
2965
2966         mtsdram(SDRAM_DLCR, CONFIG_SYS_SDRAM0_DLCR);
2967
2968 #if !defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2969         mtsdram(SDRAM_RDCC, CONFIG_SYS_SDRAM0_RDCC);
2970         mtsdram(SDRAM_RQDC, CONFIG_SYS_SDRAM0_RQDC);
2971         mtsdram(SDRAM_RFDC, CONFIG_SYS_SDRAM0_RFDC);
2972 #endif /* !CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2973
2974         /*
2975          * Enable Controller by SDRAM0_MCOPT2[DCEN] = 1:
2976          */
2977
2978         mfsdram(SDRAM_MCOPT2, val);
2979         mtsdram(SDRAM_MCOPT2, val | SDRAM_MCOPT2_DCEN_ENABLE);
2980
2981 #if defined(CONFIG_440)
2982         /*
2983          * Program TLB entries with caches enabled, for best performace
2984          * while auto-calibrating and ECC generation
2985          */
2986         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), 0);
2987 #endif
2988
2989 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
2990 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
2991         /*------------------------------------------------------------------
2992          | DQS calibration.
2993          +-----------------------------------------------------------------*/
2994         DQS_autocalibration();
2995 #endif /* !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) */
2996 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
2997
2998         /*
2999          * Now complete RDSS configuration as mentioned on page 7 of the AMCC
3000          * PowerPC440SP/SPe DDR2 application note:
3001          * "DDR1/DDR2 Initialization Sequence and Dynamic Tuning"
3002          */
3003         update_rdcc();
3004
3005 #if defined(CONFIG_DDR_ECC)
3006         do_program_ecc(0);
3007 #endif /* defined(CONFIG_DDR_ECC) */
3008
3009 #if defined(CONFIG_440)
3010         /*
3011          * Now after initialization (auto-calibration and ECC generation)
3012          * remove the TLB entries with caches enabled and program again with
3013          * desired cache functionality
3014          */
3015         remove_tlb(0, (CONFIG_SYS_MBYTES_SDRAM << 20));
3016         program_tlb(0, 0, (CONFIG_SYS_MBYTES_SDRAM << 20), MY_TLB_WORD2_I_ENABLE);
3017 #endif
3018
3019         ppc4xx_ibm_ddr2_register_dump();
3020
3021 #if defined(CONFIG_PPC4xx_DDR_AUTOCALIBRATION)
3022         /*
3023          * Clear potential errors resulting from auto-calibration.
3024          * If not done, then we could get an interrupt later on when
3025          * exceptions are enabled.
3026          */
3027         set_mcsr(get_mcsr());
3028 #endif /* CONFIG_PPC4xx_DDR_AUTOCALIBRATION */
3029
3030 #endif /* !defined(CONFIG_NAND_U_BOOT) || defined(CONFIG_NAND_SPL) */
3031
3032         return (CONFIG_SYS_MBYTES_SDRAM << 20);
3033 }
3034 #endif /* CONFIG_SPD_EEPROM */
3035
3036 #if !defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL)
3037 #if defined(CONFIG_440)
3038 u32 mfdcr_any(u32 dcr)
3039 {
3040         u32 val;
3041
3042         switch (dcr) {
3043         case SDRAM_R0BAS + 0:
3044                 val = mfdcr(SDRAM_R0BAS + 0);
3045                 break;
3046         case SDRAM_R0BAS + 1:
3047                 val = mfdcr(SDRAM_R0BAS + 1);
3048                 break;
3049         case SDRAM_R0BAS + 2:
3050                 val = mfdcr(SDRAM_R0BAS + 2);
3051                 break;
3052         case SDRAM_R0BAS + 3:
3053                 val = mfdcr(SDRAM_R0BAS + 3);
3054                 break;
3055         default:
3056                 printf("DCR %d not defined in case statement!!!\n", dcr);
3057                 val = 0; /* just to satisfy the compiler */
3058         }
3059
3060         return val;
3061 }
3062
3063 void mtdcr_any(u32 dcr, u32 val)
3064 {
3065         switch (dcr) {
3066         case SDRAM_R0BAS + 0:
3067                 mtdcr(SDRAM_R0BAS + 0, val);
3068                 break;
3069         case SDRAM_R0BAS + 1:
3070                 mtdcr(SDRAM_R0BAS + 1, val);
3071                 break;
3072         case SDRAM_R0BAS + 2:
3073                 mtdcr(SDRAM_R0BAS + 2, val);
3074                 break;
3075         case SDRAM_R0BAS + 3:
3076                 mtdcr(SDRAM_R0BAS + 3, val);
3077                 break;
3078         default:
3079                 printf("DCR %d not defined in case statement!!!\n", dcr);
3080         }
3081 }
3082 #endif /* defined(CONFIG_440) */
3083 #endif /* !defined(CONFIG_NAND_U_BOOT) &&  !defined(CONFIG_NAND_SPL) */
3084
3085 inline void ppc4xx_ibm_ddr2_register_dump(void)
3086 {
3087 #if defined(DEBUG)
3088         printf("\nPPC4xx IBM DDR2 Register Dump:\n");
3089
3090 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3091      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3092         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R0BAS);
3093         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R1BAS);
3094         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R2BAS);
3095         PPC4xx_IBM_DDR2_DUMP_MQ_REGISTER(R3BAS);
3096 #endif /* (defined(CONFIG_440SP) || ... */
3097 #if defined(CONFIG_405EX)
3098         PPC4xx_IBM_DDR2_DUMP_REGISTER(BESR);
3099         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARL);
3100         PPC4xx_IBM_DDR2_DUMP_REGISTER(BEARH);
3101         PPC4xx_IBM_DDR2_DUMP_REGISTER(WMIRQ);
3102         PPC4xx_IBM_DDR2_DUMP_REGISTER(PLBOPT);
3103         PPC4xx_IBM_DDR2_DUMP_REGISTER(PUABA);
3104 #endif /* defined(CONFIG_405EX) */
3105         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB0CF);
3106         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB1CF);
3107         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB2CF);
3108         PPC4xx_IBM_DDR2_DUMP_REGISTER(MB3CF);
3109         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCSTAT);
3110         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT1);
3111         PPC4xx_IBM_DDR2_DUMP_REGISTER(MCOPT2);
3112         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT0);
3113         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT1);
3114         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT2);
3115         PPC4xx_IBM_DDR2_DUMP_REGISTER(MODT3);
3116         PPC4xx_IBM_DDR2_DUMP_REGISTER(CODT);
3117 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3118      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3119         PPC4xx_IBM_DDR2_DUMP_REGISTER(VVPR);
3120         PPC4xx_IBM_DDR2_DUMP_REGISTER(OPARS);
3121         /*
3122          * OPART is only used as a trigger register.
3123          *
3124          * No data is contained in this register, and reading or writing
3125          * to is can cause bad things to happen (hangs). Just skip it and
3126          * report "N/A".
3127          */
3128         printf("%20s = N/A\n", "SDRAM_OPART");
3129 #endif /* defined(CONFIG_440SP) || ... */
3130         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTR);
3131         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR0);
3132         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR1);
3133         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR2);
3134         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR3);
3135         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR4);
3136         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR5);
3137         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR6);
3138         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR7);
3139         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR8);
3140         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR9);
3141         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR10);
3142         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR11);
3143         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR12);
3144         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR13);
3145         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR14);
3146         PPC4xx_IBM_DDR2_DUMP_REGISTER(INITPLR15);
3147         PPC4xx_IBM_DDR2_DUMP_REGISTER(RQDC);
3148         PPC4xx_IBM_DDR2_DUMP_REGISTER(RFDC);
3149         PPC4xx_IBM_DDR2_DUMP_REGISTER(RDCC);
3150         PPC4xx_IBM_DDR2_DUMP_REGISTER(DLCR);
3151         PPC4xx_IBM_DDR2_DUMP_REGISTER(CLKTR);
3152         PPC4xx_IBM_DDR2_DUMP_REGISTER(WRDTR);
3153         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR1);
3154         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR2);
3155         PPC4xx_IBM_DDR2_DUMP_REGISTER(SDTR3);
3156         PPC4xx_IBM_DDR2_DUMP_REGISTER(MMODE);
3157         PPC4xx_IBM_DDR2_DUMP_REGISTER(MEMODE);
3158         PPC4xx_IBM_DDR2_DUMP_REGISTER(ECCES);
3159 #if (defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \
3160      defined(CONFIG_460EX) || defined(CONFIG_460GT))
3161         PPC4xx_IBM_DDR2_DUMP_REGISTER(CID);
3162 #endif /* defined(CONFIG_440SP) || ... */
3163         PPC4xx_IBM_DDR2_DUMP_REGISTER(RID);
3164         PPC4xx_IBM_DDR2_DUMP_REGISTER(FCSR);
3165         PPC4xx_IBM_DDR2_DUMP_REGISTER(RTSR);
3166 #endif /* defined(DEBUG) */
3167 }