arch/x86/cpu/lapic.c

   1 /*
   2  * From coreboot file of same name
   3  *
   4  * Copyright (C) 2008-2009 coresystems GmbH
   5  * Copyright (C) 2014 Google, Inc
   6  *
   7  * SPDX-License-Identifier:     GPL-2.0
   8  */
   9
  10 #include <common.h>
  11 #include <asm/io.h>
  12 #include <asm/lapic.h>
  13 #include <asm/msr.h>
  14 #include <asm/msr-index.h>
  15 #include <asm/post.h>
  16
  17 unsigned long lapic_read(unsigned long reg)
  18 {
  19         return readl(LAPIC_DEFAULT_BASE + reg);
  20 }
  21
  22 #define xchg(ptr, v)    ((__typeof__(*(ptr)))__xchg((unsigned long)(v), (ptr), \
  23                                                     sizeof(*(ptr))))
  24
  25 struct __xchg_dummy     { unsigned long a[100]; };
  26 #define __xg(x)         ((struct __xchg_dummy *)(x))
  27
  28 /*
  29  * Note: no "lock" prefix even on SMP. xchg always implies lock anyway.
  30  *
  31  * Note 2: xchg has side effect, so that attribute volatile is necessary,
  32  *         but generally the primitive is invalid, *ptr is output argument.
  33  */
  34 static inline unsigned long __xchg(unsigned long x, volatile void *ptr,
  35                                    int size)
  36 {
  37         switch (size) {
  38         case 1:
  39                 __asm__ __volatile__("xchgb %b0,%1"
  40                         : "=q" (x)
  41                         : "m" (*__xg(ptr)), "0" (x)
  42                         : "memory");
  43                 break;
  44         case 2:
  45                 __asm__ __volatile__("xchgw %w0,%1"
  46                         : "=r" (x)
  47                         : "m" (*__xg(ptr)), "0" (x)
  48                         : "memory");
  49                 break;
  50         case 4:
  51                 __asm__ __volatile__("xchgl %0,%1"
  52                         : "=r" (x)
  53                         : "m" (*__xg(ptr)), "0" (x)
  54                         : "memory");
  55                 break;
  56         }
  57
  58         return x;
  59 }
  60
  61 void lapic_write(unsigned long reg, unsigned long v)
  62 {
  63         (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE + reg), v);
  64 }
  65
  66 void enable_lapic(void)
  67 {
  68         msr_t msr;
  69
  70         msr = msr_read(MSR_IA32_APICBASE);
  71         msr.hi &= 0xffffff00;
  72         msr.lo |= MSR_IA32_APICBASE_ENABLE;
  73         msr.lo &= ~MSR_IA32_APICBASE_BASE;
  74         msr.lo |= LAPIC_DEFAULT_BASE;
  75         msr_write(MSR_IA32_APICBASE, msr);
  76 }
  77
  78 void disable_lapic(void)
  79 {
  80         msr_t msr;
  81
  82         msr = msr_read(MSR_IA32_APICBASE);
  83         msr.lo &= ~MSR_IA32_APICBASE_ENABLE;
  84         msr_write(MSR_IA32_APICBASE, msr);
  85 }
  86
  87 unsigned long lapicid(void)
  88 {
  89         return lapic_read(LAPIC_ID) >> 24;
  90 }
  91
  92 static void lapic_wait_icr_idle(void)
  93 {
  94         do { } while (lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY);
  95 }
  96
  97 int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
  98 {
  99         int timeout;
 100         unsigned long status;
 101         int result;
 102
 103         lapic_wait_icr_idle();
 104         lapic_write(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
 105         lapic_write(LAPIC_ICR, LAPIC_DM_REMRD | (reg >> 4));
 106
 107         timeout = 0;
 108         do {
 109                 status = lapic_read(LAPIC_ICR) & LAPIC_ICR_RR_MASK;
 110         } while (status == LAPIC_ICR_RR_INPROG && timeout++ < 1000);
 111
 112         result = -1;
 113         if (status == LAPIC_ICR_RR_VALID) {
 114                 *pvalue = lapic_read(LAPIC_RRR);
 115                 result = 0;
 116         }
 117
 118         return result;
 119 }
 120
 121 void lapic_setup(void)
 122 {
 123 #ifdef CONFIG_SMP
 124         /* Only Pentium Pro and later have those MSR stuff */
 125         debug("Setting up local apic: ");
 126
 127         /* Enable the local apic */
 128         enable_lapic();
 129
 130         /* Set Task Priority to 'accept all' */
 131         lapic_write(LAPIC_TASKPRI,
 132                     lapic_read(LAPIC_TASKPRI) & ~LAPIC_TPRI_MASK);
 133
 134         /* Put the local apic in virtual wire mode */
 135         lapic_write(LAPIC_SPIV, (lapic_read(LAPIC_SPIV) &
 136                     ~(LAPIC_VECTOR_MASK)) | LAPIC_SPIV_ENABLE);
 137         lapic_write(LAPIC_LVT0, (lapic_read(LAPIC_LVT0) &
 138                     ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
 139                     LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
 140                     LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
 141                     LAPIC_DELIVERY_MODE_MASK)) |
 142                     (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
 143                     LAPIC_DELIVERY_MODE_EXTINT));
 144         lapic_write(LAPIC_LVT1, (lapic_read(LAPIC_LVT1) &
 145                     ~(LAPIC_LVT_MASKED | LAPIC_LVT_LEVEL_TRIGGER |
 146                     LAPIC_LVT_REMOTE_IRR | LAPIC_INPUT_POLARITY |
 147                     LAPIC_SEND_PENDING | LAPIC_LVT_RESERVED_1 |
 148                     LAPIC_DELIVERY_MODE_MASK)) |
 149                     (LAPIC_LVT_REMOTE_IRR | LAPIC_SEND_PENDING |
 150                     LAPIC_DELIVERY_MODE_NMI));
 151
 152         debug("apic_id: 0x%02lx, ", lapicid());
 153 #else /* !CONFIG_SMP */
 154         /* Only Pentium Pro and later have those MSR stuff */
 155         debug("Disabling local apic: ");
 156         disable_lapic();
 157 #endif /* CONFIG_SMP */
 158         debug("done.\n");
 159         post_code(POST_LAPIC);
 160 }