arch/x86/dts/chromebox_panther.dts

   1 /dts-v1/;
   2
   3 /include/ "skeleton.dtsi"
   4 /include/ "serial.dtsi"
   5 /include/ "rtc.dtsi"
   6
   7 / {
   8         model = "Google Panther";
   9         compatible = "google,panther", "intel,haswell";
  10
  11         aliases {
  12                 spi0 = "/spi";
  13         };
  14
  15         config {
  16                 silent-console = <0>;
  17                 no-keyboard;
  18         };
  19
  20         gpioa {
  21                 compatible = "intel,ich6-gpio";
  22                 u-boot,dm-pre-reloc;
  23                 reg = <0 0x10>;
  24                 bank-name = "A";
  25         };
  26
  27         gpiob {
  28                 compatible = "intel,ich6-gpio";
  29                 u-boot,dm-pre-reloc;
  30                 reg = <0x30 0x10>;
  31                 bank-name = "B";
  32         };
  33
  34         gpioc {
  35                 compatible = "intel,ich6-gpio";
  36                 u-boot,dm-pre-reloc;
  37                 reg = <0x40 0x10>;
  38                 bank-name = "C";
  39         };
  40
  41         chosen {
  42                 stdout-path = "/serial";
  43         };
  44
  45         spi {
  46                 #address-cells = <1>;
  47                 #size-cells = <0>;
  48                 compatible = "intel,ich-spi";
  49                 spi-flash@0 {
  50                         #size-cells = <1>;
  51                         #address-cells = <1>;
  52                         reg = <0>;
  53                         compatible = "winbond,w25q64", "spi-flash";
  54                         memory-map = <0xff800000 0x00800000>;
  55                         rw-mrc-cache {
  56                                 label = "rw-mrc-cache";
  57                                 /* Alignment: 4k (for updating) */
  58                                 reg = <0x003e0000 0x00010000>;
  59                                 type = "wiped";
  60                                 wipe-value = [ff];
  61                         };
  62                 };
  63         };
  64
  65         tpm {
  66                 reg = <0xfed40000 0x5000>;
  67                 compatible = "infineon,slb9635lpc";
  68         };
  69
  70 };